3 * Copyright 2007,2008,2009 Free Software Foundation, Inc.
5 * This program is free software: you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation, either version 3 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 #include "app_common_v2.h"
24 #include "buffer_pool.h"
25 #include "memcpy_wa.h"
28 #include "print_rmon_regs.h"
35 volatile bool link_is_up = false; // eth handler sets this
36 int cpu_tx_buf_dest_port = PORT_ETH;
38 // If this is non-zero, this dbsm could be writing to the ethernet
39 dbsm_t *ac_could_be_sending_to_eth;
41 static unsigned char exp_seqno __attribute__((unused)) = 0;
44 sync_to_pps(const op_generic_t *p)
46 timesync_regs->sync_on_next_pps = 1;
47 //putstr("SYNC to PPS\n");
52 sync_every_pps(const op_generic_t *p)
55 timesync_regs->tick_control |= TSC_TRIGGER_EVERYPPS;
57 timesync_regs->tick_control &= ~TSC_TRIGGER_EVERYPPS;
63 config_mimo_cmd(const op_config_mimo_t *p)
65 clocks_mimo_config(p->flags);
70 set_reply_hdr(u2_eth_packet_t *reply_pkt, u2_eth_packet_t const *cmd_pkt)
72 reply_pkt->ehdr.dst = cmd_pkt->ehdr.src;
73 reply_pkt->ehdr.src = *ethernet_mac_addr();
74 reply_pkt->ehdr.ethertype = U2_ETHERTYPE;
75 reply_pkt->thdr.flags = 0;
76 reply_pkt->thdr.fifo_status = 0; // written by protocol engine
77 reply_pkt->thdr.seqno = 0; // written by protocol engine
78 reply_pkt->thdr.ack = 0; // written by protocol engine
79 u2p_set_word0(&reply_pkt->fixed, 0, CONTROL_CHAN);
80 reply_pkt->fixed.timestamp = timer_regs->time;
84 send_reply(unsigned char *reply, size_t reply_len)
89 // wait for buffer to become idle
90 hal_set_leds(0x4, 0x4);
91 while((buffer_pool_status->status & BPS_IDLE(CPU_TX_BUF)) == 0)
93 hal_set_leds(0x0, 0x4);
95 // copy reply into CPU_TX_BUF
96 memcpy_wa(buffer_ram(CPU_TX_BUF), reply, reply_len);
98 // wait until nobody else is sending to the ethernet
99 if (ac_could_be_sending_to_eth){
100 hal_set_leds(0x8, 0x8);
101 dbsm_wait_for_opening(ac_could_be_sending_to_eth);
102 hal_set_leds(0x0, 0x8);
106 printf("sending_reply to port %d, len = %d\n", cpu_tx_buf_dest_port, (int)reply_len);
107 print_buffer(buffer_ram(CPU_TX_BUF), reply_len/4);
111 bp_send_from_buf(CPU_TX_BUF, cpu_tx_buf_dest_port, 1, 0, reply_len/4);
113 // wait for it to complete (not long, it's a small pkt)
114 while((buffer_pool_status->status & (BPS_DONE(CPU_TX_BUF) | BPS_ERROR(CPU_TX_BUF))) == 0)
117 bp_clear_buf(CPU_TX_BUF);
122 op_id_cmd(const op_generic_t *p,
123 void *reply_payload, size_t reply_payload_space)
125 op_id_reply_t *r = (op_id_reply_t *) reply_payload;
126 if (reply_payload_space < sizeof(*r)) // no room
129 // Build reply subpacket
131 r->opcode = OP_ID_REPLY;
132 r->len = sizeof(op_id_reply_t);
134 r->addr = *ethernet_mac_addr();
135 r->hw_rev = (u2_hw_rev_major << 8) | u2_hw_rev_minor;
136 // r->fpga_md5sum = ; // FIXME
137 // r->sw_md5sum = ; // FIXME
144 config_tx_v2_cmd(const op_config_tx_v2_t *p,
145 void *reply_payload, size_t reply_payload_space)
147 op_config_tx_reply_v2_t *r = (op_config_tx_reply_v2_t *) reply_payload;
148 if (reply_payload_space < sizeof(*r))
151 struct tune_result tune_result;
152 memset(&tune_result, 0, sizeof(tune_result));
156 if (p->valid & CFGV_GAIN){
157 ok &= db_set_gain(tx_dboard, p->gain);
160 if (p->valid & CFGV_FREQ){
161 bool was_streaming = is_streaming();
165 u2_fxpt_freq_t f = u2_fxpt_freq_from_hilo(p->freq_hi, p->freq_lo);
166 bool tune_ok = db_tune(tx_dboard, f, &tune_result);
168 print_tune_result("Tx", tune_ok, f, &tune_result);
174 if (p->valid & CFGV_INTERP_DECIM){
175 int interp = p->interp;
181 interp = interp >> 1;
186 interp = interp >> 1;
189 if (interp < MIN_CIC_INTERP || interp > MAX_CIC_INTERP)
192 dsp_tx_regs->interp_rate = (hb1<<9) | (hb2<<8) | interp;
193 // printf("Interp: %d, register %d\n", p->interp, (hb1<<9) | (hb2<<8) | interp);
197 if (p->valid & CFGV_SCALE_IQ){
198 dsp_tx_regs->scale_iq = p->scale_iq;
201 // Build reply subpacket
203 r->opcode = OP_CONFIG_TX_REPLY_V2;
207 r->inverted = tune_result.inverted;
208 r->baseband_freq_hi = u2_fxpt_freq_hi(tune_result.baseband_freq);
209 r->baseband_freq_lo = u2_fxpt_freq_lo(tune_result.baseband_freq);
210 r->duc_freq_hi = u2_fxpt_freq_hi(tune_result.dxc_freq);
211 r->duc_freq_lo = u2_fxpt_freq_lo(tune_result.dxc_freq);
212 r->residual_freq_hi = u2_fxpt_freq_hi(tune_result.residual_freq);
213 r->residual_freq_lo = u2_fxpt_freq_lo(tune_result.residual_freq);
218 config_rx_v2_cmd(const op_config_rx_v2_t *p,
219 void *reply_payload, size_t reply_payload_space)
221 op_config_rx_reply_v2_t *r = (op_config_rx_reply_v2_t *) reply_payload;
222 if (reply_payload_space < sizeof(*r))
225 struct tune_result tune_result;
226 memset(&tune_result, 0, sizeof(tune_result));
230 if (p->valid & CFGV_GAIN){
231 ok &= db_set_gain(rx_dboard, p->gain);
234 if (p->valid & CFGV_FREQ){
235 bool was_streaming = is_streaming();
239 u2_fxpt_freq_t f = u2_fxpt_freq_from_hilo(p->freq_hi, p->freq_lo);
240 bool tune_ok = db_tune(rx_dboard, f, &tune_result);
242 print_tune_result("Rx", tune_ok, f, &tune_result);
248 if (p->valid & CFGV_INTERP_DECIM){
249 int decim = p->decim;
263 if (decim < MIN_CIC_DECIM || decim > MAX_CIC_DECIM)
266 dsp_rx_regs->decim_rate = (hb1<<9) | (hb2<<8) | decim;
267 // printf("Decim: %d, register %d\n", p->decim, (hb1<<9) | (hb2<<8) | decim);
271 if (p->valid & CFGV_SCALE_IQ){
272 dsp_rx_regs->scale_iq = p->scale_iq;
275 // Build reply subpacket
277 r->opcode = OP_CONFIG_RX_REPLY_V2;
281 r->inverted = tune_result.inverted;
282 r->baseband_freq_hi = u2_fxpt_freq_hi(tune_result.baseband_freq);
283 r->baseband_freq_lo = u2_fxpt_freq_lo(tune_result.baseband_freq);
284 r->ddc_freq_hi = u2_fxpt_freq_hi(tune_result.dxc_freq);
285 r->ddc_freq_lo = u2_fxpt_freq_lo(tune_result.dxc_freq);
286 r->residual_freq_hi = u2_fxpt_freq_hi(tune_result.residual_freq);
287 r->residual_freq_lo = u2_fxpt_freq_lo(tune_result.residual_freq);
293 read_time_cmd(const op_generic_t *p,
294 void *reply_payload, size_t reply_payload_space)
296 op_read_time_reply_t *r = (op_read_time_reply_t *) reply_payload;
297 if (reply_payload_space < sizeof(*r))
300 r->opcode = OP_READ_TIME_REPLY;
303 r->time = timer_regs->time;
309 fill_db_info(u2_db_info_t *p, const struct db_base *db)
312 p->freq_min_hi = u2_fxpt_freq_hi(db->freq_min);
313 p->freq_min_lo = u2_fxpt_freq_lo(db->freq_min);
314 p->freq_max_hi = u2_fxpt_freq_hi(db->freq_max);
315 p->freq_max_lo = u2_fxpt_freq_lo(db->freq_max);
316 p->gain_min = db->gain_min;
317 p->gain_max = db->gain_max;
318 p->gain_step_size = db->gain_step_size;
322 dboard_info_cmd(const op_generic_t *p,
323 void *reply_payload, size_t reply_payload_space)
325 op_dboard_info_reply_t *r = (op_dboard_info_reply_t *) reply_payload;
326 if (reply_payload_space < sizeof(*r))
329 r->opcode = OP_DBOARD_INFO_REPLY;
334 fill_db_info(&r->tx_db_info, tx_dboard);
335 fill_db_info(&r->rx_db_info, rx_dboard);
341 peek_cmd(const op_peek_t *p,
342 void *reply_payload, size_t reply_payload_space)
344 op_generic_t *r = (op_generic_t *) reply_payload;
346 //putstr("peek: addr="); puthex32(p->addr);
347 //printf(" bytes=%u\n", p->bytes);
349 if ((reply_payload_space < (sizeof(*r) + p->bytes)) ||
350 p->bytes > MAX_SUBPKT_LEN - sizeof(op_generic_t)) {
351 putstr("peek: insufficient reply packet space\n");
352 return 0; // FIXME do partial read?
355 r->opcode = OP_PEEK_REPLY;
356 r->len = sizeof(*r)+p->bytes;
360 memcpy_wa(reply_payload+sizeof(*r), (void *)p->addr, p->bytes);
366 poke_cmd(const op_poke_t *p)
368 int bytes = p->len - sizeof(*p);
369 //putstr("poke: addr="); puthex32(p->addr);
370 //printf(" bytes=%u\n", bytes);
372 uint8_t *src = (uint8_t *)p + sizeof(*p);
373 memcpy_wa((void *)p->addr, src, bytes);
379 set_lo_offset_cmd(const op_freq_t *p)
381 u2_fxpt_freq_t f = u2_fxpt_freq_from_hilo(p->freq_hi, p->freq_lo);
382 if (p->opcode == OP_SET_TX_LO_OFFSET)
383 return db_set_lo_offset(tx_dboard, f);
385 return db_set_lo_offset(rx_dboard, f);
389 gpio_read_cmd(const op_gpio_t *p,
390 void *reply_payload, size_t reply_payload_space)
392 op_gpio_read_reply_t *r = (op_gpio_read_reply_t *) reply_payload;
393 if (reply_payload_space < sizeof(*r)) // no room
396 // Build reply subpacket
398 r->opcode = OP_GPIO_READ_REPLY;
399 r->len = sizeof(op_gpio_read_reply_t);
403 r->value = hal_gpio_read(p->bank);
409 generic_reply(const op_generic_t *p,
410 void *reply_payload, size_t reply_payload_space,
413 op_generic_t *r = (op_generic_t *) reply_payload;
414 if (reply_payload_space < sizeof(*r))
417 r->opcode = p->opcode | OP_REPLY_BIT;
426 add_eop(void *reply_payload, size_t reply_payload_space)
428 op_generic_t *r = (op_generic_t *) reply_payload;
429 if (reply_payload_space < sizeof(*r))
441 handle_control_chan_frame(u2_eth_packet_t *pkt, size_t len)
443 unsigned char reply[sizeof(u2_eth_packet_t) + 4 * sizeof(u2_subpkt_t)] _AL4;
444 unsigned char *reply_payload = &reply[sizeof(u2_eth_packet_t)];
445 int reply_payload_space = sizeof(reply) - sizeof(u2_eth_packet_t);
448 memset(reply, 0, sizeof(reply));
449 set_reply_hdr((u2_eth_packet_t *) reply, pkt);
451 // point to beginning of payload (subpackets)
452 unsigned char *payload = ((unsigned char *) pkt) + sizeof(u2_eth_packet_t);
453 int payload_len = len - sizeof(u2_eth_packet_t);
455 size_t subpktlen = 0;
458 while (payload_len >= sizeof(op_generic_t)){
459 const op_generic_t *gp = (const op_generic_t *) payload;
462 // printf("\nopcode = %d\n", gp->opcode);
465 case OP_EOP: // end of subpackets
466 goto end_of_subpackets;
469 subpktlen = op_id_cmd(gp, reply_payload, reply_payload_space);
472 case OP_CONFIG_TX_V2:
473 subpktlen = config_tx_v2_cmd((op_config_tx_v2_t *) payload, reply_payload, reply_payload_space);
476 case OP_CONFIG_RX_V2:
477 subpktlen = config_rx_v2_cmd((op_config_rx_v2_t *) payload, reply_payload, reply_payload_space);
480 case OP_START_RX_STREAMING:
481 start_rx_streaming_cmd(&pkt->ehdr.src, (op_start_rx_streaming_t *) payload);
490 case OP_BURN_MAC_ADDR:
491 ok = ethernet_set_mac_addr(&((op_burn_mac_addr_t *)payload)->addr);
495 ok = config_mimo_cmd((op_config_mimo_t *) payload);
499 subpktlen = read_time_cmd(gp, reply_payload, reply_payload_space);
503 subpktlen = dboard_info_cmd(gp, reply_payload, reply_payload_space);
507 sync_to_pps((op_generic_t *) payload);
512 subpktlen = peek_cmd((op_peek_t *)payload, reply_payload, reply_payload_space);
516 ok = poke_cmd((op_poke_t *)payload);
519 case OP_SET_TX_LO_OFFSET:
520 case OP_SET_RX_LO_OFFSET:
521 ok = set_lo_offset_cmd((op_freq_t *)payload);
529 case OP_SYNC_EVERY_PPS:
530 ok = sync_every_pps((op_generic_t *) payload);
533 case OP_GPIO_SET_DDR:
535 hal_gpio_set_ddr(((op_gpio_t *)payload)->bank,
536 ((op_gpio_t *)payload)->value,
537 ((op_gpio_t *)payload)->mask);
540 case OP_GPIO_SET_SELS:
542 hal_gpio_set_sels(((op_gpio_set_sels_t *)payload)->bank,
543 (char *)(&((op_gpio_set_sels_t *)payload)->sels));
547 subpktlen = gpio_read_cmd((op_gpio_t *) payload, reply_payload, reply_payload_space);
552 hal_gpio_write(((op_gpio_t *)payload)->bank,
553 ((op_gpio_t *)payload)->value,
554 ((op_gpio_t *)payload)->mask);
559 dsp_rx_regs->gpio_stream_enable = (uint32_t)((op_gpio_t *)payload)->value;
562 // Add new opcode handlers here
565 subpktlen = generic_reply(gp, reply_payload, reply_payload_space, ok);
569 printf("app_common_v2: unhandled opcode = %d\n", gp->opcode);
573 int t = (gp->len + 3) & ~3; // bump to a multiple of 4
577 subpktlen = (subpktlen + 3) & ~3; // bump to a multiple of 4
578 reply_payload += subpktlen;
579 reply_payload_space -= subpktlen;
584 // add the EOP marker
585 subpktlen = add_eop(reply_payload, reply_payload_space);
586 subpktlen = (subpktlen + 3) & ~3; // bump to a multiple of 4
587 reply_payload += subpktlen;
588 reply_payload_space -= subpktlen;
590 send_reply(reply, reply_payload - reply);
595 * Called when an ethernet packet is received.
596 * Return true if we handled it here, otherwise
597 * it'll be passed on to the DSP Tx pipe
600 eth_pkt_inspector(dbsm_t *sm, int bufno)
602 u2_eth_packet_t *pkt = (u2_eth_packet_t *) buffer_ram(bufno);
603 size_t byte_len = (buffer_pool_status->last_line[bufno] - 1) * 4;
605 //static size_t last_len = 0;
607 // hal_toggle_leds(0x1);
609 // inspect rcvd frame and figure out what do do.
611 if (pkt->ehdr.ethertype != U2_ETHERTYPE)
612 return true; // ignore, probably bogus PAUSE frame from MAC
614 int chan = u2p_chan(&pkt->fixed);
618 handle_control_chan_frame(pkt, byte_len);
619 return true; // we handled the packet
626 if (byte_len != last_len){
627 printf("Len: %d last: %d\n", byte_len, last_len);
632 if((pkt->thdr.seqno) == exp_seqno){
638 //printf("S%d %d ",exp_seqno,pkt->thdr.seqno);
639 exp_seqno = pkt->thdr.seqno + 1;
642 return false; // pass it on to Tx DSP
648 * Called when eth phy state changes (w/ interrupts disabled)
651 link_changed_callback(int speed)
653 link_is_up = speed != 0;
654 hal_set_leds(link_is_up ? LED_RJ45 : 0x0, LED_RJ45);
655 printf("\neth link changed: speed = %d\n", speed);
660 print_tune_result(char *msg, bool tune_ok,
661 u2_fxpt_freq_t target_freq, struct tune_result *r)
664 printf("db_tune %s %s\n", msg, tune_ok ? "true" : "false");
665 putstr(" target_freq "); print_fxpt_freq(target_freq); newline();
666 putstr(" baseband_freq "); print_fxpt_freq(r->baseband_freq); newline();
667 putstr(" dxc_freq "); print_fxpt_freq(r->dxc_freq); newline();
668 putstr(" residual_freq "); print_fxpt_freq(r->residual_freq); newline();
669 printf(" inverted %s\n", r->inverted ? "true" : "false");