3 * Copyright 2007,2008 Free Software Foundation, Inc.
5 * This program is free software: you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation, either version 3 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 #include "app_common_v2.h"
24 #include "buffer_pool.h"
25 #include "memcpy_wa.h"
28 #include "print_rmon_regs.h"
35 volatile bool link_is_up = false; // eth handler sets this
36 int cpu_tx_buf_dest_port = PORT_ETH;
38 // If this is non-zero, this dbsm could be writing to the ethernet
39 dbsm_t *ac_could_be_sending_to_eth;
41 static unsigned char exp_seqno __attribute__((unused)) = 0;
44 burn_mac_addr(const op_burn_mac_addr_t *p)
46 return ethernet_set_mac_addr(&p->addr);
50 sync_to_pps(const op_generic_t *p)
52 timesync_regs->sync_on_next_pps = 1;
53 putstr("SYNC to PPS\n");
58 config_mimo_cmd(const op_config_mimo_t *p)
60 clocks_mimo_config(p->flags);
65 set_reply_hdr(u2_eth_packet_t *reply_pkt, u2_eth_packet_t const *cmd_pkt)
67 reply_pkt->ehdr.dst = cmd_pkt->ehdr.src;
68 reply_pkt->ehdr.ethertype = U2_ETHERTYPE;
69 reply_pkt->thdr.flags = 0;
70 reply_pkt->thdr.fifo_status = 0; // written by protocol engine
71 reply_pkt->thdr.seqno = 0; // written by protocol engine
72 reply_pkt->thdr.ack = 0; // written by protocol engine
73 u2p_set_word0(&reply_pkt->fixed, 0, CONTROL_CHAN);
74 reply_pkt->fixed.timestamp = timer_regs->time;
78 send_reply(unsigned char *reply, size_t reply_len)
83 // wait for buffer to become idle
84 hal_set_leds(0x4, 0x4);
85 while((buffer_pool_status->status & BPS_IDLE(CPU_TX_BUF)) == 0)
87 hal_set_leds(0x0, 0x4);
89 // copy reply into CPU_TX_BUF
90 memcpy_wa(buffer_ram(CPU_TX_BUF), reply, reply_len);
92 // wait until nobody else is sending to the ethernet
93 if (ac_could_be_sending_to_eth){
94 hal_set_leds(0x8, 0x8);
95 dbsm_wait_for_opening(ac_could_be_sending_to_eth);
96 hal_set_leds(0x0, 0x8);
100 printf("sending_reply to port %d, len = %d\n", cpu_tx_buf_dest_port, (int)reply_len);
101 print_buffer(buffer_ram(CPU_TX_BUF), reply_len/4);
105 bp_send_from_buf(CPU_TX_BUF, cpu_tx_buf_dest_port, 1, 0, reply_len/4);
107 // wait for it to complete (not long, it's a small pkt)
108 while((buffer_pool_status->status & (BPS_DONE(CPU_TX_BUF) | BPS_ERROR(CPU_TX_BUF))) == 0)
111 bp_clear_buf(CPU_TX_BUF);
116 op_id_cmd(const op_generic_t *p,
117 void *reply_payload, size_t reply_payload_space)
119 op_id_reply_t *r = (op_id_reply_t *) reply_payload;
120 if (reply_payload_space < sizeof(*r)) // no room
123 // Build reply subpacket
125 r->opcode = OP_ID_REPLY;
126 r->len = sizeof(op_id_reply_t);
128 r->addr = *ethernet_mac_addr();
129 r->hw_rev = (u2_hw_rev_major << 8) | u2_hw_rev_minor;
130 // r->fpga_md5sum = ; // FIXME
131 // r->sw_md5sum = ; // FIXME
138 config_tx_v2_cmd(const op_config_tx_v2_t *p,
139 void *reply_payload, size_t reply_payload_space)
141 op_config_tx_reply_v2_t *r = (op_config_tx_reply_v2_t *) reply_payload;
142 if (reply_payload_space < sizeof(*r))
145 struct tune_result tune_result;
146 memset(&tune_result, 0, sizeof(tune_result));
150 if (p->valid & CFGV_GAIN){
151 ok &= db_set_gain(tx_dboard, p->gain);
154 if (p->valid & CFGV_FREQ){
155 bool was_streaming = is_streaming();
159 u2_fxpt_freq_t f = u2_fxpt_freq_from_hilo(p->freq_hi, p->freq_lo);
160 bool tune_ok = db_tune(tx_dboard, f, &tune_result);
162 print_tune_result("Tx", tune_ok, f, &tune_result);
168 if (p->valid & CFGV_INTERP_DECIM){
169 int interp = p->interp;
175 interp = interp >> 1;
180 interp = interp >> 1;
183 if (interp < MIN_INTERP || interp > MAX_INTERP)
186 dsp_tx_regs->interp_rate = (hb1<<9) | (hb2<<8) | interp;
187 // printf("Interp: %d, register %d\n", p->interp, (hb1<<9) | (hb2<<8) | interp);
191 if (p->valid & CFGV_SCALE_IQ){
192 dsp_tx_regs->scale_iq = p->scale_iq;
195 // Build reply subpacket
197 r->opcode = OP_CONFIG_TX_REPLY_V2;
201 r->inverted = tune_result.inverted;
202 r->baseband_freq_hi = u2_fxpt_freq_hi(tune_result.baseband_freq);
203 r->baseband_freq_lo = u2_fxpt_freq_lo(tune_result.baseband_freq);
204 r->duc_freq_hi = u2_fxpt_freq_hi(tune_result.dxc_freq);
205 r->duc_freq_lo = u2_fxpt_freq_lo(tune_result.dxc_freq);
206 r->residual_freq_hi = u2_fxpt_freq_hi(tune_result.residual_freq);
207 r->residual_freq_lo = u2_fxpt_freq_lo(tune_result.residual_freq);
212 config_rx_v2_cmd(const op_config_rx_v2_t *p,
213 void *reply_payload, size_t reply_payload_space)
215 op_config_rx_reply_v2_t *r = (op_config_rx_reply_v2_t *) reply_payload;
216 if (reply_payload_space < sizeof(*r))
219 struct tune_result tune_result;
220 memset(&tune_result, 0, sizeof(tune_result));
224 if (p->valid & CFGV_GAIN){
225 ok &= db_set_gain(rx_dboard, p->gain);
228 if (p->valid & CFGV_FREQ){
229 bool was_streaming = is_streaming();
233 u2_fxpt_freq_t f = u2_fxpt_freq_from_hilo(p->freq_hi, p->freq_lo);
234 bool tune_ok = db_tune(rx_dboard, f, &tune_result);
236 print_tune_result("Rx", tune_ok, f, &tune_result);
242 if (p->valid & CFGV_INTERP_DECIM){
243 int decim = p->decim;
257 if (decim < MIN_DECIM || decim > MAX_DECIM)
260 dsp_rx_regs->decim_rate = (hb1<<9) | (hb2<<8) | decim;
261 // printf("Decim: %d, register %d\n", p->decim, (hb1<<9) | (hb2<<8) | decim);
265 if (p->valid & CFGV_SCALE_IQ){
266 dsp_rx_regs->scale_iq = p->scale_iq;
269 // Build reply subpacket
271 r->opcode = OP_CONFIG_RX_REPLY_V2;
275 r->inverted = tune_result.inverted;
276 r->baseband_freq_hi = u2_fxpt_freq_hi(tune_result.baseband_freq);
277 r->baseband_freq_lo = u2_fxpt_freq_lo(tune_result.baseband_freq);
278 r->ddc_freq_hi = u2_fxpt_freq_hi(tune_result.dxc_freq);
279 r->ddc_freq_lo = u2_fxpt_freq_lo(tune_result.dxc_freq);
280 r->residual_freq_hi = u2_fxpt_freq_hi(tune_result.residual_freq);
281 r->residual_freq_lo = u2_fxpt_freq_lo(tune_result.residual_freq);
287 read_time_cmd(const op_generic_t *p,
288 void *reply_payload, size_t reply_payload_space)
290 op_read_time_reply_t *r = (op_read_time_reply_t *) reply_payload;
291 if (reply_payload_space < sizeof(*r))
294 r->opcode = OP_READ_TIME_REPLY;
297 r->time = timer_regs->time;
303 fill_db_info(u2_db_info_t *p, const struct db_base *db)
306 p->freq_min_hi = u2_fxpt_freq_hi(db->freq_min);
307 p->freq_min_lo = u2_fxpt_freq_lo(db->freq_min);
308 p->freq_max_hi = u2_fxpt_freq_hi(db->freq_max);
309 p->freq_max_lo = u2_fxpt_freq_lo(db->freq_max);
310 p->gain_min = db->gain_min;
311 p->gain_max = db->gain_max;
312 p->gain_step_size = db->gain_step_size;
316 dboard_info_cmd(const op_generic_t *p,
317 void *reply_payload, size_t reply_payload_space)
319 op_dboard_info_reply_t *r = (op_dboard_info_reply_t *) reply_payload;
320 if (reply_payload_space < sizeof(*r))
323 r->opcode = OP_DBOARD_INFO_REPLY;
328 fill_db_info(&r->tx_db_info, tx_dboard);
329 fill_db_info(&r->rx_db_info, rx_dboard);
335 peek_cmd(const op_peek_t *p,
336 void *reply_payload, size_t reply_payload_space)
338 op_generic_t *r = (op_generic_t *) reply_payload;
340 putstr("peek: addr="); puthex32(p->addr);
341 printf(" bytes=%u\n", p->bytes);
343 if (reply_payload_space < (sizeof(*r) + p->bytes)) {
344 putstr("peek: insufficient reply packet space\n");
345 return 0; // FIXME do partial read?
348 r->opcode = OP_PEEK_REPLY;
349 r->len = sizeof(*r)+p->bytes;
353 memcpy_wa(reply_payload+sizeof(*r), (void *)p->addr, p->bytes);
359 poke_cmd(const op_poke_t *p)
361 int bytes = p->len - sizeof(*p);
362 putstr("poke: addr="); puthex32(p->addr);
363 printf(" bytes=%u\n", bytes);
365 uint8_t *src = (uint8_t *)p + sizeof(*p);
366 memcpy_wa((void *)p->addr, src, bytes);
372 generic_reply(const op_generic_t *p,
373 void *reply_payload, size_t reply_payload_space,
376 op_generic_t *r = (op_generic_t *) reply_payload;
377 if (reply_payload_space < sizeof(*r))
380 r->opcode = p->opcode | OP_REPLY_BIT;
389 add_eop(void *reply_payload, size_t reply_payload_space)
391 op_generic_t *r = (op_generic_t *) reply_payload;
392 if (reply_payload_space < sizeof(*r))
404 handle_control_chan_frame(u2_eth_packet_t *pkt, size_t len)
406 unsigned char reply[sizeof(u2_eth_packet_t) + 4 * sizeof(u2_subpkt_t)] _AL4;
407 unsigned char *reply_payload = &reply[sizeof(u2_eth_packet_t)];
408 int reply_payload_space = sizeof(reply) - sizeof(u2_eth_packet_t);
411 memset(reply, 0, sizeof(reply));
412 set_reply_hdr((u2_eth_packet_t *) reply, pkt);
414 // point to beginning of payload (subpackets)
415 unsigned char *payload = ((unsigned char *) pkt) + sizeof(u2_eth_packet_t);
416 int payload_len = len - sizeof(u2_eth_packet_t);
418 size_t subpktlen = 0;
420 while (payload_len >= sizeof(op_generic_t)){
421 const op_generic_t *gp = (const op_generic_t *) payload;
425 case OP_EOP: // end of subpackets
426 goto end_of_subpackets;
429 subpktlen = op_id_cmd(gp, reply_payload, reply_payload_space);
432 case OP_CONFIG_TX_V2:
433 subpktlen = config_tx_v2_cmd((op_config_tx_v2_t *) payload,
434 reply_payload, reply_payload_space);
437 case OP_CONFIG_RX_V2:
438 subpktlen = config_rx_v2_cmd((op_config_rx_v2_t *) payload,
439 reply_payload, reply_payload_space);
442 case OP_START_RX_STREAMING:
443 start_rx_streaming_cmd(&pkt->ehdr.src, (op_start_rx_streaming_t *) payload);
444 subpktlen = generic_reply(gp, reply_payload, reply_payload_space, true);
449 subpktlen = generic_reply(gp, reply_payload, reply_payload_space, true);
452 case OP_BURN_MAC_ADDR:
453 subpktlen = generic_reply(gp, reply_payload, reply_payload_space,
454 burn_mac_addr((op_burn_mac_addr_t *) payload));
458 subpktlen = generic_reply(gp, reply_payload, reply_payload_space,
459 config_mimo_cmd((op_config_mimo_t *) payload));
463 subpktlen = read_time_cmd(gp, reply_payload, reply_payload_space);
467 subpktlen = dboard_info_cmd(gp, reply_payload, reply_payload_space);
471 subpktlen = generic_reply(gp, reply_payload, reply_payload_space,
472 sync_to_pps((op_generic_t *) payload));
476 subpktlen = peek_cmd((op_peek_t *)payload, reply_payload, reply_payload_space);
480 subpktlen = generic_reply(gp, reply_payload, reply_payload_space,
481 poke_cmd((op_poke_t *)payload));
485 printf("app_common_v2: unhandled opcode = %d\n", gp->opcode);
489 int t = (gp->len + 3) & ~3; // bump to a multiple of 4
493 subpktlen = (subpktlen + 3) & ~3; // bump to a multiple of 4
494 reply_payload += subpktlen;
495 reply_payload_space -= subpktlen;
500 // add the EOP marker
501 subpktlen = add_eop(reply_payload, reply_payload_space);
502 subpktlen = (subpktlen + 3) & ~3; // bump to a multiple of 4
503 reply_payload += subpktlen;
504 reply_payload_space -= subpktlen;
506 send_reply(reply, reply_payload - reply);
511 * Called when an ethernet packet is received.
512 * Return true if we handled it here, otherwise
513 * it'll be passed on to the DSP Tx pipe
516 eth_pkt_inspector(dbsm_t *sm, int bufno)
518 u2_eth_packet_t *pkt = (u2_eth_packet_t *) buffer_ram(bufno);
519 size_t byte_len = (buffer_pool_status->last_line[bufno] - 3) * 4;
521 //static size_t last_len = 0;
523 // hal_toggle_leds(0x1);
525 // inspect rcvd frame and figure out what do do.
527 if (pkt->ehdr.ethertype != U2_ETHERTYPE)
528 return true; // ignore, probably bogus PAUSE frame from MAC
530 int chan = u2p_chan(&pkt->fixed);
534 handle_control_chan_frame(pkt, byte_len);
535 return true; // we handled the packet
542 if (byte_len != last_len){
543 printf("Len: %d last: %d\n", byte_len, last_len);
548 if((pkt->thdr.seqno) == exp_seqno){
554 //printf("S%d %d ",exp_seqno,pkt->thdr.seqno);
555 exp_seqno = pkt->thdr.seqno + 1;
558 return false; // pass it on to Tx DSP
564 * Called when eth phy state changes (w/ interrupts disabled)
567 link_changed_callback(int speed)
569 link_is_up = speed != 0;
570 hal_set_leds(link_is_up ? 0x20 : 0x0, 0x20);
571 printf("\neth link changed: speed = %d\n", speed);
576 print_tune_result(char *msg, bool tune_ok,
577 u2_fxpt_freq_t target_freq, struct tune_result *r)
580 printf("db_tune %s %s\n", msg, tune_ok ? "true" : "false");
581 putstr(" target_freq "); print_fxpt_freq(target_freq); newline();
582 putstr(" baseband_freq "); print_fxpt_freq(r->baseband_freq); newline();
583 putstr(" dxc_freq "); print_fxpt_freq(r->dxc_freq); newline();
584 putstr(" residual_freq "); print_fxpt_freq(r->residual_freq); newline();
585 printf(" inverted %s\n", r->inverted ? "true" : "false");