3 * Copyright 2007,2008,2009 Free Software Foundation, Inc.
5 * This program is free software: you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation, either version 3 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 #include "app_common_v2.h"
24 #include "buffer_pool.h"
25 #include "memcpy_wa.h"
28 #include "print_rmon_regs.h"
34 #include "usrp2_i2c_addr.h"
36 volatile bool link_is_up = false; // eth handler sets this
37 int cpu_tx_buf_dest_port = PORT_ETH;
39 // If this is non-zero, this dbsm could be writing to the ethernet
40 dbsm_t *ac_could_be_sending_to_eth;
42 static unsigned char exp_seqno __attribute__((unused)) = 0;
45 sync_to_pps(const op_generic_t *p)
47 timesync_regs->sync_on_next_pps = 1;
48 //putstr("SYNC to PPS\n");
53 sync_every_pps(const op_generic_t *p)
56 timesync_regs->tick_control |= TSC_TRIGGER_EVERYPPS;
58 timesync_regs->tick_control &= ~TSC_TRIGGER_EVERYPPS;
64 config_mimo_cmd(const op_config_mimo_t *p)
66 clocks_mimo_config(p->flags);
71 set_reply_hdr(u2_eth_packet_t *reply_pkt, u2_eth_packet_t const *cmd_pkt)
73 reply_pkt->ehdr.dst = cmd_pkt->ehdr.src;
74 reply_pkt->ehdr.src = *ethernet_mac_addr();
75 reply_pkt->ehdr.ethertype = U2_ETHERTYPE;
76 reply_pkt->thdr.flags = 0;
77 reply_pkt->thdr.fifo_status = 0; // written by protocol engine
78 reply_pkt->thdr.seqno = 0; // written by protocol engine
79 reply_pkt->thdr.ack = 0; // written by protocol engine
80 u2p_set_word0(&reply_pkt->fixed, 0, CONTROL_CHAN);
81 reply_pkt->fixed.timestamp = timer_regs->time;
85 send_reply(unsigned char *reply, size_t reply_len)
90 // wait for buffer to become idle
91 hal_set_leds(0x4, 0x4);
92 while((buffer_pool_status->status & BPS_IDLE(CPU_TX_BUF)) == 0)
94 hal_set_leds(0x0, 0x4);
96 // copy reply into CPU_TX_BUF
97 memcpy_wa(buffer_ram(CPU_TX_BUF), reply, reply_len);
99 // wait until nobody else is sending to the ethernet
100 if (ac_could_be_sending_to_eth){
101 hal_set_leds(0x8, 0x8);
102 dbsm_wait_for_opening(ac_could_be_sending_to_eth);
103 hal_set_leds(0x0, 0x8);
107 printf("sending_reply to port %d, len = %d\n", cpu_tx_buf_dest_port, (int)reply_len);
108 print_buffer(buffer_ram(CPU_TX_BUF), reply_len/4);
112 bp_send_from_buf(CPU_TX_BUF, cpu_tx_buf_dest_port, 1, 0, reply_len/4);
114 // wait for it to complete (not long, it's a small pkt)
115 while((buffer_pool_status->status & (BPS_DONE(CPU_TX_BUF) | BPS_ERROR(CPU_TX_BUF))) == 0)
118 bp_clear_buf(CPU_TX_BUF);
123 op_id_cmd(const op_generic_t *p,
124 void *reply_payload, size_t reply_payload_space)
126 op_id_reply_t *r = (op_id_reply_t *) reply_payload;
127 if (reply_payload_space < sizeof(*r)) // no room
130 // Build reply subpacket
132 r->opcode = OP_ID_REPLY;
133 r->len = sizeof(op_id_reply_t);
135 r->addr = *ethernet_mac_addr();
136 r->hw_rev = (u2_hw_rev_major << 8) | u2_hw_rev_minor;
137 // r->fpga_md5sum = ; // FIXME
138 // r->sw_md5sum = ; // FIXME
145 config_tx_v2_cmd(const op_config_tx_v2_t *p,
146 void *reply_payload, size_t reply_payload_space)
148 op_config_tx_reply_v2_t *r = (op_config_tx_reply_v2_t *) reply_payload;
149 if (reply_payload_space < sizeof(*r))
152 struct tune_result tune_result;
153 memset(&tune_result, 0, sizeof(tune_result));
157 if (p->valid & CFGV_GAIN){
158 ok &= db_set_gain(tx_dboard, p->gain);
161 if (p->valid & CFGV_FREQ){
162 bool was_streaming = is_streaming();
166 u2_fxpt_freq_t f = u2_fxpt_freq_from_hilo(p->freq_hi, p->freq_lo);
167 bool tune_ok = db_tune(tx_dboard, f, &tune_result);
169 print_tune_result("Tx", tune_ok, f, &tune_result);
175 if (p->valid & CFGV_INTERP_DECIM){
176 int interp = p->interp;
182 interp = interp >> 1;
187 interp = interp >> 1;
190 if (interp < MIN_CIC_INTERP || interp > MAX_CIC_INTERP)
193 dsp_tx_regs->interp_rate = (hb1<<9) | (hb2<<8) | interp;
194 // printf("Interp: %d, register %d\n", p->interp, (hb1<<9) | (hb2<<8) | interp);
198 if (p->valid & CFGV_SCALE_IQ){
199 dsp_tx_regs->scale_iq = p->scale_iq;
202 // Build reply subpacket
204 r->opcode = OP_CONFIG_TX_REPLY_V2;
208 r->inverted = tune_result.inverted;
209 r->baseband_freq_hi = u2_fxpt_freq_hi(tune_result.baseband_freq);
210 r->baseband_freq_lo = u2_fxpt_freq_lo(tune_result.baseband_freq);
211 r->duc_freq_hi = u2_fxpt_freq_hi(tune_result.dxc_freq);
212 r->duc_freq_lo = u2_fxpt_freq_lo(tune_result.dxc_freq);
213 r->residual_freq_hi = u2_fxpt_freq_hi(tune_result.residual_freq);
214 r->residual_freq_lo = u2_fxpt_freq_lo(tune_result.residual_freq);
219 config_rx_v2_cmd(const op_config_rx_v2_t *p,
220 void *reply_payload, size_t reply_payload_space)
222 op_config_rx_reply_v2_t *r = (op_config_rx_reply_v2_t *) reply_payload;
223 if (reply_payload_space < sizeof(*r))
226 struct tune_result tune_result;
227 memset(&tune_result, 0, sizeof(tune_result));
231 if (p->valid & CFGV_GAIN){
232 ok &= db_set_gain(rx_dboard, p->gain);
235 if (p->valid & CFGV_FREQ){
236 bool was_streaming = is_streaming();
240 u2_fxpt_freq_t f = u2_fxpt_freq_from_hilo(p->freq_hi, p->freq_lo);
241 bool tune_ok = db_tune(rx_dboard, f, &tune_result);
243 print_tune_result("Rx", tune_ok, f, &tune_result);
249 if (p->valid & CFGV_INTERP_DECIM){
250 int decim = p->decim;
264 if (decim < MIN_CIC_DECIM || decim > MAX_CIC_DECIM)
267 dsp_rx_regs->decim_rate = (hb1<<9) | (hb2<<8) | decim;
268 // printf("Decim: %d, register %d\n", p->decim, (hb1<<9) | (hb2<<8) | decim);
272 if (p->valid & CFGV_SCALE_IQ){
273 dsp_rx_regs->scale_iq = p->scale_iq;
276 // Build reply subpacket
278 r->opcode = OP_CONFIG_RX_REPLY_V2;
282 r->inverted = tune_result.inverted;
283 r->baseband_freq_hi = u2_fxpt_freq_hi(tune_result.baseband_freq);
284 r->baseband_freq_lo = u2_fxpt_freq_lo(tune_result.baseband_freq);
285 r->ddc_freq_hi = u2_fxpt_freq_hi(tune_result.dxc_freq);
286 r->ddc_freq_lo = u2_fxpt_freq_lo(tune_result.dxc_freq);
287 r->residual_freq_hi = u2_fxpt_freq_hi(tune_result.residual_freq);
288 r->residual_freq_lo = u2_fxpt_freq_lo(tune_result.residual_freq);
294 read_time_cmd(const op_generic_t *p,
295 void *reply_payload, size_t reply_payload_space)
297 op_read_time_reply_t *r = (op_read_time_reply_t *) reply_payload;
298 if (reply_payload_space < sizeof(*r))
301 r->opcode = OP_READ_TIME_REPLY;
304 r->time = timer_regs->time;
310 fill_db_info(u2_db_info_t *p, const struct db_base *db)
312 //p->dbid = db->dbid;
313 p->freq_min_hi = u2_fxpt_freq_hi(db->freq_min);
314 p->freq_min_lo = u2_fxpt_freq_lo(db->freq_min);
315 p->freq_max_hi = u2_fxpt_freq_hi(db->freq_max);
316 p->freq_max_lo = u2_fxpt_freq_lo(db->freq_max);
317 p->gain_min = db->gain_min;
318 p->gain_max = db->gain_max;
319 p->gain_step_size = db->gain_step_size;
323 dboard_info_cmd(const op_generic_t *p,
324 void *reply_payload, size_t reply_payload_space)
326 op_dboard_info_reply_t *r = (op_dboard_info_reply_t *) reply_payload;
327 if (reply_payload_space < sizeof(*r))
330 r->opcode = OP_DBOARD_INFO_REPLY;
335 fill_db_info(&r->tx_db_info, tx_dboard);
336 fill_db_info(&r->rx_db_info, rx_dboard);
338 r->tx_db_info.dbid = read_dboard_eeprom(I2C_ADDR_TX_A);
339 r->rx_db_info.dbid = read_dboard_eeprom(I2C_ADDR_RX_A);
345 peek_cmd(const op_peek_t *p,
346 void *reply_payload, size_t reply_payload_space)
348 op_generic_t *r = (op_generic_t *) reply_payload;
350 //putstr("peek: addr="); puthex32(p->addr);
351 //printf(" bytes=%u\n", p->bytes);
353 if ((reply_payload_space < (sizeof(*r) + p->bytes)) ||
354 p->bytes > MAX_SUBPKT_LEN - sizeof(op_generic_t)) {
355 putstr("peek: insufficient reply packet space\n");
356 return 0; // FIXME do partial read?
359 r->opcode = OP_PEEK_REPLY;
360 r->len = sizeof(*r)+p->bytes;
364 memcpy_wa(reply_payload+sizeof(*r), (void *)p->addr, p->bytes);
370 poke_cmd(const op_poke_t *p)
372 int bytes = p->len - sizeof(*p);
373 //putstr("poke: addr="); puthex32(p->addr);
374 //printf(" bytes=%u\n", bytes);
376 uint8_t *src = (uint8_t *)p + sizeof(*p);
377 memcpy_wa((void *)p->addr, src, bytes);
383 set_lo_offset_cmd(const op_freq_t *p)
385 u2_fxpt_freq_t f = u2_fxpt_freq_from_hilo(p->freq_hi, p->freq_lo);
386 if (p->opcode == OP_SET_TX_LO_OFFSET)
387 return db_set_lo_offset(tx_dboard, f);
389 return db_set_lo_offset(rx_dboard, f);
393 gpio_read_cmd(const op_gpio_t *p,
394 void *reply_payload, size_t reply_payload_space)
396 op_gpio_read_reply_t *r = (op_gpio_read_reply_t *) reply_payload;
397 if (reply_payload_space < sizeof(*r)) // no room
400 // Build reply subpacket
402 r->opcode = OP_GPIO_READ_REPLY;
403 r->len = sizeof(op_gpio_read_reply_t);
407 r->value = hal_gpio_read(p->bank);
413 generic_reply(const op_generic_t *p,
414 void *reply_payload, size_t reply_payload_space,
417 op_generic_t *r = (op_generic_t *) reply_payload;
418 if (reply_payload_space < sizeof(*r))
421 r->opcode = p->opcode | OP_REPLY_BIT;
430 add_eop(void *reply_payload, size_t reply_payload_space)
432 op_generic_t *r = (op_generic_t *) reply_payload;
433 if (reply_payload_space < sizeof(*r))
445 handle_control_chan_frame(u2_eth_packet_t *pkt, size_t len)
447 unsigned char reply[sizeof(u2_eth_packet_t) + 4 * sizeof(u2_subpkt_t)] _AL4;
448 unsigned char *reply_payload = &reply[sizeof(u2_eth_packet_t)];
449 int reply_payload_space = sizeof(reply) - sizeof(u2_eth_packet_t);
452 memset(reply, 0, sizeof(reply));
453 set_reply_hdr((u2_eth_packet_t *) reply, pkt);
455 // point to beginning of payload (subpackets)
456 unsigned char *payload = ((unsigned char *) pkt) + sizeof(u2_eth_packet_t);
457 int payload_len = len - sizeof(u2_eth_packet_t);
459 size_t subpktlen = 0;
462 while (payload_len >= sizeof(op_generic_t)){
463 const op_generic_t *gp = (const op_generic_t *) payload;
466 // printf("\nopcode = %d\n", gp->opcode);
469 case OP_EOP: // end of subpackets
470 goto end_of_subpackets;
473 subpktlen = op_id_cmd(gp, reply_payload, reply_payload_space);
476 case OP_CONFIG_TX_V2:
477 subpktlen = config_tx_v2_cmd((op_config_tx_v2_t *) payload, reply_payload, reply_payload_space);
480 case OP_CONFIG_RX_V2:
481 subpktlen = config_rx_v2_cmd((op_config_rx_v2_t *) payload, reply_payload, reply_payload_space);
484 case OP_START_RX_STREAMING:
485 if (pkt->fixed.timestamp == -1) // Start now (default)
486 start_rx_streaming_cmd(&pkt->ehdr.src, (op_start_rx_streaming_t *) payload);
488 start_rx_streaming_at_cmd(&pkt->ehdr.src, (op_start_rx_streaming_t *)payload, pkt->fixed.timestamp);
497 case OP_BURN_MAC_ADDR:
498 ok = ethernet_set_mac_addr(&((op_burn_mac_addr_t *)payload)->addr);
502 ok = config_mimo_cmd((op_config_mimo_t *) payload);
506 subpktlen = read_time_cmd(gp, reply_payload, reply_payload_space);
510 subpktlen = dboard_info_cmd(gp, reply_payload, reply_payload_space);
514 sync_to_pps((op_generic_t *) payload);
519 subpktlen = peek_cmd((op_peek_t *)payload, reply_payload, reply_payload_space);
523 ok = poke_cmd((op_poke_t *)payload);
526 case OP_SET_TX_LO_OFFSET:
527 case OP_SET_RX_LO_OFFSET:
528 ok = set_lo_offset_cmd((op_freq_t *)payload);
536 case OP_SYNC_EVERY_PPS:
537 ok = sync_every_pps((op_generic_t *) payload);
540 case OP_GPIO_SET_DDR:
542 hal_gpio_set_ddr(((op_gpio_t *)payload)->bank,
543 ((op_gpio_t *)payload)->value,
544 ((op_gpio_t *)payload)->mask);
547 case OP_GPIO_SET_SELS:
549 hal_gpio_set_sels(((op_gpio_set_sels_t *)payload)->bank,
550 (char *)(&((op_gpio_set_sels_t *)payload)->sels));
554 subpktlen = gpio_read_cmd((op_gpio_t *) payload, reply_payload, reply_payload_space);
559 hal_gpio_write(((op_gpio_t *)payload)->bank,
560 ((op_gpio_t *)payload)->value,
561 ((op_gpio_t *)payload)->mask);
566 dsp_rx_regs->gpio_stream_enable = (uint32_t)((op_gpio_t *)payload)->value;
569 // Add new opcode handlers here
572 subpktlen = generic_reply(gp, reply_payload, reply_payload_space, ok);
576 printf("app_common_v2: unhandled opcode = %d\n", gp->opcode);
580 int t = (gp->len + 3) & ~3; // bump to a multiple of 4
584 subpktlen = (subpktlen + 3) & ~3; // bump to a multiple of 4
585 reply_payload += subpktlen;
586 reply_payload_space -= subpktlen;
591 // add the EOP marker
592 subpktlen = add_eop(reply_payload, reply_payload_space);
593 subpktlen = (subpktlen + 3) & ~3; // bump to a multiple of 4
594 reply_payload += subpktlen;
595 reply_payload_space -= subpktlen;
597 send_reply(reply, reply_payload - reply);
602 * Called when an ethernet packet is received.
603 * Return true if we handled it here, otherwise
604 * it'll be passed on to the DSP Tx pipe
607 eth_pkt_inspector(dbsm_t *sm, int bufno)
609 u2_eth_packet_t *pkt = (u2_eth_packet_t *) buffer_ram(bufno);
610 size_t byte_len = (buffer_pool_status->last_line[bufno] - 1) * 4;
612 //static size_t last_len = 0;
614 // hal_toggle_leds(0x1);
616 // inspect rcvd frame and figure out what do do.
618 if (pkt->ehdr.ethertype != U2_ETHERTYPE)
619 return true; // ignore, probably bogus PAUSE frame from MAC
621 int chan = u2p_chan(&pkt->fixed);
625 handle_control_chan_frame(pkt, byte_len);
626 return true; // we handled the packet
633 if (byte_len != last_len){
634 printf("Len: %d last: %d\n", byte_len, last_len);
639 if((pkt->thdr.seqno) == exp_seqno){
645 //printf("S%d %d ",exp_seqno,pkt->thdr.seqno);
646 exp_seqno = pkt->thdr.seqno + 1;
649 return false; // pass it on to Tx DSP
655 * Called when eth phy state changes (w/ interrupts disabled)
658 link_changed_callback(int speed)
660 link_is_up = speed != 0;
661 hal_set_leds(link_is_up ? LED_RJ45 : 0x0, LED_RJ45);
662 printf("\neth link changed: speed = %d\n", speed);
667 print_tune_result(char *msg, bool tune_ok,
668 u2_fxpt_freq_t target_freq, struct tune_result *r)
671 printf("db_tune %s %s\n", msg, tune_ok ? "true" : "false");
672 putstr(" target_freq "); print_fxpt_freq(target_freq); newline();
673 putstr(" baseband_freq "); print_fxpt_freq(r->baseband_freq); newline();
674 putstr(" dxc_freq "); print_fxpt_freq(r->dxc_freq); newline();
675 putstr(" residual_freq "); print_fxpt_freq(r->residual_freq); newline();
676 printf(" inverted %s\n", r->inverted ? "true" : "false");