1 # This is the template file for creating symbols with tragesym
2 # every line starting with '#' is a comment line.
5 # rotate_labels rotates the pintext of top and bottom pins
6 # wordswap swaps labels if the pin is on the right side an looks like this:
14 pinwidthhorizontal=400
17 # name will be printed in the top of the symbol
18 # if you have a device with slots, you'll have to use slot= and slotdef=
19 # use comment= if there are special information you want to add
25 description=EP2C20 Cyclone II FPGA
26 documentation=http://www.altera.com
39 # tabseparated list of pin descriptions
40 # pinnr is the physical number of the pin
41 # seq is the pinseq= attribute, leave it blank if it doesn't matter
42 # type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
43 # style can be (line,dot,clk,dotclk,none). none if only want to add a net
44 # posit. can be (l,r,t,b) or empty for nets
45 # net specifies the name of the Vcc or GND name
46 # label represents the pinlabel.
47 # negation lines can be added with _Q_
48 # if you want to add a "_" or "\" use "\_" and "\\" as escape sequences
49 #-----------------------------------------------------
50 #pinnr seq type style posit. net label
51 #-----------------------------------------------------
52 U5 pwr line r GND\_PLL1
53 U6 pwr line l VCCD\_PLL1
54 U7 pwr line l VCCA\_PLL1
55 V7 pwr line r GNDA\_PLL1
56 V5 pwr line r GND\_PLL1
58 E16 pwr line r GNDA\_PLL2
59 E17 pwr line r GND\_PLL2
60 F16 pwr line l VCCA\_PLL2
61 F17 pwr line l VCCD\_PLL2
62 F18 pwr line r GND\_PLL2
64 F5 pwr line r GND\_PLL3
65 E5 pwr line l VCCD\_PLL3
66 F6 pwr line r GND\_PLL3
67 F7 pwr line r GNDA\_PLL3
68 E6 pwr line l VCCA\_PLL3
70 V18 pwr line r GND\_PLL4
71 U17 pwr line l VCCD\_PLL4
72 T17 pwr line r GND\_PLL4
73 V16 pwr line r GNDA\_PLL4
74 U16 pwr line l VCCA\_PLL4
132 J10 pwr line l VccInt
133 J11 pwr line l VccInt
134 J12 pwr line l VccInt
135 J13 pwr line l VccInt
137 K14 pwr line l VccInt
139 L14 pwr line l VccInt
141 M14 pwr line l VccInt
143 N14 pwr line l VccInt
144 P10 pwr line l VccInt
145 P11 pwr line l VccInt
146 P12 pwr line l VccInt
147 P13 pwr line l VccInt
149 AA1 pwr line l VccIO1
160 C11 pwr line l VccIO3
161 E10 pwr line l VccIO3
164 A21 pwr line l VccIO4
165 C12 pwr line l VccIO4
166 D17 pwr line l VccIO4
167 E13 pwr line l VccIO4
168 G14 pwr line l VccIO4
170 B22 pwr line l VccIO5
171 G19 pwr line l VccIO5
172 J16 pwr line l VccIO5
173 L20 pwr line l VccIO5
175 AA22 pwr line l VccIO6
176 M20 pwr line l VccIO6
177 P16 pwr line l VccIO6
178 T19 pwr line l VccIO6
180 AB21 pwr line l VccIO7
181 T14 pwr line l VccIO7
182 V13 pwr line l VccIO7
183 W17 pwr line l VccIO7
184 Y12 pwr line l VccIO7
186 AB2 pwr line l VccIO8
188 V10 pwr line l VccIO8
190 Y11 pwr line l VccIO8