3 * Copyright 2004 Free Software Foundation, Inc.
5 * This file is part of GNU Radio
7 * GNU Radio is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 3, or (at your option)
12 * GNU Radio is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with GNU Radio; see the file COPYING. If not, write to
19 * the Free Software Foundation, Inc., 51 Franklin Street,
20 * Boston, MA 02110-1301, USA.
23 #include <usrp_standard.h>
25 #include "usrp_prims.h"
26 #include "fpga_regs_common.h"
27 #include "fpga_regs_standard.h"
34 static const int OLD_CAPS_VAL = 0xaa55ff77;
35 static const int DEFAULT_CAPS_VAL = ((2 << bmFR_RB_CAPS_NDUC_SHIFT)
36 | (2 << bmFR_RB_CAPS_NDDC_SHIFT)
37 | bmFR_RB_CAPS_RX_HAS_HALFBAND);
39 // #define USE_FPGA_TX_CORDIC
42 using namespace ad9862;
44 #define NELEM(x) (sizeof (x) / sizeof (x[0]))
48 compute_freq_control_word_fpga (double master_freq, double target_freq,
49 double *actual_freq, bool verbose)
51 static const int NBITS = 14;
53 int v = (int) rint (target_freq / master_freq * pow (2.0, 32.0));
56 v = (v >> (32 - NBITS)) << (32 - NBITS); // keep only top NBITS
58 *actual_freq = v * master_freq / pow (2.0, 32.0);
62 "compute_freq_control_word_fpga: target = %g actual = %g delta = %g\n",
63 target_freq, *actual_freq, *actual_freq - target_freq);
65 return (unsigned int) v;
68 // The 9862 uses an unsigned 24-bit frequency tuning word and
69 // a separate register to control the sign.
72 compute_freq_control_word_9862 (double master_freq, double target_freq,
73 double *actual_freq, bool verbose)
80 int v = (int) rint (fabs (target_freq) / master_freq * pow (2.0, 24.0));
81 *actual_freq = v * master_freq / pow (2.0, 24.0) * sign;
85 "compute_freq_control_word_9862: target = %g actual = %g delta = %g v = %8d\n",
86 target_freq, *actual_freq, *actual_freq - target_freq, v);
88 return (unsigned int) v;
91 // ----------------------------------------------------------------
93 usrp_standard_common::usrp_standard_common(usrp_basic *parent)
95 // read new FPGA capability register
96 if (!parent->_read_fpga_reg(FR_RB_CAPS, &d_fpga_caps)){
97 fprintf (stderr, "usrp_standard_common: failed to read FPGA cap register.\n");
98 throw std::runtime_error ("usrp_standard_common::ctor");
100 // If we don't have the cap register, set the value to what it would
101 // have had if we did have one ;)
102 if (d_fpga_caps == OLD_CAPS_VAL)
103 d_fpga_caps = DEFAULT_CAPS_VAL;
106 fprintf(stdout, "has_rx_halfband = %d\n", has_rx_halfband());
107 fprintf(stdout, "nddcs = %d\n", nddcs());
108 fprintf(stdout, "has_tx_halfband = %d\n", has_tx_halfband());
109 fprintf(stdout, "nducs = %d\n", nducs());
114 usrp_standard_common::has_rx_halfband() const
116 return (d_fpga_caps & bmFR_RB_CAPS_RX_HAS_HALFBAND) ? true : false;
120 usrp_standard_common::nddcs() const
122 return (d_fpga_caps & bmFR_RB_CAPS_NDDC_MASK) >> bmFR_RB_CAPS_NDDC_SHIFT;
126 usrp_standard_common::has_tx_halfband() const
128 return (d_fpga_caps & bmFR_RB_CAPS_TX_HAS_HALFBAND) ? true : false;
132 usrp_standard_common::nducs() const
134 return (d_fpga_caps & bmFR_RB_CAPS_NDUC_MASK) >> bmFR_RB_CAPS_NDUC_SHIFT;
137 // ----------------------------------------------------------------
140 real_rx_mux_value (int mux, int nchan)
148 usrp_standard_rx::usrp_standard_rx (int which_board,
149 unsigned int decim_rate,
150 int nchan, int mux, int mode,
151 int fusb_block_size, int fusb_nblocks,
152 const std::string fpga_filename,
153 const std::string firmware_filename
155 : usrp_basic_rx (which_board, fusb_block_size, fusb_nblocks,
156 fpga_filename, firmware_filename),
157 usrp_standard_common(this),
158 d_nchan (1), d_sw_mux (0x0), d_hw_mux (0x0)
160 if (!set_format(make_format())){
161 fprintf (stderr, "usrp_standard_rx: set_format failed\n");
162 throw std::runtime_error ("usrp_standard_rx::ctor");
164 if (!set_nchannels (nchan)){
165 fprintf (stderr, "usrp_standard_rx: set_nchannels failed\n");
166 throw std::runtime_error ("usrp_standard_rx::ctor");
168 if (!set_decim_rate (decim_rate)){
169 fprintf (stderr, "usrp_standard_rx: set_decim_rate failed\n");
170 throw std::runtime_error ("usrp_standard_rx::ctor");
172 if (!set_mux (real_rx_mux_value (mux, nchan))){
173 fprintf (stderr, "usrp_standard_rx: set_mux failed\n");
174 throw std::runtime_error ("usrp_standard_rx::ctor");
176 if (!set_fpga_mode (mode)){
177 fprintf (stderr, "usrp_standard_rx: set_fpga_mode failed\n");
178 throw std::runtime_error ("usrp_standard_rx::ctor");
181 for (int i = 0; i < MAX_CHAN; i++){
187 usrp_standard_rx::~usrp_standard_rx ()
189 // fprintf(stderr, "\nusrp_standard_rx: dtor\n");
193 usrp_standard_rx::start ()
195 if (!usrp_basic_rx::start ())
204 usrp_standard_rx::stop ()
206 bool ok = usrp_basic_rx::stop ();
214 usrp_standard_rx::make (int which_board,
215 unsigned int decim_rate,
216 int nchan, int mux, int mode,
217 int fusb_block_size, int fusb_nblocks,
218 const std::string fpga_filename,
219 const std::string firmware_filename
222 usrp_standard_rx *u = 0;
225 u = new usrp_standard_rx (which_board, decim_rate,
227 fusb_block_size, fusb_nblocks,
228 fpga_filename, firmware_filename);
240 usrp_standard_rx::set_decim_rate(unsigned int rate)
242 if ((rate & 0x1) || rate < 4 || rate > 256){
243 fprintf (stderr, "usrp_standard_rx::set_decim_rate: rate must be EVEN and in [4, 256]\n");
248 set_usb_data_rate ((adc_rate () / rate * nchannels ())
249 * (2 * sizeof (short)));
251 bool s = disable_rx ();
252 int v = has_rx_halfband() ? d_decim_rate/2 - 1 : d_decim_rate - 1;
253 bool ok = _write_fpga_reg (FR_DECIM_RATE, v);
258 bool usrp_standard_rx::set_nchannels (int nchan)
260 if (!(nchan == 1 || nchan == 2 || nchan == 4))
268 return write_hw_mux_reg ();
272 // map software mux value to hw mux value
274 // Software mux value:
277 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
278 // +-------+-------+-------+-------+-------+-------+-------+-------+
279 // | Q3 | I3 | Q2 | I2 | Q1 | I1 | Q0 | I0 |
280 // +-------+-------+-------+-------+-------+-------+-------+-------+
282 // Each 4-bit I field is either 0,1,2,3
283 // Each 4-bit Q field is either 0,1,2,3 or 0xf (input is const zero)
284 // All Q's must be 0xf or none of them may be 0xf
287 // Hardware mux value:
290 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
291 // +-----------------------+-------+-------+-------+-------+-+-----+
292 // | must be zero | Q3| I3| Q2| I2| Q1| I1| Q0| I0|Z| NCH |
293 // +-----------------------+-------+-------+-------+-------+-+-----+
297 map_sw_mux_to_hw_mux (int sw_mux, int *hw_mux_ptr)
299 // confirm that all I's are either 0,1,2,3
301 for (int i = 0; i < 8; i += 2){
302 int t = (sw_mux >> (4 * i)) & 0xf;
303 if (!(0 <= t && t <= 3))
307 // confirm that all Q's are either 0,1,2,3 or 0xf
309 for (int i = 1; i < 8; i += 2){
310 int t = (sw_mux >> (4 * i)) & 0xf;
311 if (!(t == 0xf || (0 <= t && t <= 3)))
315 // confirm that all Q inputs are 0xf (const zero input),
316 // or none of them are 0xf
321 for (int i = 0; i < 4; i++){
322 int qx_is_0xf = ((sw_mux >> (8 * i + 4)) & 0xf) == 0xf;
327 if (q_and || !q_or){ // OK
328 int hw_mux_value = 0;
330 for (int i = 0; i < 8; i++){
331 int t = (sw_mux >> (4 * i)) & 0x3;
332 hw_mux_value |= t << (2 * i + 4);
336 hw_mux_value |= 0x8; // all Q's zero
338 *hw_mux_ptr = hw_mux_value;
346 usrp_standard_rx::set_mux (int mux)
348 if (!map_sw_mux_to_hw_mux (mux, &d_hw_mux))
351 // fprintf (stderr, "sw_mux = 0x%08x hw_mux = 0x%08x\n", mux, d_hw_mux);
354 return write_hw_mux_reg ();
358 usrp_standard_rx::write_hw_mux_reg ()
360 bool s = disable_rx ();
361 bool ok = _write_fpga_reg (FR_RX_MUX, d_hw_mux | d_nchan);
368 usrp_standard_rx::set_rx_freq (int channel, double freq)
370 if (channel < 0 || channel > MAX_CHAN)
374 compute_freq_control_word_fpga (adc_freq(),
375 freq, &d_rx_freq[channel],
378 return _write_fpga_reg (FR_RX_FREQ_0 + channel, v);
382 usrp_standard_rx::decim_rate () const { return d_decim_rate; }
385 usrp_standard_rx::nchannels () const { return d_nchan; }
388 usrp_standard_rx::mux () const { return d_sw_mux; }
391 usrp_standard_rx::rx_freq (int channel) const
393 if (channel < 0 || channel >= MAX_CHAN)
396 return d_rx_freq[channel];
400 usrp_standard_rx::set_fpga_mode (int mode)
402 return _write_fpga_reg (FR_MODE, mode);
406 usrp_standard_rx::set_ddc_phase(int channel, int phase)
408 if (channel < 0 || channel >= MAX_CHAN)
411 return _write_fpga_reg(FR_RX_PHASE_0 + channel, phase);
415 // To avoid quiet failures, check for things that our code cares about.
418 rx_format_is_valid(unsigned int format)
420 int width = usrp_standard_rx::format_width(format);
421 int want_q = usrp_standard_rx::format_want_q(format);
423 if (!(width == 8 || width == 16)) // FIXME add other widths when valid
426 if (!want_q) // FIXME remove check when the rest of the code can handle I only
433 usrp_standard_rx::set_format(unsigned int format)
435 if (!rx_format_is_valid(format))
438 return _write_fpga_reg(FR_RX_FORMAT, format);
442 usrp_standard_rx::format() const
444 return d_fpga_shadows[FR_RX_FORMAT];
447 // ----------------------------------------------------------------
450 usrp_standard_rx::make_format(int width, int shift, bool want_q, bool bypass_halfband)
452 unsigned int format =
453 (((width << bmFR_RX_FORMAT_WIDTH_SHIFT) & bmFR_RX_FORMAT_WIDTH_MASK)
454 | (shift << bmFR_RX_FORMAT_SHIFT_SHIFT) & bmFR_RX_FORMAT_SHIFT_MASK);
457 format |= bmFR_RX_FORMAT_WANT_Q;
459 format |= bmFR_RX_FORMAT_BYPASS_HB;
465 usrp_standard_rx::format_width(unsigned int format)
467 return (format & bmFR_RX_FORMAT_WIDTH_MASK) >> bmFR_RX_FORMAT_WIDTH_SHIFT;
471 usrp_standard_rx::format_shift(unsigned int format)
473 return (format & bmFR_RX_FORMAT_SHIFT_MASK) >> bmFR_RX_FORMAT_SHIFT_SHIFT;
477 usrp_standard_rx::format_want_q(unsigned int format)
479 return (format & bmFR_RX_FORMAT_WANT_Q) != 0;
483 usrp_standard_rx::format_bypass_halfband(unsigned int format)
485 return (format & bmFR_RX_FORMAT_BYPASS_HB) != 0;
488 //////////////////////////////////////////////////////////////////
491 // tx data is timed to CLKOUT1 (64 MHz)
493 // fine modulator enabled
496 static unsigned char tx_regs_use_nco[] = {
497 REG_TX_IF, (TX_IF_USE_CLKOUT1
500 | TX_IF_INTERLEAVED),
501 REG_TX_DIGITAL, (TX_DIGITAL_2_DATA_PATHS
502 | TX_DIGITAL_INTERPOLATE_4X)
507 real_tx_mux_value (int mux, int nchan)
522 usrp_standard_tx::usrp_standard_tx (int which_board,
523 unsigned int interp_rate,
525 int fusb_block_size, int fusb_nblocks,
526 const std::string fpga_filename,
527 const std::string firmware_filename
529 : usrp_basic_tx (which_board, fusb_block_size, fusb_nblocks, fpga_filename, firmware_filename),
530 usrp_standard_common(this),
531 d_sw_mux (0x8), d_hw_mux (0x81)
533 if (!usrp_9862_write_many_all (d_udh, tx_regs_use_nco, sizeof (tx_regs_use_nco))){
534 fprintf (stderr, "usrp_standard_tx: failed to init AD9862 TX regs\n");
535 throw std::runtime_error ("usrp_standard_tx::ctor");
537 if (!set_nchannels (nchan)){
538 fprintf (stderr, "usrp_standard_tx: set_nchannels failed\n");
539 throw std::runtime_error ("usrp_standard_tx::ctor");
541 if (!set_interp_rate (interp_rate)){
542 fprintf (stderr, "usrp_standard_tx: set_interp_rate failed\n");
543 throw std::runtime_error ("usrp_standard_tx::ctor");
545 if (!set_mux (real_tx_mux_value (mux, nchan))){
546 fprintf (stderr, "usrp_standard_tx: set_mux failed\n");
547 throw std::runtime_error ("usrp_standard_tx::ctor");
550 for (int i = 0; i < MAX_CHAN; i++){
551 d_tx_modulator_shadow[i] = (TX_MODULATOR_DISABLE_NCO
552 | TX_MODULATOR_COARSE_MODULATION_NONE);
553 d_coarse_mod[i] = CM_OFF;
558 usrp_standard_tx::~usrp_standard_tx ()
560 // fprintf(stderr, "\nusrp_standard_tx: dtor\n");
564 usrp_standard_tx::start ()
566 if (!usrp_basic_tx::start ())
575 usrp_standard_tx::stop ()
577 bool ok = usrp_basic_tx::stop ();
585 usrp_standard_tx::make (int which_board,
586 unsigned int interp_rate,
588 int fusb_block_size, int fusb_nblocks,
589 const std::string fpga_filename,
590 const std::string firmware_filename
593 usrp_standard_tx *u = 0;
596 u = new usrp_standard_tx (which_board, interp_rate, nchan, mux,
597 fusb_block_size, fusb_nblocks,
598 fpga_filename, firmware_filename);
610 usrp_standard_tx::set_interp_rate (unsigned int rate)
612 // fprintf (stderr, "usrp_standard_tx::set_interp_rate\n");
614 if ((rate & 0x3) || rate < 4 || rate > 512){
615 fprintf (stderr, "usrp_standard_tx::set_interp_rate: rate must be in [4, 512] and a multiple of 4.\n");
619 d_interp_rate = rate;
620 set_usb_data_rate ((dac_rate () / rate * nchannels ())
621 * (2 * sizeof (short)));
623 // We're using the interp by 4 feature of the 9862 so that we can
624 // use its fine modulator. Thus, we reduce the FPGA's interpolation rate
627 bool s = disable_tx ();
628 bool ok = _write_fpga_reg (FR_INTERP_RATE, d_interp_rate/4 - 1);
634 usrp_standard_tx::set_nchannels (int nchan)
636 if (!(nchan == 1 || nchan == 2))
643 return write_hw_mux_reg ();
647 usrp_standard_tx::set_mux (int mux)
651 return write_hw_mux_reg ();
655 usrp_standard_tx::write_hw_mux_reg ()
657 bool s = disable_tx ();
658 bool ok = _write_fpga_reg (FR_TX_MUX, d_hw_mux | d_nchan);
663 #ifdef USE_FPGA_TX_CORDIC
666 usrp_standard_tx::set_tx_freq (int channel, double freq)
668 if (channel < 0 || channel >= MAX_CHAN)
671 // This assumes we're running the 4x on-chip interpolator.
674 compute_freq_control_word_fpga (dac_freq () / 4,
675 freq, &d_tx_freq[channel],
678 return _write_fpga_reg (FR_TX_FREQ_0 + channel, v);
685 usrp_standard_tx::set_tx_freq (int channel, double freq)
687 if (channel < 0 || channel >= MAX_CHAN)
690 // split freq into fine and coarse components
695 assert (dac_freq () == 128000000);
697 if (freq < -44e6) // too low
699 else if (freq < -24e6){ // [-44, -24)
700 cm = CM_NEG_FDAC_OVER_4;
701 coarse = -dac_freq () / 4;
703 else if (freq < -8e6){ // [-24, -8)
704 cm = CM_NEG_FDAC_OVER_8;
705 coarse = -dac_freq () / 8;
707 else if (freq < 8e6){ // [-8, 8)
711 else if (freq < 24e6){ // [8, 24)
712 cm = CM_POS_FDAC_OVER_8;
713 coarse = dac_freq () / 8;
715 else if (freq <= 44e6){ // [24, 44]
716 cm = CM_POS_FDAC_OVER_4;
717 coarse = dac_freq () / 4;
723 set_coarse_modulator (channel, cm); // set bits in d_tx_modulator_shadow
725 double fine = freq - coarse;
728 // Compute fine tuning word...
729 // This assumes we're running the 4x on-chip interpolator.
730 // (This is required to use the fine modulator.)
733 compute_freq_control_word_9862 (dac_freq () / 4,
734 fine, &d_tx_freq[channel], d_verbose);
736 d_tx_freq[channel] += coarse; // adjust actual
738 unsigned char high, mid, low;
740 high = (v >> 16) & 0xff;
741 mid = (v >> 8) & 0xff;
742 low = (v >> 0) & 0xff;
746 // write the fine tuning word
747 ok &= _write_9862 (channel, REG_TX_NCO_FTW_23_16, high);
748 ok &= _write_9862 (channel, REG_TX_NCO_FTW_15_8, mid);
749 ok &= _write_9862 (channel, REG_TX_NCO_FTW_7_0, low);
752 d_tx_modulator_shadow[channel] |= TX_MODULATOR_ENABLE_NCO;
755 d_tx_modulator_shadow[channel] |= TX_MODULATOR_NEG_FINE_TUNE;
757 d_tx_modulator_shadow[channel] &= ~TX_MODULATOR_NEG_FINE_TUNE;
759 ok &=_write_9862 (channel, REG_TX_MODULATOR, d_tx_modulator_shadow[channel]);
766 usrp_standard_tx::set_coarse_modulator (int channel, coarse_mod_t cm)
768 if (channel < 0 || channel >= MAX_CHAN)
772 case CM_NEG_FDAC_OVER_4:
773 d_tx_modulator_shadow[channel] &= ~TX_MODULATOR_CM_MASK;
774 d_tx_modulator_shadow[channel] |= TX_MODULATOR_COARSE_MODULATION_F_OVER_4;
775 d_tx_modulator_shadow[channel] |= TX_MODULATOR_NEG_COARSE_TUNE;
778 case CM_NEG_FDAC_OVER_8:
779 d_tx_modulator_shadow[channel] &= ~TX_MODULATOR_CM_MASK;
780 d_tx_modulator_shadow[channel] |= TX_MODULATOR_COARSE_MODULATION_F_OVER_8;
781 d_tx_modulator_shadow[channel] |= TX_MODULATOR_NEG_COARSE_TUNE;
785 d_tx_modulator_shadow[channel] &= ~TX_MODULATOR_CM_MASK;
788 case CM_POS_FDAC_OVER_8:
789 d_tx_modulator_shadow[channel] &= ~TX_MODULATOR_CM_MASK;
790 d_tx_modulator_shadow[channel] |= TX_MODULATOR_COARSE_MODULATION_F_OVER_8;
793 case CM_POS_FDAC_OVER_4:
794 d_tx_modulator_shadow[channel] &= ~TX_MODULATOR_CM_MASK;
795 d_tx_modulator_shadow[channel] |= TX_MODULATOR_COARSE_MODULATION_F_OVER_4;
802 d_coarse_mod[channel] = cm;
807 usrp_standard_tx::interp_rate () const { return d_interp_rate; }
810 usrp_standard_tx::nchannels () const { return d_nchan; }
813 usrp_standard_tx::mux () const { return d_sw_mux; }
816 usrp_standard_tx::tx_freq (int channel) const
818 if (channel < 0 || channel >= MAX_CHAN)
821 return d_tx_freq[channel];
824 usrp_standard_tx::coarse_mod_t
825 usrp_standard_tx::coarse_modulator (int channel) const
827 if (channel < 0 || channel >= MAX_CHAN)
830 return d_coarse_mod[channel];