3 * Copyright 2003,2004,2006,2009 Free Software Foundation, Inc.
5 * This file is part of GNU Radio
7 * GNU Radio is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 3, or (at your option)
12 * GNU Radio is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with GNU Radio; see the file COPYING. If not, write to
19 * the Free Software Foundation, Inc., 51 Franklin Street,
20 * Boston, MA 02110-1301, USA.
27 #include "usrp/usrp_prims.h"
28 #include "usrp_commands.h"
30 #include "usrp_i2c_addr.h"
31 #include "fpga_regs_common.h"
32 #include "fpga_regs_standard.h"
39 #include <time.h> // FIXME should check with autoconf (nanosleep)
43 #include "std_paths.h"
46 #include <libusb-1.0/libusb.h>
57 using namespace ad9862;
59 static const int FIRMWARE_HASH_SLOT = 0;
60 static const int FPGA_HASH_SLOT = 1;
62 static const int hash_slot_addr[2] = {
63 USRP_HASH_SLOT_0_ADDR,
67 static const char *default_firmware_filename = "std.ihx";
68 static const char *default_fpga_filename = "std_2rxhb_2tx.rbf";
71 find_file (const char *filename, int hw_rev)
73 const char **sp = std_paths;
74 static char path[1000];
77 s = getenv("USRP_PATH");
79 snprintf (path, sizeof (path), "%s/rev%d/%s", s, hw_rev, filename);
80 if (access (path, R_OK) == 0)
85 snprintf (path, sizeof (path), "%s/rev%d/%s", *sp, hw_rev, filename);
86 if (access (path, R_OK) == 0)
94 get_proto_filename(const std::string user_filename, const char *env_var, const char *def)
96 if (user_filename.length() != 0)
97 return user_filename.c_str();
99 char *s = getenv(env_var);
107 static void power_down_9862s (libusb_device_handle *udh);
110 // ----------------------------------------------------------------
113 * q must be a real USRP, not an FX2. Return its hardware rev number.
117 usrp_hw_rev (libusb_device *q)
119 libusb_device_descriptor desc = _get_usb_device_descriptor(q);
120 return desc.bcdDevice & 0x00FF;
124 * q must be a real USRP, not an FX2. Return true if it's configured.
127 _usrp_configured_p (libusb_device *q)
129 libusb_device_descriptor desc = _get_usb_device_descriptor(q);
130 return (desc.bcdDevice & 0xFF00) != 0;
134 usrp_usrp_p (libusb_device *q)
136 libusb_device_descriptor desc = _get_usb_device_descriptor(q);
137 return (desc.idVendor == USB_VID_FSF
138 && desc.idProduct == USB_PID_FSF_USRP);
142 usrp_fx2_p (libusb_device *q)
144 libusb_device_descriptor desc = _get_usb_device_descriptor(q);
145 return (desc.idVendor == USB_VID_CYPRESS
146 && desc.idProduct == USB_PID_CYPRESS_FX2);
150 usrp_usrp0_p (libusb_device *q)
152 return usrp_usrp_p (q) && usrp_hw_rev (q) == 0;
156 usrp_usrp1_p (libusb_device *q)
158 return usrp_usrp_p (q) && usrp_hw_rev (q) == 1;
162 usrp_usrp2_p (libusb_device *q)
164 return usrp_usrp_p (q) && usrp_hw_rev (q) == 2;
169 usrp_unconfigured_usrp_p (libusb_device *q)
171 return usrp_usrp_p (q) && !_usrp_configured_p (q);
175 usrp_configured_usrp_p (libusb_device *q)
177 return usrp_usrp_p (q) && _usrp_configured_p (q);
181 // ----------------------------------------------------------------
184 libusb_device_handle *
185 usrp_open_cmd_interface (libusb_device *dev)
187 return usrp_open_interface (dev, USRP_CMD_INTERFACE, USRP_CMD_ALTINTERFACE);
190 libusb_device_handle *
191 usrp_open_rx_interface (libusb_device *dev)
193 return usrp_open_interface (dev, USRP_RX_INTERFACE, USRP_RX_ALTINTERFACE);
196 libusb_device_handle *
197 usrp_open_tx_interface (libusb_device *dev)
199 return usrp_open_interface (dev, USRP_TX_INTERFACE, USRP_TX_ALTINTERFACE);
203 // ----------------------------------------------------------------
204 // write internal ram using Cypress vendor extension
207 write_internal_ram (libusb_device_handle *udh, unsigned char *buf,
208 int start_addr, size_t len)
213 int quanta = MAX_EP0_PKTSIZE;
215 for (addr = start_addr; addr < start_addr + (int) len; addr += quanta){
216 n = len + start_addr - addr;
220 a = _usb_control_transfer (udh, 0x40, 0xA0, addr, 0,
221 (unsigned char*)(buf + (addr - start_addr)), n, 1000);
224 fprintf(stderr,"write_internal_ram failed: %u\n", a);
232 // ----------------------------------------------------------------
233 // whack the CPUCS register using the upload RAM vendor extension
236 reset_cpu (libusb_device_handle *udh, bool reset_p)
241 v = 1; // hold processor in reset
243 v = 0; // release reset
245 return write_internal_ram (udh, &v, 0xE600, 1);
248 // ----------------------------------------------------------------
249 // Load intel format file into cypress FX2 (8051)
252 _usrp_load_firmware (libusb_device_handle *udh, const char *filename,
253 unsigned char hash[USRP_HASH_SIZE])
255 FILE *f = fopen (filename, "ra");
261 if (!reset_cpu (udh, true)) // hold CPU in reset while loading firmware
269 unsigned char data[256];
270 unsigned char checksum, a;
275 fgets(s, sizeof (s), f); /* we should not use more than 263 bytes normally */
277 fprintf(stderr,"%s: invalid line: \"%s\"\n", filename, s);
280 sscanf(s+1, "%02x", &length);
281 sscanf(s+3, "%04x", &addr);
282 sscanf(s+7, "%02x", &type);
286 a=length+(addr &0xff)+(addr>>8)+type;
287 for(i=0;i<length;i++){
288 sscanf (s+9+i*2,"%02x", &b);
293 sscanf (s+9+length*2,"%02x", &b);
295 if (((a+checksum)&0xff)!=0x00){
296 fprintf (stderr, " ** Checksum failed: got 0x%02x versus 0x%02x\n", (-a)&0xff, checksum);
299 if (!write_internal_ram (udh, data, addr, length))
302 else if (type == 0x01){ // EOF
305 else if (type == 0x02){
306 fprintf(stderr, "Extended address: whatever I do with it?\n");
307 fprintf (stderr, "%s: invalid line: \"%s\"\n", filename, s);
312 // we jam the hash value into the FX2 memory before letting
313 // the cpu out of reset. When it comes out of reset it
314 // may renumerate which will invalidate udh.
316 if (!usrp_set_hash (udh, FIRMWARE_HASH_SLOT, hash))
317 fprintf (stderr, "usrp: failed to write firmware hash slot\n");
319 if (!reset_cpu (udh, false)) // take CPU out of reset
330 // ----------------------------------------------------------------
334 _usrp_load_fpga (libusb_device_handle *udh, const char *filename,
335 unsigned char hash[USRP_HASH_SIZE])
339 FILE *fp = fopen (filename, "rb");
345 unsigned char buf[MAX_EP0_PKTSIZE]; // 64 is max size of EP0 packet on FX2
348 usrp_set_led (udh, 1, 1); // led 1 on
351 // reset FPGA (and on rev1 both AD9862's, thus killing clock)
352 usrp_set_fpga_reset (udh, 1); // hold fpga in reset
354 if (write_cmd (udh, VRQ_FPGA_LOAD, 0, FL_BEGIN, 0, 0) != 0)
357 while ((n = fread (buf, 1, sizeof (buf), fp)) > 0){
358 if (write_cmd (udh, VRQ_FPGA_LOAD, 0, FL_XFER, buf, n) != n)
362 if (write_cmd (udh, VRQ_FPGA_LOAD, 0, FL_END, 0, 0) != 0)
367 if (!usrp_set_hash (udh, FPGA_HASH_SLOT, hash))
368 fprintf (stderr, "usrp: failed to write fpga hash slot\n");
370 // On the rev1 USRP, the {tx,rx}_{enable,reset} bits are
371 // controlled over the serial bus, and hence aren't observed until
372 // we've got a good fpga bitstream loaded.
374 usrp_set_fpga_reset (udh, 0); // fpga out of master reset
376 // now these commands will work
378 ok &= usrp_set_fpga_tx_enable (udh, 0);
379 ok &= usrp_set_fpga_rx_enable (udh, 0);
381 ok &= usrp_set_fpga_tx_reset (udh, 1); // reset tx and rx paths
382 ok &= usrp_set_fpga_rx_reset (udh, 1);
383 ok &= usrp_set_fpga_tx_reset (udh, 0); // reset tx and rx paths
384 ok &= usrp_set_fpga_rx_reset (udh, 0);
387 fprintf (stderr, "usrp: failed to reset tx and/or rx path\n");
389 // Manually reset all regs except master control to zero.
390 // FIXME may want to remove this when we rework FPGA reset strategy.
391 // In the mean while, this gets us reproducible behavior.
392 for (int i = 0; i < FR_USER_0; i++){
393 if (i == FR_MASTER_CTRL)
395 usrp_write_fpga_reg(udh, i, 0);
398 power_down_9862s (udh); // on the rev1, power these down!
399 usrp_set_led (udh, 1, 0); // led 1 off
404 power_down_9862s (udh); // on the rev1, power these down!
409 // ----------------------------------------------------------------
412 usrp_set_led (libusb_device_handle *udh, int which, bool on)
414 int r = write_cmd (udh, VRQ_SET_LED, on, which, 0, 0);
420 usrp_set_hash (libusb_device_handle *udh, int which,
421 const unsigned char hash[USRP_HASH_SIZE])
425 // we use the Cypress firmware down load command to jam it in.
426 int r = _usb_control_transfer (udh, 0x40, 0xa0, hash_slot_addr[which], 0,
427 (unsigned char *) hash, USRP_HASH_SIZE, 1000);
428 return r == USRP_HASH_SIZE;
432 usrp_get_hash (libusb_device_handle *udh, int which,
433 unsigned char hash[USRP_HASH_SIZE])
437 // we use the Cypress firmware upload command to fetch it.
438 int r = _usb_control_transfer (udh, 0xc0, 0xa0, hash_slot_addr[which], 0,
439 (unsigned char *) hash, USRP_HASH_SIZE, 1000);
440 return r == USRP_HASH_SIZE;
446 usrp_set_switch (libusb_device_handle *udh, int cmd_byte, bool on)
448 return write_cmd (udh, cmd_byte, on, 0, 0, 0) == 0;
452 usrp1_fpga_write (libusb_device_handle *udh,
453 int regno, int value)
455 // on the rev1 usrp, we use the generic spi_write interface
457 unsigned char buf[4];
459 buf[0] = (value >> 24) & 0xff; // MSB first
460 buf[1] = (value >> 16) & 0xff;
461 buf[2] = (value >> 8) & 0xff;
462 buf[3] = (value >> 0) & 0xff;
464 return usrp_spi_write (udh, 0x00 | (regno & 0x7f),
466 SPI_FMT_MSB | SPI_FMT_HDR_1,
471 usrp1_fpga_read (libusb_device_handle *udh,
472 int regno, int *value)
475 unsigned char buf[4];
477 bool ok = usrp_spi_read (udh, 0x80 | (regno & 0x7f),
479 SPI_FMT_MSB | SPI_FMT_HDR_1,
483 *value = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
489 usrp_write_fpga_reg (libusb_device_handle *udh, int reg, int value)
491 switch (usrp_hw_rev (_get_usb_device (udh))){
492 case 0: // not supported ;)
496 return usrp1_fpga_write (udh, reg, value);
501 usrp_read_fpga_reg (libusb_device_handle *udh, int reg, int *value)
503 switch (usrp_hw_rev (_get_usb_device (udh))){
504 case 0: // not supported ;)
508 return usrp1_fpga_read (udh, reg, value);
513 usrp_set_fpga_reset (libusb_device_handle *udh, bool on)
515 return usrp_set_switch (udh, VRQ_FPGA_SET_RESET, on);
519 usrp_set_fpga_tx_enable (libusb_device_handle *udh, bool on)
521 return usrp_set_switch (udh, VRQ_FPGA_SET_TX_ENABLE, on);
525 usrp_set_fpga_rx_enable (libusb_device_handle *udh, bool on)
527 return usrp_set_switch (udh, VRQ_FPGA_SET_RX_ENABLE, on);
531 usrp_set_fpga_tx_reset (libusb_device_handle *udh, bool on)
533 return usrp_set_switch (udh, VRQ_FPGA_SET_TX_RESET, on);
537 usrp_set_fpga_rx_reset (libusb_device_handle *udh, bool on)
539 return usrp_set_switch (udh, VRQ_FPGA_SET_RX_RESET, on);
543 // ----------------------------------------------------------------
544 // conditional load stuff
547 compute_hash (const char *filename, unsigned char hash[USRP_HASH_SIZE])
549 assert (USRP_HASH_SIZE == 16);
550 memset (hash, 0, USRP_HASH_SIZE);
552 FILE *fp = fopen (filename, "rb");
557 int r = md5_stream (fp, hash);
563 static usrp_load_status_t
564 usrp_conditionally_load_something (libusb_device_handle *udh,
565 const char *filename,
568 bool loader (libusb_device_handle *,
570 unsigned char [USRP_HASH_SIZE]))
572 unsigned char file_hash[USRP_HASH_SIZE];
573 unsigned char usrp_hash[USRP_HASH_SIZE];
575 if (access (filename, R_OK) != 0){
580 if (!compute_hash (filename, file_hash))
584 && usrp_get_hash (udh, slot, usrp_hash)
585 && memcmp (file_hash, usrp_hash, USRP_HASH_SIZE) == 0)
586 return ULS_ALREADY_LOADED;
588 bool r = loader (udh, filename, file_hash);
597 usrp_load_firmware (libusb_device_handle *udh,
598 const char *filename,
601 return usrp_conditionally_load_something (udh, filename, force,
603 _usrp_load_firmware);
607 usrp_load_fpga (libusb_device_handle *udh,
608 const char *filename,
611 return usrp_conditionally_load_something (udh, filename, force,
616 static libusb_device_handle *
617 open_nth_cmd_interface (int nth, libusb_context *ctx)
620 libusb_device *udev = usrp_find_device (nth, false, ctx);
622 fprintf (stderr, "usrp: failed to find usrp[%d]\n", nth);
626 libusb_device_handle *udh;
628 udh = usrp_open_cmd_interface (udev);
630 // FIXME this could be because somebody else has it open.
631 // We should delay and retry...
632 fprintf (stderr, "open_nth_cmd_interface: open_cmd_interface failed\n");
640 our_nanosleep (const struct timespec *delay)
642 struct timespec new_delay = *delay;
643 struct timespec remainder;
646 int r = nanosleep (&new_delay, &remainder);
650 new_delay = remainder;
652 perror ("nanosleep");
659 mdelay (int millisecs)
662 ts.tv_sec = millisecs / 1000;
663 ts.tv_nsec = (millisecs - (1000 * ts.tv_sec)) * 1000000;
664 return our_nanosleep (&ts);
669 usrp_load_firmware_nth (int nth, const char *filename, bool force, libusb_context *ctx)
671 libusb_device_handle *udh = open_nth_cmd_interface (nth, ctx);
675 usrp_load_status_t s = usrp_load_firmware (udh, filename, force);
676 usrp_close_interface (udh);
680 case ULS_ALREADY_LOADED: // nothing changed...
681 return ULS_ALREADY_LOADED;
685 // we loaded firmware successfully.
687 // It's highly likely that the board will renumerate (simulate a
688 // disconnect/reconnect sequence), invalidating our current
691 // FIXME. Turn this into a loop that rescans until we refind ourselves
693 struct timespec t; // delay for 1 second
701 case ULS_ERROR: // some kind of problem
707 load_status_msg (usrp_load_status_t s, const char *type, const char *filename)
709 char *e = getenv("USRP_VERBOSE");
710 bool verbose = e != 0;
714 fprintf (stderr, "usrp: failed to load %s %s.\n", type, filename);
717 case ULS_ALREADY_LOADED:
719 fprintf (stderr, "usrp: %s %s already loaded.\n", type, filename);
724 fprintf (stderr, "usrp: %s %s loaded successfully.\n", type, filename);
730 usrp_load_standard_bits (int nth, bool force,
731 const std::string fpga_filename,
732 const std::string firmware_filename,
735 usrp_load_status_t s;
736 const char *filename;
737 const char *proto_filename;
740 // first, figure out what hardware rev we're dealing with
742 libusb_device *udev = usrp_find_device (nth, false, ctx);
744 fprintf (stderr, "usrp: failed to find usrp[%d]\n", nth);
747 hw_rev = usrp_hw_rev (udev);
750 // start by loading the firmware
752 proto_filename = get_proto_filename(firmware_filename, "USRP_FIRMWARE",
753 default_firmware_filename);
754 filename = find_file(proto_filename, hw_rev);
756 fprintf (stderr, "Can't find firmware: %s\n", proto_filename);
759 s = usrp_load_firmware_nth (nth, filename, force, ctx);
760 load_status_msg (s, "firmware", filename);
765 // if we actually loaded firmware, we must reload fpga ...
769 // now move on to the fpga configuration bitstream
771 proto_filename = get_proto_filename(fpga_filename, "USRP_FPGA",
772 default_fpga_filename);
773 filename = find_file (proto_filename, hw_rev);
775 fprintf (stderr, "Can't find fpga bitstream: %s\n", proto_filename);
778 libusb_device_handle *udh = open_nth_cmd_interface (nth, ctx);
782 s = usrp_load_fpga (udh, filename, force);
783 usrp_close_interface (udh);
784 load_status_msg (s, "fpga bitstream", filename);
794 _usrp_get_status (libusb_device_handle *udh, int which, bool *trouble)
796 unsigned char status;
799 if (write_cmd (udh, VRQ_GET_STATUS, 0, which,
800 &status, sizeof (status)) != sizeof (status))
808 usrp_check_rx_overrun (libusb_device_handle *udh, bool *overrun_p)
810 return _usrp_get_status (udh, GS_RX_OVERRUN, overrun_p);
814 usrp_check_tx_underrun (libusb_device_handle *udh, bool *underrun_p)
816 return _usrp_get_status (udh, GS_TX_UNDERRUN, underrun_p);
821 usrp_i2c_write (libusb_device_handle *udh, int i2c_addr,
822 const void *buf, int len)
824 if (len < 1 || len > MAX_EP0_PKTSIZE)
827 return write_cmd (udh, VRQ_I2C_WRITE, i2c_addr, 0,
828 (unsigned char *) buf, len) == len;
833 usrp_i2c_read (libusb_device_handle *udh, int i2c_addr,
836 if (len < 1 || len > MAX_EP0_PKTSIZE)
839 return write_cmd (udh, VRQ_I2C_READ, i2c_addr, 0,
840 (unsigned char *) buf, len) == len;
844 usrp_spi_write (libusb_device_handle *udh,
845 int optional_header, int enables, int format,
846 const void *buf, int len)
848 if (len < 0 || len > MAX_EP0_PKTSIZE)
851 return write_cmd (udh, VRQ_SPI_WRITE,
853 ((enables & 0xff) << 8) | (format & 0xff),
854 (unsigned char *) buf, len) == len;
859 usrp_spi_read (libusb_device_handle *udh,
860 int optional_header, int enables, int format,
863 if (len < 0 || len > MAX_EP0_PKTSIZE)
866 return write_cmd (udh, VRQ_SPI_READ,
868 ((enables & 0xff) << 8) | (format & 0xff),
869 (unsigned char *) buf, len) == len;
873 usrp_9862_write (libusb_device_handle *udh, int which_codec,
874 int regno, int value)
877 fprintf (stderr, "usrp_9862_write which = %d, reg = %2d, val = %3d (0x%02x)\n",
878 which_codec, regno, value, value);
880 unsigned char buf[1];
884 return usrp_spi_write (udh, 0x00 | (regno & 0x3f),
885 which_codec == 0 ? SPI_ENABLE_CODEC_A : SPI_ENABLE_CODEC_B,
886 SPI_FMT_MSB | SPI_FMT_HDR_1,
891 usrp_9862_read (libusb_device_handle *udh, int which_codec,
892 int regno, unsigned char *value)
894 return usrp_spi_read (udh, 0x80 | (regno & 0x3f),
895 which_codec == 0 ? SPI_ENABLE_CODEC_A : SPI_ENABLE_CODEC_B,
896 SPI_FMT_MSB | SPI_FMT_HDR_1,
901 usrp_9862_write_many (libusb_device_handle *udh,
903 const unsigned char *buf,
907 return false; // must be even
912 result &= usrp_9862_write (udh, which_codec, buf[0], buf[1]);
922 usrp_9862_write_many_all (libusb_device_handle *udh,
923 const unsigned char *buf, int len)
925 // FIXME handle 2/2 and 4/4 versions
928 result = usrp_9862_write_many (udh, 0, buf, len);
929 result &= usrp_9862_write_many (udh, 1, buf, len);
934 power_down_9862s (libusb_device_handle *udh)
936 static const unsigned char regs[] = {
937 REG_RX_PWR_DN, 0x01, // everything
938 REG_TX_PWR_DN, 0x0f, // pwr dn digital and analog_both
939 REG_TX_MODULATOR, 0x00 // coarse & fine modulators disabled
942 switch (usrp_hw_rev (_get_usb_device (udh))){
947 usrp_9862_write_many_all (udh, regs, sizeof (regs));
953 static const int EEPROM_PAGESIZE = 16;
956 usrp_eeprom_write (libusb_device_handle *udh, int i2c_addr,
957 int eeprom_offset, const void *buf, int len)
959 unsigned char cmd[2];
960 const unsigned char *p = (unsigned char *) buf;
962 // The simplest thing that could possibly work:
963 // all writes are single byte writes.
965 // We could speed this up using the page write feature,
966 // but we write so infrequently, why bother...
969 cmd[0] = eeprom_offset++;
971 bool r = usrp_i2c_write (udh, i2c_addr, cmd, sizeof (cmd));
972 mdelay (10); // delay 10ms worst case write time
981 usrp_eeprom_read (libusb_device_handle *udh, int i2c_addr,
982 int eeprom_offset, void *buf, int len)
984 unsigned char *p = (unsigned char *) buf;
986 // We setup a random read by first doing a "zero byte write".
987 // Writes carry an address. Reads use an implicit address.
989 unsigned char cmd[1];
990 cmd[0] = eeprom_offset;
991 if (!usrp_i2c_write (udh, i2c_addr, cmd, sizeof (cmd)))
995 int n = std::min (len, MAX_EP0_PKTSIZE);
996 if (!usrp_i2c_read (udh, i2c_addr, p, n))
1004 // ----------------------------------------------------------------
1007 slot_to_codec (int slot, int *which_codec)
1023 fprintf (stderr, "usrp_prims:slot_to_codec: invalid slot = %d\n", slot);
1030 tx_slot_p (int slot)
1043 usrp_write_aux_dac (libusb_device_handle *udh, int slot,
1044 int which_dac, int value)
1048 if (!slot_to_codec (slot, &which_codec))
1051 if (!(0 <= which_dac && which_dac < 4)){
1052 fprintf (stderr, "usrp_write_aux_dac: invalid dac = %d\n", which_dac);
1056 value &= 0x0fff; // mask to 12-bits
1058 if (which_dac == 3){
1059 // dac 3 is really 12-bits. Use value as is.
1061 r &= usrp_9862_write (udh, which_codec, 43, (value >> 4)); // most sig
1062 r &= usrp_9862_write (udh, which_codec, 42, (value & 0xf) << 4); // least sig
1066 // dac 0, 1, and 2 are really 8 bits.
1067 value = value >> 4; // shift value appropriately
1068 return usrp_9862_write (udh, which_codec, 36 + which_dac, value);
1074 usrp_read_aux_adc (libusb_device_handle *udh, int slot,
1075 int which_adc, int *value)
1080 if (!slot_to_codec (slot, &which_codec))
1083 if (!(0 <= which_codec && which_codec < 2)){
1084 fprintf (stderr, "usrp_read_aux_adc: invalid adc = %d\n", which_adc);
1088 unsigned char aux_adc_control =
1089 AUX_ADC_CTRL_REFSEL_A // on chip reference
1090 | AUX_ADC_CTRL_REFSEL_B; // on chip reference
1092 int rd_reg = 26; // base address of two regs to read for result
1094 // program the ADC mux bits
1095 if (tx_slot_p (slot))
1096 aux_adc_control |= AUX_ADC_CTRL_SELECT_A2 | AUX_ADC_CTRL_SELECT_B2;
1099 aux_adc_control |= AUX_ADC_CTRL_SELECT_A1 | AUX_ADC_CTRL_SELECT_B1;
1102 // I'm not sure if we can set the mux and issue a start conversion
1103 // in the same cycle, so let's do them one at a time.
1105 usrp_9862_write (udh, which_codec, 34, aux_adc_control);
1108 aux_adc_control |= AUX_ADC_CTRL_START_A;
1111 aux_adc_control |= AUX_ADC_CTRL_START_B;
1114 // start the conversion
1115 usrp_9862_write (udh, which_codec, 34, aux_adc_control);
1117 // read the 10-bit result back
1118 unsigned char v_lo = 0;
1119 unsigned char v_hi = 0;
1120 bool r = usrp_9862_read (udh, which_codec, rd_reg, &v_lo);
1121 r &= usrp_9862_read (udh, which_codec, rd_reg + 1, &v_hi);
1124 *value = ((v_hi << 2) | ((v_lo >> 6) & 0x3)) << 2; // format as 12-bit
1129 // ----------------------------------------------------------------
1131 static int slot_to_i2c_addr (int slot)
1134 case SLOT_TX_A: return I2C_ADDR_TX_A;
1135 case SLOT_RX_A: return I2C_ADDR_RX_A;
1136 case SLOT_TX_B: return I2C_ADDR_TX_B;
1137 case SLOT_RX_B: return I2C_ADDR_RX_B;
1143 set_chksum (unsigned char *buf)
1147 for (i = 0; i < DB_EEPROM_CLEN - 1; i++)
1152 static usrp_dbeeprom_status_t
1153 read_dboard_eeprom (libusb_device_handle *udh,
1154 int slot_id, unsigned char *buf)
1156 int i2c_addr = slot_to_i2c_addr (slot_id);
1158 return UDBE_BAD_SLOT;
1160 if (!usrp_eeprom_read (udh, i2c_addr, 0, buf, DB_EEPROM_CLEN))
1161 return UDBE_NO_EEPROM;
1163 if (buf[DB_EEPROM_MAGIC] != DB_EEPROM_MAGIC_VALUE)
1164 return UDBE_INVALID_EEPROM;
1167 for (unsigned int i = 0; i < DB_EEPROM_CLEN; i++)
1170 if ((sum & 0xff) != 0)
1171 return UDBE_INVALID_EEPROM;
1176 usrp_dbeeprom_status_t
1177 usrp_read_dboard_eeprom (libusb_device_handle *udh,
1178 int slot_id, usrp_dboard_eeprom *eeprom)
1180 unsigned char buf[DB_EEPROM_CLEN];
1182 memset (eeprom, 0, sizeof (*eeprom));
1184 usrp_dbeeprom_status_t s = read_dboard_eeprom (udh, slot_id, buf);
1188 eeprom->id = (buf[DB_EEPROM_ID_MSB] << 8) | buf[DB_EEPROM_ID_LSB];
1189 eeprom->oe = (buf[DB_EEPROM_OE_MSB] << 8) | buf[DB_EEPROM_OE_LSB];
1190 eeprom->offset[0] = (buf[DB_EEPROM_OFFSET_0_MSB] << 8) | buf[DB_EEPROM_OFFSET_0_LSB];
1191 eeprom->offset[1] = (buf[DB_EEPROM_OFFSET_1_MSB] << 8) | buf[DB_EEPROM_OFFSET_1_LSB];
1197 usrp_write_dboard_offsets (libusb_device_handle *udh, int slot_id,
1198 short offset0, short offset1)
1200 unsigned char buf[DB_EEPROM_CLEN];
1202 usrp_dbeeprom_status_t s = read_dboard_eeprom (udh, slot_id, buf);
1206 buf[DB_EEPROM_OFFSET_0_LSB] = (offset0 >> 0) & 0xff;
1207 buf[DB_EEPROM_OFFSET_0_MSB] = (offset0 >> 8) & 0xff;
1208 buf[DB_EEPROM_OFFSET_1_LSB] = (offset1 >> 0) & 0xff;
1209 buf[DB_EEPROM_OFFSET_1_MSB] = (offset1 >> 8) & 0xff;
1212 return usrp_eeprom_write (udh, slot_to_i2c_addr (slot_id),
1213 0, buf, sizeof (buf));
1216 // ----------------------------------------------------------------
1219 usrp_serial_number(libusb_device_handle *udh)
1221 libusb_device_descriptor desc =
1222 _get_usb_device_descriptor (_get_usb_device (udh));
1224 unsigned char iserial = desc.iSerialNumber;
1228 unsigned char buf[1024];
1229 if (_get_usb_string_descriptor (udh, iserial, buf, sizeof(buf)) < 0)