3 * Copyright 2003,2004,2006,2009 Free Software Foundation, Inc.
5 * This file is part of GNU Radio
7 * GNU Radio is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 3, or (at your option)
12 * GNU Radio is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with GNU Radio; see the file COPYING. If not, write to
19 * the Free Software Foundation, Inc., 51 Franklin Street,
20 * Boston, MA 02110-1301, USA.
27 #include "usrp/usrp_prims.h"
28 #include "usrp_commands.h"
30 #include "usrp_i2c_addr.h"
31 #include "fpga_regs_common.h"
32 #include "fpga_regs_standard.h"
39 #include <time.h> // FIXME should check with autoconf (nanosleep)
45 #include <libusb-1.0/libusb.h>
56 using namespace ad9862;
58 static const int FIRMWARE_HASH_SLOT = 0;
59 static const int FPGA_HASH_SLOT = 1;
61 static const int hash_slot_addr[2] = {
62 USRP_HASH_SLOT_0_ADDR,
66 static const char *default_firmware_filename = "std.ihx";
67 static const char *default_fpga_filename = "std_2rxhb_2tx.rbf";
70 #include "std_paths.h"
74 find_file (const char *filename, int hw_rev)
76 const char **sp = std_paths;
77 static char path[1000];
80 s = getenv("USRP_PATH");
82 snprintf (path, sizeof (path), "%s/rev%d/%s", s, hw_rev, filename);
83 if (access (path, R_OK) == 0)
88 snprintf (path, sizeof (path), "%s/rev%d/%s", *sp, hw_rev, filename);
89 if (access (path, R_OK) == 0)
97 get_proto_filename(const std::string user_filename, const char *env_var, const char *def)
99 if (user_filename.length() != 0)
100 return user_filename.c_str();
102 char *s = getenv(env_var);
110 void power_down_9862s (libusb_device_handle *udh);
112 // ----------------------------------------------------------------
115 usrp_usrp0_p (libusb_device *q)
117 return usrp_usrp_p (q) && usrp_hw_rev (q) == 0;
121 usrp_usrp1_p (libusb_device *q)
123 return usrp_usrp_p (q) && usrp_hw_rev (q) == 1;
127 usrp_usrp2_p (libusb_device *q)
129 return usrp_usrp_p (q) && usrp_hw_rev (q) == 2;
134 usrp_unconfigured_usrp_p (libusb_device *q)
136 return usrp_usrp_p (q) && !_usrp_configured_p (q);
140 usrp_configured_usrp_p (libusb_device *q)
142 return usrp_usrp_p (q) && _usrp_configured_p (q);
145 libusb_device_handle *
146 usrp_open_cmd_interface (libusb_device *dev)
148 return usrp_open_interface (dev, USRP_CMD_INTERFACE, USRP_CMD_ALTINTERFACE);
151 libusb_device_handle *
152 usrp_open_rx_interface (libusb_device *dev)
154 return usrp_open_interface (dev, USRP_RX_INTERFACE, USRP_RX_ALTINTERFACE);
157 libusb_device_handle *
158 usrp_open_tx_interface (libusb_device *dev)
160 return usrp_open_interface (dev, USRP_TX_INTERFACE, USRP_TX_ALTINTERFACE);
164 // ----------------------------------------------------------------
165 // whack the CPUCS register using the upload RAM vendor extension
168 reset_cpu (libusb_device_handle *udh, bool reset_p)
173 v = 1; // hold processor in reset
175 v = 0; // release reset
177 return write_internal_ram (udh, &v, 0xE600, 1);
180 // ----------------------------------------------------------------
181 // Load intel format file into cypress FX2 (8051)
184 _usrp_load_firmware (libusb_device_handle *udh, const char *filename,
185 unsigned char hash[USRP_HASH_SIZE])
187 FILE *f = fopen (filename, "ra");
193 if (!reset_cpu (udh, true)) // hold CPU in reset while loading firmware
201 unsigned char data[256];
202 unsigned char checksum, a;
207 fgets(s, sizeof (s), f); /* we should not use more than 263 bytes normally */
209 fprintf(stderr,"%s: invalid line: \"%s\"\n", filename, s);
212 sscanf(s+1, "%02x", &length);
213 sscanf(s+3, "%04x", &addr);
214 sscanf(s+7, "%02x", &type);
218 a=length+(addr &0xff)+(addr>>8)+type;
219 for(i=0;i<length;i++){
220 sscanf (s+9+i*2,"%02x", &b);
225 sscanf (s+9+length*2,"%02x", &b);
227 if (((a+checksum)&0xff)!=0x00){
228 fprintf (stderr, " ** Checksum failed: got 0x%02x versus 0x%02x\n", (-a)&0xff, checksum);
231 if (!write_internal_ram (udh, data, addr, length))
234 else if (type == 0x01){ // EOF
237 else if (type == 0x02){
238 fprintf(stderr, "Extended address: whatever I do with it?\n");
239 fprintf (stderr, "%s: invalid line: \"%s\"\n", filename, s);
244 // we jam the hash value into the FX2 memory before letting
245 // the cpu out of reset. When it comes out of reset it
246 // may renumerate which will invalidate udh.
248 if (!usrp_set_hash (udh, FIRMWARE_HASH_SLOT, hash))
249 fprintf (stderr, "usrp: failed to write firmware hash slot\n");
251 if (!reset_cpu (udh, false)) // take CPU out of reset
262 // ----------------------------------------------------------------
266 _usrp_load_fpga (libusb_device_handle *udh, const char *filename,
267 unsigned char hash[USRP_HASH_SIZE])
271 FILE *fp = fopen (filename, "rb");
277 unsigned char buf[MAX_EP0_PKTSIZE]; // 64 is max size of EP0 packet on FX2
280 usrp_set_led (udh, 1, 1); // led 1 on
283 // reset FPGA (and on rev1 both AD9862's, thus killing clock)
284 usrp_set_fpga_reset (udh, 1); // hold fpga in reset
286 if (write_cmd (udh, VRQ_FPGA_LOAD, 0, FL_BEGIN, 0, 0) != 0)
289 while ((n = fread (buf, 1, sizeof (buf), fp)) > 0){
290 if (write_cmd (udh, VRQ_FPGA_LOAD, 0, FL_XFER, buf, n) != n)
294 if (write_cmd (udh, VRQ_FPGA_LOAD, 0, FL_END, 0, 0) != 0)
299 if (!usrp_set_hash (udh, FPGA_HASH_SLOT, hash))
300 fprintf (stderr, "usrp: failed to write fpga hash slot\n");
302 // On the rev1 USRP, the {tx,rx}_{enable,reset} bits are
303 // controlled over the serial bus, and hence aren't observed until
304 // we've got a good fpga bitstream loaded.
306 usrp_set_fpga_reset (udh, 0); // fpga out of master reset
308 // now these commands will work
310 ok &= usrp_set_fpga_tx_enable (udh, 0);
311 ok &= usrp_set_fpga_rx_enable (udh, 0);
313 ok &= usrp_set_fpga_tx_reset (udh, 1); // reset tx and rx paths
314 ok &= usrp_set_fpga_rx_reset (udh, 1);
315 ok &= usrp_set_fpga_tx_reset (udh, 0); // reset tx and rx paths
316 ok &= usrp_set_fpga_rx_reset (udh, 0);
319 fprintf (stderr, "usrp: failed to reset tx and/or rx path\n");
321 // Manually reset all regs except master control to zero.
322 // FIXME may want to remove this when we rework FPGA reset strategy.
323 // In the mean while, this gets us reproducible behavior.
324 for (int i = 0; i < FR_USER_0; i++){
325 if (i == FR_MASTER_CTRL)
327 usrp_write_fpga_reg(udh, i, 0);
330 power_down_9862s (udh); // on the rev1, power these down!
331 usrp_set_led (udh, 1, 0); // led 1 off
336 power_down_9862s (udh); // on the rev1, power these down!
341 // ----------------------------------------------------------------
344 usrp_set_led (libusb_device_handle *udh, int which, bool on)
346 int r = write_cmd (udh, VRQ_SET_LED, on, which, 0, 0);
353 usrp_set_switch (libusb_device_handle *udh, int cmd_byte, bool on)
355 return write_cmd (udh, cmd_byte, on, 0, 0, 0) == 0;
359 usrp1_fpga_write (libusb_device_handle *udh,
360 int regno, int value)
362 // on the rev1 usrp, we use the generic spi_write interface
364 unsigned char buf[4];
366 buf[0] = (value >> 24) & 0xff; // MSB first
367 buf[1] = (value >> 16) & 0xff;
368 buf[2] = (value >> 8) & 0xff;
369 buf[3] = (value >> 0) & 0xff;
371 return usrp_spi_write (udh, 0x00 | (regno & 0x7f),
373 SPI_FMT_MSB | SPI_FMT_HDR_1,
378 usrp1_fpga_read (libusb_device_handle *udh,
379 int regno, int *value)
382 unsigned char buf[4];
384 bool ok = usrp_spi_read (udh, 0x80 | (regno & 0x7f),
386 SPI_FMT_MSB | SPI_FMT_HDR_1,
390 *value = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
397 usrp_set_fpga_reset (libusb_device_handle *udh, bool on)
399 return usrp_set_switch (udh, VRQ_FPGA_SET_RESET, on);
403 usrp_set_fpga_tx_enable (libusb_device_handle *udh, bool on)
405 return usrp_set_switch (udh, VRQ_FPGA_SET_TX_ENABLE, on);
409 usrp_set_fpga_rx_enable (libusb_device_handle *udh, bool on)
411 return usrp_set_switch (udh, VRQ_FPGA_SET_RX_ENABLE, on);
415 usrp_set_fpga_tx_reset (libusb_device_handle *udh, bool on)
417 return usrp_set_switch (udh, VRQ_FPGA_SET_TX_RESET, on);
421 usrp_set_fpga_rx_reset (libusb_device_handle *udh, bool on)
423 return usrp_set_switch (udh, VRQ_FPGA_SET_RX_RESET, on);
427 // ----------------------------------------------------------------
428 // conditional load stuff
431 compute_hash (const char *filename, unsigned char hash[USRP_HASH_SIZE])
433 assert (USRP_HASH_SIZE == 16);
434 memset (hash, 0, USRP_HASH_SIZE);
436 FILE *fp = fopen (filename, "rb");
441 int r = md5_stream (fp, hash);
447 static usrp_load_status_t
448 usrp_conditionally_load_something (libusb_device_handle *udh,
449 const char *filename,
452 bool loader (libusb_device_handle *,
454 unsigned char [USRP_HASH_SIZE]))
456 unsigned char file_hash[USRP_HASH_SIZE];
457 unsigned char usrp_hash[USRP_HASH_SIZE];
459 if (access (filename, R_OK) != 0){
464 if (!compute_hash (filename, file_hash))
468 && usrp_get_hash (udh, slot, usrp_hash)
469 && memcmp (file_hash, usrp_hash, USRP_HASH_SIZE) == 0)
470 return ULS_ALREADY_LOADED;
472 bool r = loader (udh, filename, file_hash);
481 usrp_load_firmware (libusb_device_handle *udh,
482 const char *filename,
485 return usrp_conditionally_load_something (udh, filename, force,
487 _usrp_load_firmware);
491 usrp_load_fpga (libusb_device_handle *udh,
492 const char *filename,
495 return usrp_conditionally_load_something (udh, filename, force,
500 static libusb_device_handle *
501 open_nth_cmd_interface (int nth, libusb_context *ctx)
504 libusb_device *udev = usrp_find_device (nth, false, ctx);
506 fprintf (stderr, "usrp: failed to find usrp[%d]\n", nth);
510 libusb_device_handle *udh;
512 udh = usrp_open_cmd_interface (udev);
514 // FIXME this could be because somebody else has it open.
515 // We should delay and retry...
516 fprintf (stderr, "open_nth_cmd_interface: open_cmd_interface failed\n");
524 our_nanosleep (const struct timespec *delay)
526 struct timespec new_delay = *delay;
527 struct timespec remainder;
530 int r = nanosleep (&new_delay, &remainder);
534 new_delay = remainder;
536 perror ("nanosleep");
543 mdelay (int millisecs)
546 ts.tv_sec = millisecs / 1000;
547 ts.tv_nsec = (millisecs - (1000 * ts.tv_sec)) * 1000000;
548 return our_nanosleep (&ts);
553 usrp_load_firmware_nth (int nth, const char *filename, bool force, libusb_context *ctx)
555 libusb_device_handle *udh = open_nth_cmd_interface (nth, ctx);
559 usrp_load_status_t s = usrp_load_firmware (udh, filename, force);
560 usrp_close_interface (udh);
564 case ULS_ALREADY_LOADED: // nothing changed...
565 return ULS_ALREADY_LOADED;
569 // we loaded firmware successfully.
571 // It's highly likely that the board will renumerate (simulate a
572 // disconnect/reconnect sequence), invalidating our current
575 // FIXME. Turn this into a loop that rescans until we refind ourselves
577 struct timespec t; // delay for 1 second
585 case ULS_ERROR: // some kind of problem
591 load_status_msg (usrp_load_status_t s, const char *type, const char *filename)
593 char *e = getenv("USRP_VERBOSE");
594 bool verbose = e != 0;
598 fprintf (stderr, "usrp: failed to load %s %s.\n", type, filename);
601 case ULS_ALREADY_LOADED:
603 fprintf (stderr, "usrp: %s %s already loaded.\n", type, filename);
608 fprintf (stderr, "usrp: %s %s loaded successfully.\n", type, filename);
614 usrp_load_standard_bits (int nth, bool force,
615 const std::string fpga_filename,
616 const std::string firmware_filename,
619 usrp_load_status_t s;
620 const char *filename;
621 const char *proto_filename;
624 // first, figure out what hardware rev we're dealing with
626 libusb_device *udev = usrp_find_device (nth, false, ctx);
628 fprintf (stderr, "usrp: failed to find usrp[%d]\n", nth);
631 hw_rev = usrp_hw_rev (udev);
634 // start by loading the firmware
636 proto_filename = get_proto_filename(firmware_filename, "USRP_FIRMWARE",
637 default_firmware_filename);
638 filename = find_file(proto_filename, hw_rev);
640 fprintf (stderr, "Can't find firmware: %s\n", proto_filename);
643 s = usrp_load_firmware_nth (nth, filename, force, ctx);
644 load_status_msg (s, "firmware", filename);
649 // if we actually loaded firmware, we must reload fpga ...
653 // now move on to the fpga configuration bitstream
655 proto_filename = get_proto_filename(fpga_filename, "USRP_FPGA",
656 default_fpga_filename);
657 filename = find_file (proto_filename, hw_rev);
659 fprintf (stderr, "Can't find fpga bitstream: %s\n", proto_filename);
662 libusb_device_handle *udh = open_nth_cmd_interface (nth, ctx);
666 s = usrp_load_fpga (udh, filename, force);
667 usrp_close_interface (udh);
668 load_status_msg (s, "fpga bitstream", filename);
678 _usrp_get_status (libusb_device_handle *udh, int which, bool *trouble)
680 unsigned char status;
683 if (write_cmd (udh, VRQ_GET_STATUS, 0, which,
684 &status, sizeof (status)) != sizeof (status))
692 usrp_check_rx_overrun (libusb_device_handle *udh, bool *overrun_p)
694 return _usrp_get_status (udh, GS_RX_OVERRUN, overrun_p);
698 usrp_check_tx_underrun (libusb_device_handle *udh, bool *underrun_p)
700 return _usrp_get_status (udh, GS_TX_UNDERRUN, underrun_p);
705 usrp_i2c_write (libusb_device_handle *udh, int i2c_addr,
706 const void *buf, int len)
708 if (len < 1 || len > MAX_EP0_PKTSIZE)
711 return write_cmd (udh, VRQ_I2C_WRITE, i2c_addr, 0,
712 (unsigned char *) buf, len) == len;
717 usrp_i2c_read (libusb_device_handle *udh, int i2c_addr,
720 if (len < 1 || len > MAX_EP0_PKTSIZE)
723 return write_cmd (udh, VRQ_I2C_READ, i2c_addr, 0,
724 (unsigned char *) buf, len) == len;
728 usrp_spi_write (libusb_device_handle *udh,
729 int optional_header, int enables, int format,
730 const void *buf, int len)
732 if (len < 0 || len > MAX_EP0_PKTSIZE)
735 return write_cmd (udh, VRQ_SPI_WRITE,
737 ((enables & 0xff) << 8) | (format & 0xff),
738 (unsigned char *) buf, len) == len;
743 usrp_spi_read (libusb_device_handle *udh,
744 int optional_header, int enables, int format,
747 if (len < 0 || len > MAX_EP0_PKTSIZE)
750 return write_cmd (udh, VRQ_SPI_READ,
752 ((enables & 0xff) << 8) | (format & 0xff),
753 (unsigned char *) buf, len) == len;
757 usrp_9862_write (libusb_device_handle *udh, int which_codec,
758 int regno, int value)
761 fprintf (stderr, "usrp_9862_write which = %d, reg = %2d, val = %3d (0x%02x)\n",
762 which_codec, regno, value, value);
764 unsigned char buf[1];
768 return usrp_spi_write (udh, 0x00 | (regno & 0x3f),
769 which_codec == 0 ? SPI_ENABLE_CODEC_A : SPI_ENABLE_CODEC_B,
770 SPI_FMT_MSB | SPI_FMT_HDR_1,
775 usrp_9862_read (libusb_device_handle *udh, int which_codec,
776 int regno, unsigned char *value)
778 return usrp_spi_read (udh, 0x80 | (regno & 0x3f),
779 which_codec == 0 ? SPI_ENABLE_CODEC_A : SPI_ENABLE_CODEC_B,
780 SPI_FMT_MSB | SPI_FMT_HDR_1,
785 usrp_9862_write_many (libusb_device_handle *udh,
787 const unsigned char *buf,
791 return false; // must be even
796 result &= usrp_9862_write (udh, which_codec, buf[0], buf[1]);
806 usrp_9862_write_many_all (libusb_device_handle *udh,
807 const unsigned char *buf, int len)
809 // FIXME handle 2/2 and 4/4 versions
812 result = usrp_9862_write_many (udh, 0, buf, len);
813 result &= usrp_9862_write_many (udh, 1, buf, len);
818 static const int EEPROM_PAGESIZE = 16;
821 usrp_eeprom_write (libusb_device_handle *udh, int i2c_addr,
822 int eeprom_offset, const void *buf, int len)
824 unsigned char cmd[2];
825 const unsigned char *p = (unsigned char *) buf;
827 // The simplest thing that could possibly work:
828 // all writes are single byte writes.
830 // We could speed this up using the page write feature,
831 // but we write so infrequently, why bother...
834 cmd[0] = eeprom_offset++;
836 bool r = usrp_i2c_write (udh, i2c_addr, cmd, sizeof (cmd));
837 mdelay (10); // delay 10ms worst case write time
846 usrp_eeprom_read (libusb_device_handle *udh, int i2c_addr,
847 int eeprom_offset, void *buf, int len)
849 unsigned char *p = (unsigned char *) buf;
851 // We setup a random read by first doing a "zero byte write".
852 // Writes carry an address. Reads use an implicit address.
854 unsigned char cmd[1];
855 cmd[0] = eeprom_offset;
856 if (!usrp_i2c_write (udh, i2c_addr, cmd, sizeof (cmd)))
860 int n = std::min (len, MAX_EP0_PKTSIZE);
861 if (!usrp_i2c_read (udh, i2c_addr, p, n))
869 // ----------------------------------------------------------------
872 slot_to_codec (int slot, int *which_codec)
888 fprintf (stderr, "usrp_prims:slot_to_codec: invalid slot = %d\n", slot);
908 usrp_write_aux_dac (libusb_device_handle *udh, int slot,
909 int which_dac, int value)
913 if (!slot_to_codec (slot, &which_codec))
916 if (!(0 <= which_dac && which_dac < 4)){
917 fprintf (stderr, "usrp_write_aux_dac: invalid dac = %d\n", which_dac);
921 value &= 0x0fff; // mask to 12-bits
924 // dac 3 is really 12-bits. Use value as is.
926 r &= usrp_9862_write (udh, which_codec, 43, (value >> 4)); // most sig
927 r &= usrp_9862_write (udh, which_codec, 42, (value & 0xf) << 4); // least sig
931 // dac 0, 1, and 2 are really 8 bits.
932 value = value >> 4; // shift value appropriately
933 return usrp_9862_write (udh, which_codec, 36 + which_dac, value);
939 usrp_read_aux_adc (libusb_device_handle *udh, int slot,
940 int which_adc, int *value)
945 if (!slot_to_codec (slot, &which_codec))
948 if (!(0 <= which_codec && which_codec < 2)){
949 fprintf (stderr, "usrp_read_aux_adc: invalid adc = %d\n", which_adc);
953 unsigned char aux_adc_control =
954 AUX_ADC_CTRL_REFSEL_A // on chip reference
955 | AUX_ADC_CTRL_REFSEL_B; // on chip reference
957 int rd_reg = 26; // base address of two regs to read for result
959 // program the ADC mux bits
960 if (tx_slot_p (slot))
961 aux_adc_control |= AUX_ADC_CTRL_SELECT_A2 | AUX_ADC_CTRL_SELECT_B2;
964 aux_adc_control |= AUX_ADC_CTRL_SELECT_A1 | AUX_ADC_CTRL_SELECT_B1;
967 // I'm not sure if we can set the mux and issue a start conversion
968 // in the same cycle, so let's do them one at a time.
970 usrp_9862_write (udh, which_codec, 34, aux_adc_control);
973 aux_adc_control |= AUX_ADC_CTRL_START_A;
976 aux_adc_control |= AUX_ADC_CTRL_START_B;
979 // start the conversion
980 usrp_9862_write (udh, which_codec, 34, aux_adc_control);
982 // read the 10-bit result back
983 unsigned char v_lo = 0;
984 unsigned char v_hi = 0;
985 bool r = usrp_9862_read (udh, which_codec, rd_reg, &v_lo);
986 r &= usrp_9862_read (udh, which_codec, rd_reg + 1, &v_hi);
989 *value = ((v_hi << 2) | ((v_lo >> 6) & 0x3)) << 2; // format as 12-bit
994 // ----------------------------------------------------------------
996 static int slot_to_i2c_addr (int slot)
999 case SLOT_TX_A: return I2C_ADDR_TX_A;
1000 case SLOT_RX_A: return I2C_ADDR_RX_A;
1001 case SLOT_TX_B: return I2C_ADDR_TX_B;
1002 case SLOT_RX_B: return I2C_ADDR_RX_B;
1008 set_chksum (unsigned char *buf)
1012 for (i = 0; i < DB_EEPROM_CLEN - 1; i++)
1017 static usrp_dbeeprom_status_t
1018 read_dboard_eeprom (libusb_device_handle *udh,
1019 int slot_id, unsigned char *buf)
1021 int i2c_addr = slot_to_i2c_addr (slot_id);
1023 return UDBE_BAD_SLOT;
1025 if (!usrp_eeprom_read (udh, i2c_addr, 0, buf, DB_EEPROM_CLEN))
1026 return UDBE_NO_EEPROM;
1028 if (buf[DB_EEPROM_MAGIC] != DB_EEPROM_MAGIC_VALUE)
1029 return UDBE_INVALID_EEPROM;
1032 for (unsigned int i = 0; i < DB_EEPROM_CLEN; i++)
1035 if ((sum & 0xff) != 0)
1036 return UDBE_INVALID_EEPROM;
1041 usrp_dbeeprom_status_t
1042 usrp_read_dboard_eeprom (libusb_device_handle *udh,
1043 int slot_id, usrp_dboard_eeprom *eeprom)
1045 unsigned char buf[DB_EEPROM_CLEN];
1047 memset (eeprom, 0, sizeof (*eeprom));
1049 usrp_dbeeprom_status_t s = read_dboard_eeprom (udh, slot_id, buf);
1053 eeprom->id = (buf[DB_EEPROM_ID_MSB] << 8) | buf[DB_EEPROM_ID_LSB];
1054 eeprom->oe = (buf[DB_EEPROM_OE_MSB] << 8) | buf[DB_EEPROM_OE_LSB];
1055 eeprom->offset[0] = (buf[DB_EEPROM_OFFSET_0_MSB] << 8) | buf[DB_EEPROM_OFFSET_0_LSB];
1056 eeprom->offset[1] = (buf[DB_EEPROM_OFFSET_1_MSB] << 8) | buf[DB_EEPROM_OFFSET_1_LSB];
1062 usrp_write_dboard_offsets (libusb_device_handle *udh, int slot_id,
1063 short offset0, short offset1)
1065 unsigned char buf[DB_EEPROM_CLEN];
1067 usrp_dbeeprom_status_t s = read_dboard_eeprom (udh, slot_id, buf);
1071 buf[DB_EEPROM_OFFSET_0_LSB] = (offset0 >> 0) & 0xff;
1072 buf[DB_EEPROM_OFFSET_0_MSB] = (offset0 >> 8) & 0xff;
1073 buf[DB_EEPROM_OFFSET_1_LSB] = (offset1 >> 0) & 0xff;
1074 buf[DB_EEPROM_OFFSET_1_MSB] = (offset1 >> 8) & 0xff;
1077 return usrp_eeprom_write (udh, slot_to_i2c_addr (slot_id),
1078 0, buf, sizeof (buf));