3 * Copyright 2003,2004,2006,2009 Free Software Foundation, Inc.
5 * This file is part of GNU Radio
7 * GNU Radio is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 3, or (at your option)
12 * GNU Radio is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with GNU Radio; see the file COPYING. If not, write to
19 * the Free Software Foundation, Inc., 51 Franklin Street,
20 * Boston, MA 02110-1301, USA.
27 #include "usrp_primsi.h"
28 #include "usrp_commands.h"
30 #include "usrp_i2c_addr.h"
31 #include "fpga_regs_common.h"
32 #include "fpga_regs_standard.h"
39 #include <time.h> // FIXME should check with autoconf (nanosleep)
43 #include "std_paths.h"
51 using namespace ad9862;
53 static const int FIRMWARE_HASH_SLOT = 0;
54 static const int FPGA_HASH_SLOT = 1;
56 static const int hash_slot_addr[2] = {
57 USRP_HASH_SLOT_0_ADDR,
61 static const char *default_firmware_filename = "std.ihx";
62 static const char *default_fpga_filename = "std_2rxhb_2tx.rbf";
65 find_file (const char *filename, int hw_rev)
67 const char **sp = std_paths;
68 static char path[1000];
71 s = getenv("USRP_PATH");
73 snprintf (path, sizeof (path), "%s/rev%d/%s", s, hw_rev, filename);
74 if (access (path, R_OK) == 0)
79 snprintf (path, sizeof (path), "%s/rev%d/%s", *sp, hw_rev, filename);
80 if (access (path, R_OK) == 0)
88 get_proto_filename(const std::string user_filename, const char *env_var, const char *def)
90 if (user_filename.length() != 0)
91 return user_filename.c_str();
93 char *s = getenv(env_var);
101 static void power_down_9862s (libusb_device_handle *udh);
104 // ----------------------------------------------------------------
107 * q must be a real USRP, not an FX2. Return its hardware rev number.
111 usrp_hw_rev (libusb_device *q)
113 libusb_device_descriptor desc = _get_usb_device_descriptor(q);
114 return desc.bcdDevice & 0x00FF;
118 * q must be a real USRP, not an FX2. Return true if it's configured.
121 _usrp_configured_p (libusb_device *q)
123 libusb_device_descriptor desc = _get_usb_device_descriptor(q);
124 return (desc.bcdDevice & 0xFF00) != 0;
128 usrp_usrp_p (libusb_device *q)
130 libusb_device_descriptor desc = _get_usb_device_descriptor(q);
131 return (desc.idVendor == USB_VID_FSF
132 && desc.idProduct == USB_PID_FSF_USRP);
136 usrp_fx2_p (libusb_device *q)
138 libusb_device_descriptor desc = _get_usb_device_descriptor(q);
139 return (desc.idVendor == USB_VID_CYPRESS
140 && desc.idProduct == USB_PID_CYPRESS_FX2);
144 usrp_usrp0_p (libusb_device *q)
146 return usrp_usrp_p (q) && usrp_hw_rev (q) == 0;
150 usrp_usrp1_p (libusb_device *q)
152 return usrp_usrp_p (q) && usrp_hw_rev (q) == 1;
156 usrp_usrp2_p (libusb_device *q)
158 return usrp_usrp_p (q) && usrp_hw_rev (q) == 2;
163 usrp_unconfigured_usrp_p (libusb_device *q)
165 return usrp_usrp_p (q) && !_usrp_configured_p (q);
169 usrp_configured_usrp_p (libusb_device *q)
171 return usrp_usrp_p (q) && _usrp_configured_p (q);
175 // ----------------------------------------------------------------
178 libusb_device_handle *
179 usrp_open_cmd_interface (libusb_device *dev)
181 return usrp_open_interface (dev, USRP_CMD_INTERFACE, USRP_CMD_ALTINTERFACE);
184 libusb_device_handle *
185 usrp_open_rx_interface (libusb_device *dev)
187 return usrp_open_interface (dev, USRP_RX_INTERFACE, USRP_RX_ALTINTERFACE);
190 libusb_device_handle *
191 usrp_open_tx_interface (libusb_device *dev)
193 return usrp_open_interface (dev, USRP_TX_INTERFACE, USRP_TX_ALTINTERFACE);
197 // ----------------------------------------------------------------
198 // write internal ram using Cypress vendor extension
201 write_internal_ram (libusb_device_handle *udh, unsigned char *buf,
202 int start_addr, size_t len)
207 int quanta = MAX_EP0_PKTSIZE;
209 for (addr = start_addr; addr < start_addr + (int) len; addr += quanta){
210 n = len + start_addr - addr;
214 a = _usb_control_transfer (udh, 0x40, 0xA0, addr, 0,
215 (unsigned char*)(buf + (addr - start_addr)), n, 1000);
218 fprintf(stderr,"write_internal_ram failed: %i\n", a);
226 // ----------------------------------------------------------------
227 // whack the CPUCS register using the upload RAM vendor extension
230 reset_cpu (libusb_device_handle *udh, bool reset_p)
235 v = 1; // hold processor in reset
237 v = 0; // release reset
239 return write_internal_ram (udh, &v, 0xE600, 1);
242 // ----------------------------------------------------------------
243 // Load intel format file into cypress FX2 (8051)
246 _usrp_load_firmware (libusb_device_handle *udh, const char *filename,
247 unsigned char hash[USRP_HASH_SIZE])
249 FILE *f = fopen (filename, "ra");
255 if (!reset_cpu (udh, true)) // hold CPU in reset while loading firmware
263 unsigned char data[256];
264 unsigned char checksum, a;
269 fgets(s, sizeof (s), f); /* we should not use more than 263 bytes normally */
271 fprintf(stderr,"%s: invalid line: \"%s\"\n", filename, s);
274 sscanf(s+1, "%02x", &length);
275 sscanf(s+3, "%04x", &addr);
276 sscanf(s+7, "%02x", &type);
280 a=length+(addr &0xff)+(addr>>8)+type;
281 for(i=0;i<length;i++){
282 sscanf (s+9+i*2,"%02x", &b);
287 sscanf (s+9+length*2,"%02x", &b);
289 if (((a+checksum)&0xff)!=0x00){
290 fprintf (stderr, " ** Checksum failed: got 0x%02x versus 0x%02x\n", (-a)&0xff, checksum);
293 if (!write_internal_ram (udh, data, addr, length))
296 else if (type == 0x01){ // EOF
299 else if (type == 0x02){
300 fprintf(stderr, "Extended address: whatever I do with it?\n");
301 fprintf (stderr, "%s: invalid line: \"%s\"\n", filename, s);
306 // we jam the hash value into the FX2 memory before letting
307 // the cpu out of reset. When it comes out of reset it
308 // may renumerate which will invalidate udh.
310 if (!usrp_set_hash (udh, FIRMWARE_HASH_SLOT, hash))
311 fprintf (stderr, "usrp: failed to write firmware hash slot\n");
313 if (!reset_cpu (udh, false)) // take CPU out of reset
324 // ----------------------------------------------------------------
328 _usrp_load_fpga (libusb_device_handle *udh, const char *filename,
329 unsigned char hash[USRP_HASH_SIZE])
333 FILE *fp = fopen (filename, "rb");
339 unsigned char buf[MAX_EP0_PKTSIZE]; // 64 is max size of EP0 packet on FX2
342 usrp_set_led (udh, 1, 1); // led 1 on
345 // reset FPGA (and on rev1 both AD9862's, thus killing clock)
346 usrp_set_fpga_reset (udh, 1); // hold fpga in reset
348 if (write_cmd (udh, VRQ_FPGA_LOAD, 0, FL_BEGIN, 0, 0) != 0)
351 while ((n = fread (buf, 1, sizeof (buf), fp)) > 0){
352 if (write_cmd (udh, VRQ_FPGA_LOAD, 0, FL_XFER, buf, n) != n)
356 if (write_cmd (udh, VRQ_FPGA_LOAD, 0, FL_END, 0, 0) != 0)
361 if (!usrp_set_hash (udh, FPGA_HASH_SLOT, hash))
362 fprintf (stderr, "usrp: failed to write fpga hash slot\n");
364 // On the rev1 USRP, the {tx,rx}_{enable,reset} bits are
365 // controlled over the serial bus, and hence aren't observed until
366 // we've got a good fpga bitstream loaded.
368 usrp_set_fpga_reset (udh, 0); // fpga out of master reset
370 // now these commands will work
372 ok &= usrp_set_fpga_tx_enable (udh, 0);
373 ok &= usrp_set_fpga_rx_enable (udh, 0);
375 ok &= usrp_set_fpga_tx_reset (udh, 1); // reset tx and rx paths
376 ok &= usrp_set_fpga_rx_reset (udh, 1);
377 ok &= usrp_set_fpga_tx_reset (udh, 0); // reset tx and rx paths
378 ok &= usrp_set_fpga_rx_reset (udh, 0);
381 fprintf (stderr, "usrp: failed to reset tx and/or rx path\n");
383 // Manually reset all regs except master control to zero.
384 // FIXME may want to remove this when we rework FPGA reset strategy.
385 // In the mean while, this gets us reproducible behavior.
386 for (int i = 0; i < FR_USER_0; i++){
387 if (i == FR_MASTER_CTRL)
389 usrp_write_fpga_reg(udh, i, 0);
392 power_down_9862s (udh); // on the rev1, power these down!
393 usrp_set_led (udh, 1, 0); // led 1 off
398 power_down_9862s (udh); // on the rev1, power these down!
403 // ----------------------------------------------------------------
406 usrp_set_led (libusb_device_handle *udh, int which, bool on)
408 int r = write_cmd (udh, VRQ_SET_LED, on, which, 0, 0);
414 usrp_set_hash (libusb_device_handle *udh, int which,
415 const unsigned char hash[USRP_HASH_SIZE])
419 // we use the Cypress firmware down load command to jam it in.
420 int r = _usb_control_transfer (udh, 0x40, 0xa0, hash_slot_addr[which], 0,
421 (unsigned char *) hash, USRP_HASH_SIZE, 1000);
422 return r == USRP_HASH_SIZE;
426 usrp_get_hash (libusb_device_handle *udh, int which,
427 unsigned char hash[USRP_HASH_SIZE])
431 // we use the Cypress firmware upload command to fetch it.
432 int r = _usb_control_transfer (udh, 0xc0, 0xa0, hash_slot_addr[which], 0,
433 (unsigned char *) hash, USRP_HASH_SIZE, 1000);
434 return r == USRP_HASH_SIZE;
440 usrp_set_switch (libusb_device_handle *udh, int cmd_byte, bool on)
442 return write_cmd (udh, cmd_byte, on, 0, 0, 0) == 0;
446 usrp1_fpga_write (libusb_device_handle *udh,
447 int regno, int value)
449 // on the rev1 usrp, we use the generic spi_write interface
451 unsigned char buf[4];
453 buf[0] = (value >> 24) & 0xff; // MSB first
454 buf[1] = (value >> 16) & 0xff;
455 buf[2] = (value >> 8) & 0xff;
456 buf[3] = (value >> 0) & 0xff;
458 return usrp_spi_write (udh, 0x00 | (regno & 0x7f),
460 SPI_FMT_MSB | SPI_FMT_HDR_1,
465 usrp1_fpga_read (libusb_device_handle *udh,
466 int regno, int *value)
469 unsigned char buf[4];
471 bool ok = usrp_spi_read (udh, 0x80 | (regno & 0x7f),
473 SPI_FMT_MSB | SPI_FMT_HDR_1,
477 *value = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
483 usrp_write_fpga_reg (libusb_device_handle *udh, int reg, int value)
485 switch (usrp_hw_rev (_get_usb_device (udh))){
486 case 0: // not supported ;)
490 return usrp1_fpga_write (udh, reg, value);
495 usrp_read_fpga_reg (libusb_device_handle *udh, int reg, int *value)
497 switch (usrp_hw_rev (_get_usb_device (udh))){
498 case 0: // not supported ;)
502 return usrp1_fpga_read (udh, reg, value);
507 usrp_set_fpga_reset (libusb_device_handle *udh, bool on)
509 return usrp_set_switch (udh, VRQ_FPGA_SET_RESET, on);
513 usrp_set_fpga_tx_enable (libusb_device_handle *udh, bool on)
515 return usrp_set_switch (udh, VRQ_FPGA_SET_TX_ENABLE, on);
519 usrp_set_fpga_rx_enable (libusb_device_handle *udh, bool on)
521 return usrp_set_switch (udh, VRQ_FPGA_SET_RX_ENABLE, on);
525 usrp_set_fpga_tx_reset (libusb_device_handle *udh, bool on)
527 return usrp_set_switch (udh, VRQ_FPGA_SET_TX_RESET, on);
531 usrp_set_fpga_rx_reset (libusb_device_handle *udh, bool on)
533 return usrp_set_switch (udh, VRQ_FPGA_SET_RX_RESET, on);
537 // ----------------------------------------------------------------
538 // conditional load stuff
541 compute_hash (const char *filename, unsigned char hash[USRP_HASH_SIZE])
543 assert (USRP_HASH_SIZE == 16);
544 memset (hash, 0, USRP_HASH_SIZE);
546 FILE *fp = fopen (filename, "rb");
551 int r = md5_stream (fp, hash);
557 static usrp_load_status_t
558 usrp_conditionally_load_something (libusb_device_handle *udh,
559 const char *filename,
562 bool loader (libusb_device_handle *,
564 unsigned char [USRP_HASH_SIZE]))
566 unsigned char file_hash[USRP_HASH_SIZE];
567 unsigned char usrp_hash[USRP_HASH_SIZE];
569 if (access (filename, R_OK) != 0){
574 if (!compute_hash (filename, file_hash))
578 && usrp_get_hash (udh, slot, usrp_hash)
579 && memcmp (file_hash, usrp_hash, USRP_HASH_SIZE) == 0)
580 return ULS_ALREADY_LOADED;
582 bool r = loader (udh, filename, file_hash);
591 usrp_load_firmware (libusb_device_handle *udh,
592 const char *filename,
595 return usrp_conditionally_load_something (udh, filename, force,
597 _usrp_load_firmware);
601 usrp_load_fpga (libusb_device_handle *udh,
602 const char *filename,
605 return usrp_conditionally_load_something (udh, filename, force,
610 static libusb_device_handle *
611 open_nth_cmd_interface (int nth, libusb_context *ctx)
614 libusb_device *udev = usrp_find_device (nth, false, ctx);
616 fprintf (stderr, "usrp: failed to find usrp[%d]\n", nth);
620 libusb_device_handle *udh;
622 udh = usrp_open_cmd_interface (udev);
624 // FIXME this could be because somebody else has it open.
625 // We should delay and retry...
626 fprintf (stderr, "open_nth_cmd_interface: open_cmd_interface failed\n");
634 our_nanosleep (const struct timespec *delay)
636 struct timespec new_delay = *delay;
637 struct timespec remainder;
640 int r = nanosleep (&new_delay, &remainder);
644 new_delay = remainder;
646 perror ("nanosleep");
653 mdelay (int millisecs)
656 ts.tv_sec = millisecs / 1000;
657 ts.tv_nsec = (millisecs - (1000 * ts.tv_sec)) * 1000000;
658 return our_nanosleep (&ts);
663 usrp_load_firmware_nth (int nth, const char *filename, bool force, libusb_context *ctx)
665 libusb_device_handle *udh = open_nth_cmd_interface (nth, ctx);
669 usrp_load_status_t s = usrp_load_firmware (udh, filename, force);
670 usrp_close_interface (udh);
674 case ULS_ALREADY_LOADED: // nothing changed...
675 return ULS_ALREADY_LOADED;
679 // we loaded firmware successfully.
681 // It's highly likely that the board will renumerate (simulate a
682 // disconnect/reconnect sequence), invalidating our current
685 // FIXME. Turn this into a loop that rescans until we refind ourselves
687 struct timespec t; // delay for 1 second
695 case ULS_ERROR: // some kind of problem
701 load_status_msg (usrp_load_status_t s, const char *type, const char *filename)
703 char *e = getenv("USRP_VERBOSE");
704 bool verbose = e != 0;
708 fprintf (stderr, "usrp: failed to load %s %s.\n", type, filename);
711 case ULS_ALREADY_LOADED:
713 fprintf (stderr, "usrp: %s %s already loaded.\n", type, filename);
718 fprintf (stderr, "usrp: %s %s loaded successfully.\n", type, filename);
724 usrp_load_standard_bits (int nth, bool force,
725 const std::string fpga_filename,
726 const std::string firmware_filename,
729 usrp_load_status_t s;
730 const char *filename;
731 const char *proto_filename;
734 // first, figure out what hardware rev we're dealing with
736 libusb_device *udev = usrp_find_device (nth, false, ctx);
738 fprintf (stderr, "usrp: failed to find usrp[%d]\n", nth);
741 hw_rev = usrp_hw_rev (udev);
744 // start by loading the firmware
746 proto_filename = get_proto_filename(firmware_filename, "USRP_FIRMWARE",
747 default_firmware_filename);
748 filename = find_file(proto_filename, hw_rev);
750 fprintf (stderr, "Can't find firmware: %s\n", proto_filename);
753 s = usrp_load_firmware_nth (nth, filename, force, ctx);
754 load_status_msg (s, "firmware", filename);
759 // if we actually loaded firmware, we must reload fpga ...
763 // now move on to the fpga configuration bitstream
765 proto_filename = get_proto_filename(fpga_filename, "USRP_FPGA",
766 default_fpga_filename);
767 filename = find_file (proto_filename, hw_rev);
769 fprintf (stderr, "Can't find fpga bitstream: %s\n", proto_filename);
772 libusb_device_handle *udh = open_nth_cmd_interface (nth, ctx);
776 s = usrp_load_fpga (udh, filename, force);
777 usrp_close_interface (udh);
778 load_status_msg (s, "fpga bitstream", filename);
788 _usrp_get_status (libusb_device_handle *udh, int which, bool *trouble)
790 unsigned char status;
793 if (write_cmd (udh, VRQ_GET_STATUS, 0, which,
794 &status, sizeof (status)) != sizeof (status))
802 usrp_check_rx_overrun (libusb_device_handle *udh, bool *overrun_p)
804 return _usrp_get_status (udh, GS_RX_OVERRUN, overrun_p);
808 usrp_check_tx_underrun (libusb_device_handle *udh, bool *underrun_p)
810 return _usrp_get_status (udh, GS_TX_UNDERRUN, underrun_p);
815 usrp_i2c_write (libusb_device_handle *udh, int i2c_addr,
816 const void *buf, int len)
818 if (len < 1 || len > MAX_EP0_PKTSIZE)
821 return write_cmd (udh, VRQ_I2C_WRITE, i2c_addr, 0,
822 (unsigned char *) buf, len) == len;
827 usrp_i2c_read (libusb_device_handle *udh, int i2c_addr,
830 if (len < 1 || len > MAX_EP0_PKTSIZE)
833 return write_cmd (udh, VRQ_I2C_READ, i2c_addr, 0,
834 (unsigned char *) buf, len) == len;
838 usrp_spi_write (libusb_device_handle *udh,
839 int optional_header, int enables, int format,
840 const void *buf, int len)
842 if (len < 0 || len > MAX_EP0_PKTSIZE)
845 return write_cmd (udh, VRQ_SPI_WRITE,
847 ((enables & 0xff) << 8) | (format & 0xff),
848 (unsigned char *) buf, len) == len;
853 usrp_spi_read (libusb_device_handle *udh,
854 int optional_header, int enables, int format,
857 if (len < 0 || len > MAX_EP0_PKTSIZE)
860 return write_cmd (udh, VRQ_SPI_READ,
862 ((enables & 0xff) << 8) | (format & 0xff),
863 (unsigned char *) buf, len) == len;
867 usrp_9862_write (libusb_device_handle *udh, int which_codec,
868 int regno, int value)
871 fprintf (stderr, "usrp_9862_write which = %d, reg = %2d, val = %3d (0x%02x)\n",
872 which_codec, regno, value, value);
874 unsigned char buf[1];
878 return usrp_spi_write (udh, 0x00 | (regno & 0x3f),
879 which_codec == 0 ? SPI_ENABLE_CODEC_A : SPI_ENABLE_CODEC_B,
880 SPI_FMT_MSB | SPI_FMT_HDR_1,
885 usrp_9862_read (libusb_device_handle *udh, int which_codec,
886 int regno, unsigned char *value)
888 return usrp_spi_read (udh, 0x80 | (regno & 0x3f),
889 which_codec == 0 ? SPI_ENABLE_CODEC_A : SPI_ENABLE_CODEC_B,
890 SPI_FMT_MSB | SPI_FMT_HDR_1,
895 usrp_9862_write_many (libusb_device_handle *udh,
897 const unsigned char *buf,
901 return false; // must be even
906 result &= usrp_9862_write (udh, which_codec, buf[0], buf[1]);
916 usrp_9862_write_many_all (libusb_device_handle *udh,
917 const unsigned char *buf, int len)
919 // FIXME handle 2/2 and 4/4 versions
922 result = usrp_9862_write_many (udh, 0, buf, len);
923 result &= usrp_9862_write_many (udh, 1, buf, len);
928 power_down_9862s (libusb_device_handle *udh)
930 static const unsigned char regs[] = {
931 REG_RX_PWR_DN, 0x01, // everything
932 REG_TX_PWR_DN, 0x0f, // pwr dn digital and analog_both
933 REG_TX_MODULATOR, 0x00 // coarse & fine modulators disabled
936 switch (usrp_hw_rev (_get_usb_device (udh))){
941 usrp_9862_write_many_all (udh, regs, sizeof (regs));
947 static const int EEPROM_PAGESIZE = 16;
950 usrp_eeprom_write (libusb_device_handle *udh, int i2c_addr,
951 int eeprom_offset, const void *buf, int len)
953 unsigned char cmd[2];
954 const unsigned char *p = (unsigned char *) buf;
956 // The simplest thing that could possibly work:
957 // all writes are single byte writes.
959 // We could speed this up using the page write feature,
960 // but we write so infrequently, why bother...
963 cmd[0] = eeprom_offset++;
965 bool r = usrp_i2c_write (udh, i2c_addr, cmd, sizeof (cmd));
966 mdelay (10); // delay 10ms worst case write time
975 usrp_eeprom_read (libusb_device_handle *udh, int i2c_addr,
976 int eeprom_offset, void *buf, int len)
978 unsigned char *p = (unsigned char *) buf;
980 // We setup a random read by first doing a "zero byte write".
981 // Writes carry an address. Reads use an implicit address.
983 unsigned char cmd[1];
984 cmd[0] = eeprom_offset;
985 if (!usrp_i2c_write (udh, i2c_addr, cmd, sizeof (cmd)))
989 int n = std::min (len, MAX_EP0_PKTSIZE);
990 if (!usrp_i2c_read (udh, i2c_addr, p, n))
998 // ----------------------------------------------------------------
1001 slot_to_codec (int slot, int *which_codec)
1017 fprintf (stderr, "usrp_prims:slot_to_codec: invalid slot = %d\n", slot);
1024 tx_slot_p (int slot)
1037 usrp_write_aux_dac (libusb_device_handle *udh, int slot,
1038 int which_dac, int value)
1042 if (!slot_to_codec (slot, &which_codec))
1045 if (!(0 <= which_dac && which_dac < 4)){
1046 fprintf (stderr, "usrp_write_aux_dac: invalid dac = %d\n", which_dac);
1050 value &= 0x0fff; // mask to 12-bits
1052 if (which_dac == 3){
1053 // dac 3 is really 12-bits. Use value as is.
1055 r &= usrp_9862_write (udh, which_codec, 43, (value >> 4)); // most sig
1056 r &= usrp_9862_write (udh, which_codec, 42, (value & 0xf) << 4); // least sig
1060 // dac 0, 1, and 2 are really 8 bits.
1061 value = value >> 4; // shift value appropriately
1062 return usrp_9862_write (udh, which_codec, 36 + which_dac, value);
1068 usrp_read_aux_adc (libusb_device_handle *udh, int slot,
1069 int which_adc, int *value)
1074 if (!slot_to_codec (slot, &which_codec))
1077 if (!(0 <= which_codec && which_codec < 2)){
1078 fprintf (stderr, "usrp_read_aux_adc: invalid adc = %d\n", which_adc);
1082 unsigned char aux_adc_control =
1083 AUX_ADC_CTRL_REFSEL_A // on chip reference
1084 | AUX_ADC_CTRL_REFSEL_B; // on chip reference
1086 int rd_reg = 26; // base address of two regs to read for result
1088 // program the ADC mux bits
1089 if (tx_slot_p (slot))
1090 aux_adc_control |= AUX_ADC_CTRL_SELECT_A2 | AUX_ADC_CTRL_SELECT_B2;
1093 aux_adc_control |= AUX_ADC_CTRL_SELECT_A1 | AUX_ADC_CTRL_SELECT_B1;
1096 // I'm not sure if we can set the mux and issue a start conversion
1097 // in the same cycle, so let's do them one at a time.
1099 usrp_9862_write (udh, which_codec, 34, aux_adc_control);
1102 aux_adc_control |= AUX_ADC_CTRL_START_A;
1105 aux_adc_control |= AUX_ADC_CTRL_START_B;
1108 // start the conversion
1109 usrp_9862_write (udh, which_codec, 34, aux_adc_control);
1111 // read the 10-bit result back
1112 unsigned char v_lo = 0;
1113 unsigned char v_hi = 0;
1114 bool r = usrp_9862_read (udh, which_codec, rd_reg, &v_lo);
1115 r &= usrp_9862_read (udh, which_codec, rd_reg + 1, &v_hi);
1118 *value = ((v_hi << 2) | ((v_lo >> 6) & 0x3)) << 2; // format as 12-bit
1123 // ----------------------------------------------------------------
1125 static int slot_to_i2c_addr (int slot)
1128 case SLOT_TX_A: return I2C_ADDR_TX_A;
1129 case SLOT_RX_A: return I2C_ADDR_RX_A;
1130 case SLOT_TX_B: return I2C_ADDR_TX_B;
1131 case SLOT_RX_B: return I2C_ADDR_RX_B;
1137 set_chksum (unsigned char *buf)
1141 for (i = 0; i < DB_EEPROM_CLEN - 1; i++)
1146 static usrp_dbeeprom_status_t
1147 read_dboard_eeprom (libusb_device_handle *udh,
1148 int slot_id, unsigned char *buf)
1150 int i2c_addr = slot_to_i2c_addr (slot_id);
1152 return UDBE_BAD_SLOT;
1154 if (!usrp_eeprom_read (udh, i2c_addr, 0, buf, DB_EEPROM_CLEN))
1155 return UDBE_NO_EEPROM;
1157 if (buf[DB_EEPROM_MAGIC] != DB_EEPROM_MAGIC_VALUE)
1158 return UDBE_INVALID_EEPROM;
1161 for (unsigned int i = 0; i < DB_EEPROM_CLEN; i++)
1164 if ((sum & 0xff) != 0)
1165 return UDBE_INVALID_EEPROM;
1170 usrp_dbeeprom_status_t
1171 usrp_read_dboard_eeprom (libusb_device_handle *udh,
1172 int slot_id, usrp_dboard_eeprom *eeprom)
1174 unsigned char buf[DB_EEPROM_CLEN];
1176 memset (eeprom, 0, sizeof (*eeprom));
1178 usrp_dbeeprom_status_t s = read_dboard_eeprom (udh, slot_id, buf);
1182 eeprom->id = (buf[DB_EEPROM_ID_MSB] << 8) | buf[DB_EEPROM_ID_LSB];
1183 eeprom->oe = (buf[DB_EEPROM_OE_MSB] << 8) | buf[DB_EEPROM_OE_LSB];
1184 eeprom->offset[0] = (buf[DB_EEPROM_OFFSET_0_MSB] << 8) | buf[DB_EEPROM_OFFSET_0_LSB];
1185 eeprom->offset[1] = (buf[DB_EEPROM_OFFSET_1_MSB] << 8) | buf[DB_EEPROM_OFFSET_1_LSB];
1191 usrp_write_dboard_offsets (libusb_device_handle *udh, int slot_id,
1192 short offset0, short offset1)
1194 unsigned char buf[DB_EEPROM_CLEN];
1196 usrp_dbeeprom_status_t s = read_dboard_eeprom (udh, slot_id, buf);
1200 buf[DB_EEPROM_OFFSET_0_LSB] = (offset0 >> 0) & 0xff;
1201 buf[DB_EEPROM_OFFSET_0_MSB] = (offset0 >> 8) & 0xff;
1202 buf[DB_EEPROM_OFFSET_1_LSB] = (offset1 >> 0) & 0xff;
1203 buf[DB_EEPROM_OFFSET_1_MSB] = (offset1 >> 8) & 0xff;
1206 return usrp_eeprom_write (udh, slot_to_i2c_addr (slot_id),
1207 0, buf, sizeof (buf));
1210 // ----------------------------------------------------------------
1213 usrp_serial_number(libusb_device_handle *udh)
1215 libusb_device_descriptor desc =
1216 _get_usb_device_descriptor (_get_usb_device (udh));
1218 unsigned char iserial = desc.iSerialNumber;
1222 unsigned char buf[1024];
1223 if (_get_usb_string_descriptor (udh, iserial, buf, sizeof(buf)) < 0)