3 * Copyright 2003,2004,2006,2009 Free Software Foundation, Inc.
5 * This file is part of GNU Radio
7 * GNU Radio is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 3, or (at your option)
12 * GNU Radio is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with GNU Radio; see the file COPYING. If not, write to
19 * the Free Software Foundation, Inc., 51 Franklin Street,
20 * Boston, MA 02110-1301, USA.
27 #include "usrp/usrp_prims.h"
28 #include "usrp_commands.h"
30 #include "usrp_i2c_addr.h"
31 #include "fpga_regs_common.h"
32 #include "fpga_regs_standard.h"
39 #include <time.h> // FIXME should check with autoconf (nanosleep)
45 #include <libusb-1.0/libusb.h>
56 using namespace ad9862;
58 static const int FIRMWARE_HASH_SLOT = 0;
59 static const int FPGA_HASH_SLOT = 1;
61 static const int hash_slot_addr[2] = {
62 USRP_HASH_SLOT_0_ADDR,
66 static const char *default_firmware_filename = "std.ihx";
67 static const char *default_fpga_filename = "std_2rxhb_2tx.rbf";
70 #include "std_paths.h"
74 find_file (const char *filename, int hw_rev)
76 const char **sp = std_paths;
77 static char path[1000];
80 s = getenv("USRP_PATH");
82 snprintf (path, sizeof (path), "%s/rev%d/%s", s, hw_rev, filename);
83 if (access (path, R_OK) == 0)
88 snprintf (path, sizeof (path), "%s/rev%d/%s", *sp, hw_rev, filename);
89 if (access (path, R_OK) == 0)
97 get_proto_filename(const std::string user_filename, const char *env_var, const char *def)
99 if (user_filename.length() != 0)
100 return user_filename.c_str();
102 char *s = getenv(env_var);
110 void power_down_9862s (libusb_device_handle *udh);
112 // ----------------------------------------------------------------
115 usrp_usrp0_p (libusb_device *q)
117 return usrp_usrp_p (q) && usrp_hw_rev (q) == 0;
121 usrp_usrp1_p (libusb_device *q)
123 return usrp_usrp_p (q) && usrp_hw_rev (q) == 1;
127 usrp_usrp2_p (libusb_device *q)
129 return usrp_usrp_p (q) && usrp_hw_rev (q) == 2;
134 usrp_unconfigured_usrp_p (libusb_device *q)
136 return usrp_usrp_p (q) && !_usrp_configured_p (q);
140 usrp_configured_usrp_p (libusb_device *q)
142 return usrp_usrp_p (q) && _usrp_configured_p (q);
145 libusb_device_handle *
146 usrp_open_cmd_interface (libusb_device *dev)
148 return usrp_open_interface (dev, USRP_CMD_INTERFACE, USRP_CMD_ALTINTERFACE);
151 libusb_device_handle *
152 usrp_open_rx_interface (libusb_device *dev)
154 return usrp_open_interface (dev, USRP_RX_INTERFACE, USRP_RX_ALTINTERFACE);
157 libusb_device_handle *
158 usrp_open_tx_interface (libusb_device *dev)
160 return usrp_open_interface (dev, USRP_TX_INTERFACE, USRP_TX_ALTINTERFACE);
164 // ----------------------------------------------------------------
165 // whack the CPUCS register using the upload RAM vendor extension
168 reset_cpu (libusb_device_handle *udh, bool reset_p)
173 v = 1; // hold processor in reset
175 v = 0; // release reset
177 return write_internal_ram (udh, &v, 0xE600, 1);
180 // ----------------------------------------------------------------
181 // Load intel format file into cypress FX2 (8051)
184 _usrp_load_firmware (libusb_device_handle *udh, const char *filename,
185 unsigned char hash[USRP_HASH_SIZE])
187 FILE *f = fopen (filename, "ra");
193 if (!reset_cpu (udh, true)) // hold CPU in reset while loading firmware
201 unsigned char data[256];
202 unsigned char checksum, a;
207 fgets(s, sizeof (s), f); /* we should not use more than 263 bytes normally */
209 fprintf(stderr,"%s: invalid line: \"%s\"\n", filename, s);
212 sscanf(s+1, "%02x", &length);
213 sscanf(s+3, "%04x", &addr);
214 sscanf(s+7, "%02x", &type);
218 a=length+(addr &0xff)+(addr>>8)+type;
219 for(i=0;i<length;i++){
220 sscanf (s+9+i*2,"%02x", &b);
225 sscanf (s+9+length*2,"%02x", &b);
227 if (((a+checksum)&0xff)!=0x00){
228 fprintf (stderr, " ** Checksum failed: got 0x%02x versus 0x%02x\n", (-a)&0xff, checksum);
231 if (!write_internal_ram (udh, data, addr, length))
234 else if (type == 0x01){ // EOF
237 else if (type == 0x02){
238 fprintf(stderr, "Extended address: whatever I do with it?\n");
239 fprintf (stderr, "%s: invalid line: \"%s\"\n", filename, s);
244 // we jam the hash value into the FX2 memory before letting
245 // the cpu out of reset. When it comes out of reset it
246 // may renumerate which will invalidate udh.
248 if (!usrp_set_hash (udh, FIRMWARE_HASH_SLOT, hash))
249 fprintf (stderr, "usrp: failed to write firmware hash slot\n");
251 if (!reset_cpu (udh, false)) // take CPU out of reset
262 // ----------------------------------------------------------------
266 _usrp_load_fpga (libusb_device_handle *udh, const char *filename,
267 unsigned char hash[USRP_HASH_SIZE])
271 FILE *fp = fopen (filename, "rb");
277 unsigned char buf[MAX_EP0_PKTSIZE]; // 64 is max size of EP0 packet on FX2
280 usrp_set_led (udh, 1, 1); // led 1 on
283 // reset FPGA (and on rev1 both AD9862's, thus killing clock)
284 usrp_set_fpga_reset (udh, 1); // hold fpga in reset
286 if (write_cmd (udh, VRQ_FPGA_LOAD, 0, FL_BEGIN, 0, 0) != 0)
289 while ((n = fread (buf, 1, sizeof (buf), fp)) > 0){
290 if (write_cmd (udh, VRQ_FPGA_LOAD, 0, FL_XFER, buf, n) != n)
294 if (write_cmd (udh, VRQ_FPGA_LOAD, 0, FL_END, 0, 0) != 0)
299 if (!usrp_set_hash (udh, FPGA_HASH_SLOT, hash))
300 fprintf (stderr, "usrp: failed to write fpga hash slot\n");
302 // On the rev1 USRP, the {tx,rx}_{enable,reset} bits are
303 // controlled over the serial bus, and hence aren't observed until
304 // we've got a good fpga bitstream loaded.
306 usrp_set_fpga_reset (udh, 0); // fpga out of master reset
308 // now these commands will work
310 ok &= usrp_set_fpga_tx_enable (udh, 0);
311 ok &= usrp_set_fpga_rx_enable (udh, 0);
313 ok &= usrp_set_fpga_tx_reset (udh, 1); // reset tx and rx paths
314 ok &= usrp_set_fpga_rx_reset (udh, 1);
315 ok &= usrp_set_fpga_tx_reset (udh, 0); // reset tx and rx paths
316 ok &= usrp_set_fpga_rx_reset (udh, 0);
319 fprintf (stderr, "usrp: failed to reset tx and/or rx path\n");
321 // Manually reset all regs except master control to zero.
322 // FIXME may want to remove this when we rework FPGA reset strategy.
323 // In the mean while, this gets us reproducible behavior.
324 for (int i = 0; i < FR_USER_0; i++){
325 if (i == FR_MASTER_CTRL)
327 usrp_write_fpga_reg(udh, i, 0);
330 power_down_9862s (udh); // on the rev1, power these down!
331 usrp_set_led (udh, 1, 0); // led 1 off
336 power_down_9862s (udh); // on the rev1, power these down!
341 // ----------------------------------------------------------------
344 usrp_set_led (libusb_device_handle *udh, int which, bool on)
346 int r = write_cmd (udh, VRQ_SET_LED, on, which, 0, 0);
353 usrp_set_switch (libusb_device_handle *udh, int cmd_byte, bool on)
355 return write_cmd (udh, cmd_byte, on, 0, 0, 0) == 0;
359 usrp1_fpga_write (libusb_device_handle *udh,
360 int regno, int value)
362 // on the rev1 usrp, we use the generic spi_write interface
364 unsigned char buf[4];
366 buf[0] = (value >> 24) & 0xff; // MSB first
367 buf[1] = (value >> 16) & 0xff;
368 buf[2] = (value >> 8) & 0xff;
369 buf[3] = (value >> 0) & 0xff;
371 return usrp_spi_write (udh, 0x00 | (regno & 0x7f),
373 SPI_FMT_MSB | SPI_FMT_HDR_1,
378 usrp1_fpga_read (libusb_device_handle *udh,
379 int regno, int *value)
382 unsigned char buf[4];
384 bool ok = usrp_spi_read (udh, 0x80 | (regno & 0x7f),
386 SPI_FMT_MSB | SPI_FMT_HDR_1,
390 *value = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
397 usrp_set_fpga_reset (libusb_device_handle *udh, bool on)
399 return usrp_set_switch (udh, VRQ_FPGA_SET_RESET, on);
403 usrp_set_fpga_tx_enable (libusb_device_handle *udh, bool on)
405 return usrp_set_switch (udh, VRQ_FPGA_SET_TX_ENABLE, on);
409 usrp_set_fpga_rx_enable (libusb_device_handle *udh, bool on)
411 return usrp_set_switch (udh, VRQ_FPGA_SET_RX_ENABLE, on);
415 usrp_set_fpga_tx_reset (libusb_device_handle *udh, bool on)
417 return usrp_set_switch (udh, VRQ_FPGA_SET_TX_RESET, on);
421 usrp_set_fpga_rx_reset (libusb_device_handle *udh, bool on)
423 return usrp_set_switch (udh, VRQ_FPGA_SET_RX_RESET, on);
427 // ----------------------------------------------------------------
428 // conditional load stuff
431 compute_hash (const char *filename, unsigned char hash[USRP_HASH_SIZE])
433 assert (USRP_HASH_SIZE == 16);
434 memset (hash, 0, USRP_HASH_SIZE);
436 FILE *fp = fopen (filename, "rb");
441 int r = md5_stream (fp, hash);
447 static usrp_load_status_t
448 usrp_conditionally_load_something (libusb_device_handle *udh,
449 const char *filename,
452 bool loader (libusb_device_handle *,
454 unsigned char [USRP_HASH_SIZE]))
456 unsigned char file_hash[USRP_HASH_SIZE];
457 unsigned char usrp_hash[USRP_HASH_SIZE];
459 if (access (filename, R_OK) != 0){
464 if (!compute_hash (filename, file_hash))
468 && usrp_get_hash (udh, slot, usrp_hash)
469 && memcmp (file_hash, usrp_hash, USRP_HASH_SIZE) == 0)
470 return ULS_ALREADY_LOADED;
472 bool r = loader (udh, filename, file_hash);
481 usrp_load_firmware (libusb_device_handle *udh,
482 const char *filename,
485 return usrp_conditionally_load_something (udh, filename, force,
487 _usrp_load_firmware);
491 usrp_load_fpga (libusb_device_handle *udh,
492 const char *filename,
495 return usrp_conditionally_load_something (udh, filename, force,
501 our_nanosleep (const struct timespec *delay)
503 struct timespec new_delay = *delay;
504 struct timespec remainder;
507 int r = nanosleep (&new_delay, &remainder);
511 new_delay = remainder;
513 perror ("nanosleep");
520 mdelay (int millisecs)
523 ts.tv_sec = millisecs / 1000;
524 ts.tv_nsec = (millisecs - (1000 * ts.tv_sec)) * 1000000;
525 return our_nanosleep (&ts);
529 load_status_msg (usrp_load_status_t s, const char *type, const char *filename)
531 char *e = getenv("USRP_VERBOSE");
532 bool verbose = e != 0;
536 fprintf (stderr, "usrp: failed to load %s %s.\n", type, filename);
539 case ULS_ALREADY_LOADED:
541 fprintf (stderr, "usrp: %s %s already loaded.\n", type, filename);
546 fprintf (stderr, "usrp: %s %s loaded successfully.\n", type, filename);
552 _usrp_get_status (libusb_device_handle *udh, int which, bool *trouble)
554 unsigned char status;
557 if (write_cmd (udh, VRQ_GET_STATUS, 0, which,
558 &status, sizeof (status)) != sizeof (status))
566 usrp_check_rx_overrun (libusb_device_handle *udh, bool *overrun_p)
568 return _usrp_get_status (udh, GS_RX_OVERRUN, overrun_p);
572 usrp_check_tx_underrun (libusb_device_handle *udh, bool *underrun_p)
574 return _usrp_get_status (udh, GS_TX_UNDERRUN, underrun_p);
579 usrp_i2c_write (libusb_device_handle *udh, int i2c_addr,
580 const void *buf, int len)
582 if (len < 1 || len > MAX_EP0_PKTSIZE)
585 return write_cmd (udh, VRQ_I2C_WRITE, i2c_addr, 0,
586 (unsigned char *) buf, len) == len;
591 usrp_i2c_read (libusb_device_handle *udh, int i2c_addr,
594 if (len < 1 || len > MAX_EP0_PKTSIZE)
597 return write_cmd (udh, VRQ_I2C_READ, i2c_addr, 0,
598 (unsigned char *) buf, len) == len;
602 usrp_spi_write (libusb_device_handle *udh,
603 int optional_header, int enables, int format,
604 const void *buf, int len)
606 if (len < 0 || len > MAX_EP0_PKTSIZE)
609 return write_cmd (udh, VRQ_SPI_WRITE,
611 ((enables & 0xff) << 8) | (format & 0xff),
612 (unsigned char *) buf, len) == len;
617 usrp_spi_read (libusb_device_handle *udh,
618 int optional_header, int enables, int format,
621 if (len < 0 || len > MAX_EP0_PKTSIZE)
624 return write_cmd (udh, VRQ_SPI_READ,
626 ((enables & 0xff) << 8) | (format & 0xff),
627 (unsigned char *) buf, len) == len;
631 usrp_9862_write (libusb_device_handle *udh, int which_codec,
632 int regno, int value)
635 fprintf (stderr, "usrp_9862_write which = %d, reg = %2d, val = %3d (0x%02x)\n",
636 which_codec, regno, value, value);
638 unsigned char buf[1];
642 return usrp_spi_write (udh, 0x00 | (regno & 0x3f),
643 which_codec == 0 ? SPI_ENABLE_CODEC_A : SPI_ENABLE_CODEC_B,
644 SPI_FMT_MSB | SPI_FMT_HDR_1,
649 usrp_9862_read (libusb_device_handle *udh, int which_codec,
650 int regno, unsigned char *value)
652 return usrp_spi_read (udh, 0x80 | (regno & 0x3f),
653 which_codec == 0 ? SPI_ENABLE_CODEC_A : SPI_ENABLE_CODEC_B,
654 SPI_FMT_MSB | SPI_FMT_HDR_1,
659 usrp_9862_write_many (libusb_device_handle *udh,
661 const unsigned char *buf,
665 return false; // must be even
670 result &= usrp_9862_write (udh, which_codec, buf[0], buf[1]);
680 usrp_9862_write_many_all (libusb_device_handle *udh,
681 const unsigned char *buf, int len)
683 // FIXME handle 2/2 and 4/4 versions
686 result = usrp_9862_write_many (udh, 0, buf, len);
687 result &= usrp_9862_write_many (udh, 1, buf, len);
692 static const int EEPROM_PAGESIZE = 16;
695 usrp_eeprom_write (libusb_device_handle *udh, int i2c_addr,
696 int eeprom_offset, const void *buf, int len)
698 unsigned char cmd[2];
699 const unsigned char *p = (unsigned char *) buf;
701 // The simplest thing that could possibly work:
702 // all writes are single byte writes.
704 // We could speed this up using the page write feature,
705 // but we write so infrequently, why bother...
708 cmd[0] = eeprom_offset++;
710 bool r = usrp_i2c_write (udh, i2c_addr, cmd, sizeof (cmd));
711 mdelay (10); // delay 10ms worst case write time
720 usrp_eeprom_read (libusb_device_handle *udh, int i2c_addr,
721 int eeprom_offset, void *buf, int len)
723 unsigned char *p = (unsigned char *) buf;
725 // We setup a random read by first doing a "zero byte write".
726 // Writes carry an address. Reads use an implicit address.
728 unsigned char cmd[1];
729 cmd[0] = eeprom_offset;
730 if (!usrp_i2c_write (udh, i2c_addr, cmd, sizeof (cmd)))
734 int n = std::min (len, MAX_EP0_PKTSIZE);
735 if (!usrp_i2c_read (udh, i2c_addr, p, n))
743 // ----------------------------------------------------------------
746 slot_to_codec (int slot, int *which_codec)
762 fprintf (stderr, "usrp_prims:slot_to_codec: invalid slot = %d\n", slot);
782 usrp_write_aux_dac (libusb_device_handle *udh, int slot,
783 int which_dac, int value)
787 if (!slot_to_codec (slot, &which_codec))
790 if (!(0 <= which_dac && which_dac < 4)){
791 fprintf (stderr, "usrp_write_aux_dac: invalid dac = %d\n", which_dac);
795 value &= 0x0fff; // mask to 12-bits
798 // dac 3 is really 12-bits. Use value as is.
800 r &= usrp_9862_write (udh, which_codec, 43, (value >> 4)); // most sig
801 r &= usrp_9862_write (udh, which_codec, 42, (value & 0xf) << 4); // least sig
805 // dac 0, 1, and 2 are really 8 bits.
806 value = value >> 4; // shift value appropriately
807 return usrp_9862_write (udh, which_codec, 36 + which_dac, value);
813 usrp_read_aux_adc (libusb_device_handle *udh, int slot,
814 int which_adc, int *value)
819 if (!slot_to_codec (slot, &which_codec))
822 if (!(0 <= which_codec && which_codec < 2)){
823 fprintf (stderr, "usrp_read_aux_adc: invalid adc = %d\n", which_adc);
827 unsigned char aux_adc_control =
828 AUX_ADC_CTRL_REFSEL_A // on chip reference
829 | AUX_ADC_CTRL_REFSEL_B; // on chip reference
831 int rd_reg = 26; // base address of two regs to read for result
833 // program the ADC mux bits
834 if (tx_slot_p (slot))
835 aux_adc_control |= AUX_ADC_CTRL_SELECT_A2 | AUX_ADC_CTRL_SELECT_B2;
838 aux_adc_control |= AUX_ADC_CTRL_SELECT_A1 | AUX_ADC_CTRL_SELECT_B1;
841 // I'm not sure if we can set the mux and issue a start conversion
842 // in the same cycle, so let's do them one at a time.
844 usrp_9862_write (udh, which_codec, 34, aux_adc_control);
847 aux_adc_control |= AUX_ADC_CTRL_START_A;
850 aux_adc_control |= AUX_ADC_CTRL_START_B;
853 // start the conversion
854 usrp_9862_write (udh, which_codec, 34, aux_adc_control);
856 // read the 10-bit result back
857 unsigned char v_lo = 0;
858 unsigned char v_hi = 0;
859 bool r = usrp_9862_read (udh, which_codec, rd_reg, &v_lo);
860 r &= usrp_9862_read (udh, which_codec, rd_reg + 1, &v_hi);
863 *value = ((v_hi << 2) | ((v_lo >> 6) & 0x3)) << 2; // format as 12-bit
868 // ----------------------------------------------------------------
870 static int slot_to_i2c_addr (int slot)
873 case SLOT_TX_A: return I2C_ADDR_TX_A;
874 case SLOT_RX_A: return I2C_ADDR_RX_A;
875 case SLOT_TX_B: return I2C_ADDR_TX_B;
876 case SLOT_RX_B: return I2C_ADDR_RX_B;
882 set_chksum (unsigned char *buf)
886 for (i = 0; i < DB_EEPROM_CLEN - 1; i++)
891 static usrp_dbeeprom_status_t
892 read_dboard_eeprom (libusb_device_handle *udh,
893 int slot_id, unsigned char *buf)
895 int i2c_addr = slot_to_i2c_addr (slot_id);
897 return UDBE_BAD_SLOT;
899 if (!usrp_eeprom_read (udh, i2c_addr, 0, buf, DB_EEPROM_CLEN))
900 return UDBE_NO_EEPROM;
902 if (buf[DB_EEPROM_MAGIC] != DB_EEPROM_MAGIC_VALUE)
903 return UDBE_INVALID_EEPROM;
906 for (unsigned int i = 0; i < DB_EEPROM_CLEN; i++)
909 if ((sum & 0xff) != 0)
910 return UDBE_INVALID_EEPROM;
915 usrp_dbeeprom_status_t
916 usrp_read_dboard_eeprom (libusb_device_handle *udh,
917 int slot_id, usrp_dboard_eeprom *eeprom)
919 unsigned char buf[DB_EEPROM_CLEN];
921 memset (eeprom, 0, sizeof (*eeprom));
923 usrp_dbeeprom_status_t s = read_dboard_eeprom (udh, slot_id, buf);
927 eeprom->id = (buf[DB_EEPROM_ID_MSB] << 8) | buf[DB_EEPROM_ID_LSB];
928 eeprom->oe = (buf[DB_EEPROM_OE_MSB] << 8) | buf[DB_EEPROM_OE_LSB];
929 eeprom->offset[0] = (buf[DB_EEPROM_OFFSET_0_MSB] << 8) | buf[DB_EEPROM_OFFSET_0_LSB];
930 eeprom->offset[1] = (buf[DB_EEPROM_OFFSET_1_MSB] << 8) | buf[DB_EEPROM_OFFSET_1_LSB];
936 usrp_write_dboard_offsets (libusb_device_handle *udh, int slot_id,
937 short offset0, short offset1)
939 unsigned char buf[DB_EEPROM_CLEN];
941 usrp_dbeeprom_status_t s = read_dboard_eeprom (udh, slot_id, buf);
945 buf[DB_EEPROM_OFFSET_0_LSB] = (offset0 >> 0) & 0xff;
946 buf[DB_EEPROM_OFFSET_0_MSB] = (offset0 >> 8) & 0xff;
947 buf[DB_EEPROM_OFFSET_1_LSB] = (offset1 >> 0) & 0xff;
948 buf[DB_EEPROM_OFFSET_1_MSB] = (offset1 >> 8) & 0xff;
951 return usrp_eeprom_write (udh, slot_to_i2c_addr (slot_id),
952 0, buf, sizeof (buf));