3 * Copyright 2003,2004,2008,2009 Free Software Foundation, Inc.
5 * This file is part of GNU Radio
7 * GNU Radio is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 3, or (at your option)
12 * GNU Radio is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with GNU Radio; see the file COPYING. If not, write to
19 * the Free Software Foundation, Inc., 51 Franklin Street,
20 * Boston, MA 02110-1301, USA.
27 #include "usrp/usrp_basic.h"
28 #include "usrp/usrp_prims.h"
29 #include "usrp_interfaces.h"
30 #include "fpga_regs_common.h"
31 #include "fpga_regs_standard.h"
33 #include "db_boards.h"
41 using namespace ad9862;
43 #define NELEM(x) (sizeof (x) / sizeof (x[0]))
45 // These set the buffer size used for each end point using the fast
46 // usb interface. The kernel ends up locking down this much memory.
48 static const int FUSB_BUFFER_SIZE = fusb_sysconfig::default_buffer_size();
49 static const int FUSB_BLOCK_SIZE = fusb_sysconfig::max_block_size();
50 static const int FUSB_NBLOCKS = FUSB_BUFFER_SIZE / FUSB_BLOCK_SIZE;
53 static const double POLLING_INTERVAL = 0.1; // seconds
55 ////////////////////////////////////////////////////////////////
57 static libusb_device_handle *
58 open_rx_interface (libusb_device *dev)
60 libusb_device_handle *udh = usrp_open_rx_interface (dev);
62 fprintf (stderr, "usrp_basic_rx: can't open rx interface\n");
67 static libusb_device_handle *
68 open_tx_interface (libusb_device *dev)
70 libusb_device_handle *udh = usrp_open_tx_interface (dev);
72 fprintf (stderr, "usrp_basic_tx: can't open tx interface\n");
78 //////////////////////////////////////////////////////////////////
82 ////////////////////////////////////////////////////////////////
89 // These settings give us:
90 // CLKOUT1 = CLKIN = 64 MHz
91 // CLKOUT2 = CLKIN = 64 MHz
92 // ADC is clocked at 64 MHz
93 // DAC is clocked at 128 MHz
95 static unsigned char common_regs[] = {
97 REG_DLL, (DLL_DISABLE_INTERNAL_XTAL_OSC
100 REG_CLKOUT, CLKOUT2_EQ_DLL_OVER_2,
101 REG_AUX_ADC_CLK, AUX_ADC_CLK_CLK_OVER_4
105 usrp_basic::shutdown_daughterboards()
107 // nuke d'boards before we close down USB in ~usrp_basic
108 // shutdown() will do any board shutdown while the USRP can still
110 for(size_t i = 0; i < d_db.size(); i++)
111 for(size_t j = 0; j < d_db[i].size(); j++)
112 d_db[i][j]->shutdown();
116 usrp_basic::init_db(usrp_basic_sptr u)
119 throw std::invalid_argument("u is not this");
121 d_db[0] = instantiate_dbs(d_dbid[0], u, 0);
122 d_db[1] = instantiate_dbs(d_dbid[1], u, 1);
125 std::vector<db_base_sptr>
126 usrp_basic::db(int which_side)
128 which_side &= 0x1; // clamp it to avoid any reporting any errors
129 return d_db[which_side];
133 usrp_basic::is_valid(const usrp_subdev_spec &ss)
135 if (ss.side < 0 || ss.side > 1)
138 if (ss.subdev < 0 || ss.subdev >= d_db[ss.side].size())
145 usrp_basic::selected_subdev(const usrp_subdev_spec &ss)
148 throw std::invalid_argument("invalid subdev_spec");
150 return d_db[ss.side][ss.subdev];
166 usrp_basic::set_usb_data_rate (int usb_data_rate)
168 d_usb_data_rate = usb_data_rate;
169 d_bytes_per_poll = (int) (usb_data_rate * POLLING_INTERVAL);
173 usrp_basic::_write_aux_dac (int slot, int which_dac, int value)
175 return usrp_write_aux_dac (d_udh, slot, which_dac, value);
179 usrp_basic::_read_aux_adc (int slot, int which_adc, int *value)
181 return usrp_read_aux_adc (d_udh, slot, which_adc, value);
185 usrp_basic::_read_aux_adc (int slot, int which_adc)
188 if (!_read_aux_adc (slot, which_adc, &value))
195 usrp_basic::write_eeprom (int i2c_addr, int eeprom_offset, const std::string buf)
197 return usrp_eeprom_write (d_udh, i2c_addr, eeprom_offset, buf.data (), buf.size ());
201 usrp_basic::read_eeprom (int i2c_addr, int eeprom_offset, int len)
208 if (!usrp_eeprom_read (d_udh, i2c_addr, eeprom_offset, buf, len))
211 return std::string (buf, len);
215 usrp_basic::write_i2c (int i2c_addr, const std::string buf)
217 return usrp_i2c_write (d_udh, i2c_addr, buf.data (), buf.size ());
221 usrp_basic::read_i2c (int i2c_addr, int len)
228 if (!usrp_i2c_read (d_udh, i2c_addr, buf, len))
231 return std::string (buf, len);
235 usrp_basic::serial_number()
237 return usrp_serial_number(d_udh);
240 // ----------------------------------------------------------------
243 usrp_basic::set_adc_offset (int which_adc, int offset)
245 if (which_adc < 0 || which_adc > 3)
248 return _write_fpga_reg (FR_ADC_OFFSET_0 + which_adc, offset);
252 usrp_basic::set_dac_offset (int which_dac, int offset, int offset_pin)
254 if (which_dac < 0 || which_dac > 3)
257 int which_codec = which_dac >> 1;
258 int tx_a = (which_dac & 0x1) == 0;
259 int lo = ((offset & 0x3) << 6) | (offset_pin & 0x1);
260 int hi = (offset >> 2);
264 ok = _write_9862 (which_codec, REG_TX_A_OFFSET_LO, lo);
265 ok &= _write_9862 (which_codec, REG_TX_A_OFFSET_HI, hi);
268 ok = _write_9862 (which_codec, REG_TX_B_OFFSET_LO, lo);
269 ok &= _write_9862 (which_codec, REG_TX_B_OFFSET_HI, hi);
275 usrp_basic::set_adc_buffer_bypass (int which_adc, bool bypass)
277 if (which_adc < 0 || which_adc > 3)
280 int codec = which_adc >> 1;
281 int reg = (which_adc & 1) == 0 ? REG_RX_A : REG_RX_B;
283 unsigned char cur_rx;
284 unsigned char cur_pwr_dn;
286 // If the input buffer is bypassed, we need to power it down too.
288 bool ok = _read_9862 (codec, reg, &cur_rx);
289 ok &= _read_9862 (codec, REG_RX_PWR_DN, &cur_pwr_dn);
294 cur_rx |= RX_X_BYPASS_INPUT_BUFFER;
295 cur_pwr_dn |= ((which_adc & 1) == 0) ? RX_PWR_DN_BUF_A : RX_PWR_DN_BUF_B;
298 cur_rx &= ~RX_X_BYPASS_INPUT_BUFFER;
299 cur_pwr_dn &= ~(((which_adc & 1) == 0) ? RX_PWR_DN_BUF_A : RX_PWR_DN_BUF_B);
302 ok &= _write_9862 (codec, reg, cur_rx);
303 ok &= _write_9862 (codec, REG_RX_PWR_DN, cur_pwr_dn);
308 usrp_basic::set_dc_offset_cl_enable(int bits, int mask)
310 return _write_fpga_reg(FR_DC_OFFSET_CL_EN,
311 (d_fpga_shadows[FR_DC_OFFSET_CL_EN] & ~mask) | (bits & mask));
314 // ----------------------------------------------------------------
317 usrp_basic::_write_fpga_reg (int regno, int value)
320 fprintf (stdout, "_write_fpga_reg(%3d, 0x%08x)\n", regno, value);
324 if (regno >= 0 && regno < MAX_REGS)
325 d_fpga_shadows[regno] = value;
327 return usrp_write_fpga_reg (d_udh, regno, value);
331 usrp_basic::_write_fpga_reg_masked (int regno, int value, int mask)
333 //Only use this for registers who actually use a mask in the verilog firmware, like FR_RX_MASTER_SLAVE
334 //value is a 16 bits value and mask is a 16 bits mask
336 fprintf (stdout, "_write_fpga_reg_masked(%3d, 0x%04x,0x%04x)\n", regno, value, mask);
340 if (regno >= 0 && regno < MAX_REGS)
341 d_fpga_shadows[regno] = value;
343 return usrp_write_fpga_reg (d_udh, regno, (value & 0xffff) | ((mask & 0xffff)<<16));
348 usrp_basic::_read_fpga_reg (int regno, int *value)
350 return usrp_read_fpga_reg (d_udh, regno, value);
354 usrp_basic::_read_fpga_reg (int regno)
357 if (!_read_fpga_reg (regno, &value))
363 usrp_basic::_write_9862 (int which_codec, int regno, unsigned char value)
366 // FIXME really want to enable logging in usrp_prims:usrp_9862_write
367 fprintf(stdout, "_write_9862(codec = %d, regno = %2d, val = 0x%02x)\n", which_codec, regno, value);
371 return usrp_9862_write (d_udh, which_codec, regno, value);
376 usrp_basic::_read_9862 (int which_codec, int regno, unsigned char *value) const
378 return usrp_9862_read (d_udh, which_codec, regno, value);
382 usrp_basic::_read_9862 (int which_codec, int regno) const
385 if (!_read_9862 (which_codec, regno, &value))
391 usrp_basic::_write_spi (int optional_header, int enables, int format, std::string buf)
393 return usrp_spi_write (d_udh, optional_header, enables, format,
394 buf.data(), buf.size());
398 usrp_basic::_read_spi (int optional_header, int enables, int format, int len)
405 if (!usrp_spi_read (d_udh, optional_header, enables, format, buf, len))
408 return std::string (buf, len);
413 usrp_basic::_set_led (int which_led, bool on)
415 return usrp_set_led (d_udh, which_led, on);
419 usrp_basic::write_atr_tx_delay(int value)
421 return _write_fpga_reg(FR_ATR_TX_DELAY, value);
425 usrp_basic::write_atr_rx_delay(int value)
427 return _write_fpga_reg(FR_ATR_RX_DELAY, value);
431 * ----------------------------------------------------------------
432 * Routines to access and control daughterboard specific i/o
433 * ----------------------------------------------------------------
436 slot_id_to_oe_reg (int slot_id)
438 static int reg[4] = { FR_OE_0, FR_OE_1, FR_OE_2, FR_OE_3 };
439 assert (0 <= slot_id && slot_id < 4);
444 slot_id_to_io_reg (int slot_id)
446 static int reg[4] = { FR_IO_0, FR_IO_1, FR_IO_2, FR_IO_3 };
447 assert (0 <= slot_id && slot_id < 4);
452 slot_id_to_refclk_reg(int slot_id)
454 static int reg[4] = { FR_TX_A_REFCLK, FR_RX_A_REFCLK, FR_TX_B_REFCLK, FR_RX_B_REFCLK };
455 assert (0 <= slot_id && slot_id < 4);
460 slot_id_to_atr_mask_reg(int slot_id)
462 static int reg[4] = { FR_ATR_MASK_0, FR_ATR_MASK_1, FR_ATR_MASK_2, FR_ATR_MASK_3 };
463 assert (0 <= slot_id && slot_id < 4);
468 slot_id_to_atr_txval_reg(int slot_id)
470 static int reg[4] = { FR_ATR_TXVAL_0, FR_ATR_TXVAL_1, FR_ATR_TXVAL_2, FR_ATR_TXVAL_3 };
471 assert (0 <= slot_id && slot_id < 4);
476 slot_id_to_atr_rxval_reg(int slot_id)
478 static int reg[4] = { FR_ATR_RXVAL_0, FR_ATR_RXVAL_1, FR_ATR_RXVAL_2, FR_ATR_RXVAL_3 };
479 assert (0 <= slot_id && slot_id < 4);
484 to_slot(txrx_t txrx, int which_side)
490 return ((which_side & 0x1) << 1) | ((txrx & 0x1) == C_RX);
494 usrp_basic::common_set_pga(txrx_t txrx, int which_amp, double gain)
496 if (which_amp < 0 || which_amp > 3)
499 gain = std::min(common_pga_max(txrx),
500 std::max(common_pga_min(txrx), gain));
502 int codec = which_amp >> 1;
503 int int_gain = (int) rint((gain - common_pga_min(txrx)) / common_pga_db_per_step(txrx));
505 if (txrx == C_TX){ // 0 and 1 are same, as are 2 and 3
506 return _write_9862(codec, REG_TX_PGA, int_gain);
509 int reg = (which_amp & 1) == 0 ? REG_RX_A : REG_RX_B;
511 // read current value to get input buffer bypass flag.
512 unsigned char cur_rx;
513 if (!_read_9862(codec, reg, &cur_rx))
516 cur_rx = (cur_rx & RX_X_BYPASS_INPUT_BUFFER) | (int_gain & 0x7f);
517 return _write_9862(codec, reg, cur_rx);
522 usrp_basic::common_pga(txrx_t txrx, int which_amp) const
524 if (which_amp < 0 || which_amp > 3)
528 int codec = which_amp >> 1;
530 bool ok = _read_9862 (codec, REG_TX_PGA, &v);
534 return (pga_db_per_step() * v) + pga_min();
537 int codec = which_amp >> 1;
538 int reg = (which_amp & 1) == 0 ? REG_RX_A : REG_RX_B;
540 bool ok = _read_9862 (codec, reg, &v);
544 return (pga_db_per_step() * (v & 0x1f)) + pga_min();
549 usrp_basic::common_pga_min(txrx_t txrx) const
558 usrp_basic::common_pga_max(txrx_t txrx) const
567 usrp_basic::common_pga_db_per_step(txrx_t txrx) const
576 usrp_basic::_common_write_oe(txrx_t txrx, int which_side, int value, int mask)
578 if (! (0 <= which_side && which_side <= 1))
581 return _write_fpga_reg(slot_id_to_oe_reg(to_slot(txrx, which_side)),
582 (mask << 16) | (value & 0xffff));
586 usrp_basic::common_write_io(txrx_t txrx, int which_side, int value, int mask)
588 if (! (0 <= which_side && which_side <= 1))
591 return _write_fpga_reg(slot_id_to_io_reg(to_slot(txrx, which_side)),
592 (mask << 16) | (value & 0xffff));
596 usrp_basic::common_read_io(txrx_t txrx, int which_side, int *value)
598 if (! (0 <= which_side && which_side <= 1))
602 int reg = which_side + 1; // FIXME, *very* magic number (fix in serial_io.v)
603 bool ok = _read_fpga_reg(reg, &t);
608 *value = t & 0xffff; // FIXME, more magic
612 *value = (t >> 16) & 0xffff; // FIXME, more magic
618 usrp_basic::common_read_io(txrx_t txrx, int which_side)
621 if (!common_read_io(txrx, which_side, &value))
627 usrp_basic::common_write_refclk(txrx_t txrx, int which_side, int value)
629 if (! (0 <= which_side && which_side <= 1))
632 return _write_fpga_reg(slot_id_to_refclk_reg(to_slot(txrx, which_side)),
637 usrp_basic::common_write_atr_mask(txrx_t txrx, int which_side, int value)
639 if (! (0 <= which_side && which_side <= 1))
642 return _write_fpga_reg(slot_id_to_atr_mask_reg(to_slot(txrx, which_side)),
647 usrp_basic::common_write_atr_txval(txrx_t txrx, int which_side, int value)
649 if (! (0 <= which_side && which_side <= 1))
652 return _write_fpga_reg(slot_id_to_atr_txval_reg(to_slot(txrx, which_side)),
657 usrp_basic::common_write_atr_rxval(txrx_t txrx, int which_side, int value)
659 if (! (0 <= which_side && which_side <= 1))
662 return _write_fpga_reg(slot_id_to_atr_rxval_reg(to_slot(txrx, which_side)),
667 usrp_basic::common_write_aux_dac(txrx_t txrx, int which_side, int which_dac, int value)
669 return _write_aux_dac(to_slot(txrx, which_side), which_dac, value);
673 usrp_basic::common_read_aux_adc(txrx_t txrx, int which_side, int which_adc, int *value)
675 return _read_aux_adc(to_slot(txrx, which_side), which_adc, value);
679 usrp_basic::common_read_aux_adc(txrx_t txrx, int which_side, int which_adc)
681 return _read_aux_adc(to_slot(txrx, which_side), which_adc);
685 ////////////////////////////////////////////////////////////////
689 ////////////////////////////////////////////////////////////////
691 static unsigned char rx_init_regs[] = {
693 REG_RX_A, 0, // minimum gain = 0x00 (max gain = 0x14)
694 REG_RX_B, 0, // minimum gain = 0x00 (max gain = 0x14)
695 REG_RX_MISC, (RX_MISC_HS_DUTY_CYCLE | RX_MISC_CLK_DUTY),
696 REG_RX_IF, (RX_IF_USE_CLKOUT1
698 REG_RX_DIGITAL, (RX_DIGITAL_2_CHAN)
702 usrp_basic_rx::usrp_basic_rx (int which_board, int fusb_block_size, int fusb_nblocks,
703 const std::string fpga_filename,
704 const std::string firmware_filename
706 : usrp_basic (which_board, open_rx_interface, fpga_filename, firmware_filename),
707 d_devhandle (0), d_ephandle (0),
708 d_bytes_seen (0), d_first_read (true),
711 // initialize rx specific registers
713 if (!usrp_9862_write_many_all (d_udh, rx_init_regs, sizeof (rx_init_regs))){
714 fprintf (stderr, "usrp_basic_rx: failed to init AD9862 RX regs\n");
715 throw std::runtime_error ("usrp_basic_rx/init_9862");
719 // FIXME power down 2nd codec rx path
720 usrp_9862_write (d_udh, 1, REG_RX_PWR_DN, 0x1); // power down everything
723 // Reset the rx path and leave it disabled.
724 set_rx_enable (false);
725 usrp_set_fpga_rx_reset (d_udh, true);
726 usrp_set_fpga_rx_reset (d_udh, false);
728 set_fpga_rx_sample_rate_divisor (2); // usually correct
730 set_dc_offset_cl_enable(0xf, 0xf); // enable DC offset removal control loops
732 probe_rx_slots (false);
734 //d_db[0] = instantiate_dbs(d_dbid[0], this, 0);
735 //d_db[1] = instantiate_dbs(d_dbid[1], this, 1);
737 // check fusb buffering parameters
739 if (fusb_block_size < 0 || fusb_block_size > FUSB_BLOCK_SIZE)
740 throw std::out_of_range ("usrp_basic_rx: invalid fusb_block_size");
742 if (fusb_nblocks < 0)
743 throw std::out_of_range ("usrp_basic_rx: invalid fusb_nblocks");
745 if (fusb_block_size == 0)
746 fusb_block_size = fusb_sysconfig::default_block_size();
748 if (fusb_nblocks == 0)
749 fusb_nblocks = std::max (1, FUSB_BUFFER_SIZE / fusb_block_size);
751 d_devhandle = fusb_sysconfig::make_devhandle (d_udh, d_ctx);
752 d_ephandle = d_devhandle->make_ephandle (USRP_RX_ENDPOINT, true,
753 fusb_block_size, fusb_nblocks);
755 write_atr_mask(0, 0); // zero Rx A Auto Transmit/Receive regs
756 write_atr_txval(0, 0);
757 write_atr_rxval(0, 0);
758 write_atr_mask(1, 0); // zero Rx B Auto Transmit/Receive regs
759 write_atr_txval(1, 0);
760 write_atr_rxval(1, 0);
763 static unsigned char rx_fini_regs[] = {
764 REG_RX_PWR_DN, 0x1 // power down everything
767 usrp_basic_rx::~usrp_basic_rx ()
769 if (!set_rx_enable (false)){
770 fprintf (stderr, "usrp_basic_rx: set_fpga_rx_enable failed\n");
777 if (!usrp_9862_write_many_all (d_udh, rx_fini_regs, sizeof (rx_fini_regs))){
778 fprintf (stderr, "usrp_basic_rx: failed to fini AD9862 RX regs\n");
781 shutdown_daughterboards();
786 usrp_basic_rx::start ()
788 if (!usrp_basic::start ()) // invoke parent's method
791 // fire off reads before asserting rx_enable
793 if (!d_ephandle->start ()){
794 fprintf (stderr, "usrp_basic_rx: failed to start end point streaming");
798 if (!set_rx_enable (true)){
799 fprintf (stderr, "usrp_basic_rx: set_rx_enable failed\n");
807 usrp_basic_rx::stop ()
809 bool ok = usrp_basic::stop();
811 if (!set_rx_enable(false)){
812 fprintf (stderr, "usrp_basic_rx: set_rx_enable(false) failed\n");
816 if (!d_ephandle->stop()){
817 fprintf (stderr, "usrp_basic_rx: failed to stop end point streaming");
825 usrp_basic_rx::make (int which_board, int fusb_block_size, int fusb_nblocks,
826 const std::string fpga_filename,
827 const std::string firmware_filename)
829 usrp_basic_rx *u = 0;
832 u = new usrp_basic_rx (which_board, fusb_block_size, fusb_nblocks,
833 fpga_filename, firmware_filename);
845 usrp_basic_rx::set_fpga_rx_sample_rate_divisor (unsigned int div)
847 return _write_fpga_reg (FR_RX_SAMPLE_RATE_DIV, div - 1);
852 * \brief read data from the D/A's via the FPGA.
853 * \p len must be a multiple of 512 bytes.
855 * \returns the number of bytes read, or -1 on error.
857 * If overrun is non-NULL it will be set true iff an RX overrun is detected.
860 usrp_basic_rx::read (void *buf, int len, bool *overrun)
867 if (len < 0 || (len % 512) != 0){
868 fprintf (stderr, "usrp_basic_rx::read: invalid length = %d\n", len);
872 r = d_ephandle->read (buf, len);
877 * In many cases, the FPGA reports an rx overrun right after we
878 * enable the Rx path. If this is our first read, check for the
879 * overrun to clear the condition, then ignore the result.
881 if (0 && d_first_read){ // FIXME
882 d_first_read = false;
884 usrp_check_rx_overrun (d_udh, &bogus_overrun);
887 if (overrun != 0 && d_bytes_seen >= d_bytes_per_poll){
889 if (!usrp_check_rx_overrun (d_udh, overrun)){
890 fprintf (stderr, "usrp_basic_rx: usrp_check_rx_overrun failed\n");
898 usrp_basic_rx::set_rx_enable (bool on)
901 return usrp_set_fpga_rx_enable (d_udh, on);
904 // conditional disable, return prev state
906 usrp_basic_rx::disable_rx ()
908 bool enabled = rx_enable ();
910 set_rx_enable (false);
916 usrp_basic_rx::restore_rx (bool on)
918 if (on != rx_enable ())
923 usrp_basic_rx::probe_rx_slots (bool verbose)
925 struct usrp_dboard_eeprom eeprom;
926 static int slot_id_map[2] = { SLOT_RX_A, SLOT_RX_B };
927 static const char *slot_name[2] = { "RX d'board A", "RX d'board B" };
929 for (int i = 0; i < 2; i++){
930 int slot_id = slot_id_map [i];
932 usrp_dbeeprom_status_t s = usrp_read_dboard_eeprom (d_udh, slot_id, &eeprom);
936 d_dbid[i] = eeprom.id;
937 msg = usrp_dbid_to_string (eeprom.id).c_str ();
938 set_adc_offset (2*i+0, eeprom.offset[0]);
939 set_adc_offset (2*i+1, eeprom.offset[1]);
940 _write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | eeprom.oe);
941 _write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
947 _write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | 0x0000);
948 _write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
951 case UDBE_INVALID_EEPROM:
953 msg = "Invalid EEPROM contents";
954 _write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | 0x0000);
955 _write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
965 fprintf (stderr, "%s: %s\n", slot_name[i], msg);
971 usrp_basic_rx::set_pga (int which_amp, double gain)
973 return common_set_pga(C_RX, which_amp, gain);
977 usrp_basic_rx::pga(int which_amp) const
979 return common_pga(C_RX, which_amp);
983 usrp_basic_rx::pga_min() const
985 return common_pga_min(C_RX);
989 usrp_basic_rx::pga_max() const
991 return common_pga_max(C_RX);
995 usrp_basic_rx::pga_db_per_step() const
997 return common_pga_db_per_step(C_RX);
1001 usrp_basic_rx::_write_oe (int which_side, int value, int mask)
1003 return _common_write_oe(C_RX, which_side, value, mask);
1007 usrp_basic_rx::write_io (int which_side, int value, int mask)
1009 return common_write_io(C_RX, which_side, value, mask);
1013 usrp_basic_rx::read_io (int which_side, int *value)
1015 return common_read_io(C_RX, which_side, value);
1019 usrp_basic_rx::read_io (int which_side)
1021 return common_read_io(C_RX, which_side);
1025 usrp_basic_rx::write_refclk(int which_side, int value)
1027 return common_write_refclk(C_RX, which_side, value);
1031 usrp_basic_rx::write_atr_mask(int which_side, int value)
1033 return common_write_atr_mask(C_RX, which_side, value);
1037 usrp_basic_rx::write_atr_txval(int which_side, int value)
1039 return common_write_atr_txval(C_RX, which_side, value);
1043 usrp_basic_rx::write_atr_rxval(int which_side, int value)
1045 return common_write_atr_rxval(C_RX, which_side, value);
1049 usrp_basic_rx::write_aux_dac (int which_side, int which_dac, int value)
1051 return common_write_aux_dac(C_RX, which_side, which_dac, value);
1055 usrp_basic_rx::read_aux_adc (int which_side, int which_adc, int *value)
1057 return common_read_aux_adc(C_RX, which_side, which_adc, value);
1061 usrp_basic_rx::read_aux_adc (int which_side, int which_adc)
1063 return common_read_aux_adc(C_RX, which_side, which_adc);
1067 usrp_basic_rx::block_size () const { return d_ephandle->block_size(); }
1069 ////////////////////////////////////////////////////////////////
1073 ////////////////////////////////////////////////////////////////
1077 // DAC input rate 64 MHz interleaved for a total input rate of 128 MHz
1078 // DAC input is latched on rising edge of CLKOUT2
1081 // coarse modulator disabled
1084 static unsigned char tx_init_regs[] = {
1086 REG_TX_A_OFFSET_LO, 0,
1087 REG_TX_A_OFFSET_HI, 0,
1088 REG_TX_B_OFFSET_LO, 0,
1089 REG_TX_B_OFFSET_HI, 0,
1090 REG_TX_A_GAIN, (TX_X_GAIN_COARSE_FULL | 0),
1091 REG_TX_B_GAIN, (TX_X_GAIN_COARSE_FULL | 0),
1092 REG_TX_PGA, 0xff, // maximum gain (0 dB)
1094 REG_TX_IF, (TX_IF_USE_CLKOUT1
1098 | TX_IF_INTERLEAVED),
1099 REG_TX_DIGITAL, (TX_DIGITAL_2_DATA_PATHS
1100 | TX_DIGITAL_INTERPOLATE_4X),
1101 REG_TX_MODULATOR, (TX_MODULATOR_DISABLE_NCO
1102 | TX_MODULATOR_COARSE_MODULATION_NONE),
1103 REG_TX_NCO_FTW_7_0, 0,
1104 REG_TX_NCO_FTW_15_8, 0,
1105 REG_TX_NCO_FTW_23_16, 0
1108 usrp_basic_tx::usrp_basic_tx (int which_board, int fusb_block_size, int fusb_nblocks,
1109 const std::string fpga_filename,
1110 const std::string firmware_filename)
1111 : usrp_basic (which_board, open_tx_interface, fpga_filename, firmware_filename),
1112 d_devhandle (0), d_ephandle (0),
1113 d_bytes_seen (0), d_first_write (true),
1116 if (!usrp_9862_write_many_all (d_udh, tx_init_regs, sizeof (tx_init_regs))){
1117 fprintf (stderr, "usrp_basic_tx: failed to init AD9862 TX regs\n");
1118 throw std::runtime_error ("usrp_basic_tx/init_9862");
1122 // FIXME power down 2nd codec tx path
1123 usrp_9862_write (d_udh, 1, REG_TX_PWR_DN,
1124 (TX_PWR_DN_TX_DIGITAL
1125 | TX_PWR_DN_TX_ANALOG_BOTH));
1128 // Reset the tx path and leave it disabled.
1129 set_tx_enable (false);
1130 usrp_set_fpga_tx_reset (d_udh, true);
1131 usrp_set_fpga_tx_reset (d_udh, false);
1133 set_fpga_tx_sample_rate_divisor (4); // we're using interp x4
1135 probe_tx_slots (false);
1137 //d_db[0] = instantiate_dbs(d_dbid[0], this, 0);
1138 //d_db[1] = instantiate_dbs(d_dbid[1], this, 1);
1140 // check fusb buffering parameters
1142 if (fusb_block_size < 0 || fusb_block_size > FUSB_BLOCK_SIZE)
1143 throw std::out_of_range ("usrp_basic_rx: invalid fusb_block_size");
1145 if (fusb_nblocks < 0)
1146 throw std::out_of_range ("usrp_basic_rx: invalid fusb_nblocks");
1148 if (fusb_block_size == 0)
1149 fusb_block_size = FUSB_BLOCK_SIZE;
1151 if (fusb_nblocks == 0)
1152 fusb_nblocks = std::max (1, FUSB_BUFFER_SIZE / fusb_block_size);
1154 d_devhandle = fusb_sysconfig::make_devhandle (d_udh, d_ctx);
1155 d_ephandle = d_devhandle->make_ephandle (USRP_TX_ENDPOINT, false,
1156 fusb_block_size, fusb_nblocks);
1158 write_atr_mask(0, 0); // zero Tx A Auto Transmit/Receive regs
1159 write_atr_txval(0, 0);
1160 write_atr_rxval(0, 0);
1161 write_atr_mask(1, 0); // zero Tx B Auto Transmit/Receive regs
1162 write_atr_txval(1, 0);
1163 write_atr_rxval(1, 0);
1167 static unsigned char tx_fini_regs[] = {
1168 REG_TX_PWR_DN, (TX_PWR_DN_TX_DIGITAL
1169 | TX_PWR_DN_TX_ANALOG_BOTH),
1170 REG_TX_MODULATOR, (TX_MODULATOR_DISABLE_NCO
1171 | TX_MODULATOR_COARSE_MODULATION_NONE)
1174 usrp_basic_tx::~usrp_basic_tx ()
1176 d_ephandle->stop ();
1180 if (!usrp_9862_write_many_all (d_udh, tx_fini_regs, sizeof (tx_fini_regs))){
1181 fprintf (stderr, "usrp_basic_tx: failed to fini AD9862 TX regs\n");
1184 shutdown_daughterboards();
1188 usrp_basic_tx::start ()
1190 if (!usrp_basic::start ())
1193 if (!set_tx_enable (true)){
1194 fprintf (stderr, "usrp_basic_tx: set_tx_enable failed\n");
1198 if (!d_ephandle->start ()){
1199 fprintf (stderr, "usrp_basic_tx: failed to start end point streaming");
1207 usrp_basic_tx::stop ()
1209 bool ok = usrp_basic::stop ();
1211 if (!d_ephandle->stop ()){
1212 fprintf (stderr, "usrp_basic_tx: failed to stop end point streaming");
1216 if (!set_tx_enable (false)){
1217 fprintf (stderr, "usrp_basic_tx: set_tx_enable(false) failed\n");
1225 usrp_basic_tx::make (int which_board, int fusb_block_size, int fusb_nblocks,
1226 const std::string fpga_filename,
1227 const std::string firmware_filename)
1229 usrp_basic_tx *u = 0;
1232 u = new usrp_basic_tx (which_board, fusb_block_size, fusb_nblocks,
1233 fpga_filename, firmware_filename);
1245 usrp_basic_tx::set_fpga_tx_sample_rate_divisor (unsigned int div)
1247 return _write_fpga_reg (FR_TX_SAMPLE_RATE_DIV, div - 1);
1251 * \brief Write data to the A/D's via the FPGA.
1253 * \p len must be a multiple of 512 bytes.
1254 * \returns number of bytes written or -1 on error.
1256 * if \p underrun is non-NULL, it will be set to true iff
1257 * a transmit underrun condition is detected.
1260 usrp_basic_tx::write (const void *buf, int len, bool *underrun)
1267 if (len < 0 || (len % 512) != 0){
1268 fprintf (stderr, "usrp_basic_tx::write: invalid length = %d\n", len);
1272 r = d_ephandle->write (buf, len);
1277 * In many cases, the FPGA reports an tx underrun right after we
1278 * enable the Tx path. If this is our first write, check for the
1279 * underrun to clear the condition, then ignore the result.
1281 if (d_first_write && d_bytes_seen >= 4 * FUSB_BLOCK_SIZE){
1282 d_first_write = false;
1283 bool bogus_underrun;
1284 usrp_check_tx_underrun (d_udh, &bogus_underrun);
1287 if (underrun != 0 && d_bytes_seen >= d_bytes_per_poll){
1289 if (!usrp_check_tx_underrun (d_udh, underrun)){
1290 fprintf (stderr, "usrp_basic_tx: usrp_check_tx_underrun failed\n");
1298 usrp_basic_tx::wait_for_completion ()
1300 d_ephandle->wait_for_completion ();
1304 usrp_basic_tx::set_tx_enable (bool on)
1307 // fprintf (stderr, "set_tx_enable %d\n", on);
1308 return usrp_set_fpga_tx_enable (d_udh, on);
1311 // conditional disable, return prev state
1313 usrp_basic_tx::disable_tx ()
1315 bool enabled = tx_enable ();
1317 set_tx_enable (false);
1323 usrp_basic_tx::restore_tx (bool on)
1325 if (on != tx_enable ())
1330 usrp_basic_tx::probe_tx_slots (bool verbose)
1332 struct usrp_dboard_eeprom eeprom;
1333 static int slot_id_map[2] = { SLOT_TX_A, SLOT_TX_B };
1334 static const char *slot_name[2] = { "TX d'board A", "TX d'board B" };
1336 for (int i = 0; i < 2; i++){
1337 int slot_id = slot_id_map [i];
1338 const char *msg = 0;
1339 usrp_dbeeprom_status_t s = usrp_read_dboard_eeprom (d_udh, slot_id, &eeprom);
1343 d_dbid[i] = eeprom.id;
1344 msg = usrp_dbid_to_string (eeprom.id).c_str ();
1345 // FIXME, figure out interpretation of dc offset for TX d'boards
1346 // offset = (eeprom.offset[1] << 16) | (eeprom.offset[0] & 0xffff);
1347 _write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | eeprom.oe);
1348 _write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
1351 case UDBE_NO_EEPROM:
1354 _write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | 0x0000);
1355 _write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
1358 case UDBE_INVALID_EEPROM:
1360 msg = "Invalid EEPROM contents";
1361 _write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | 0x0000);
1362 _write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
1372 fprintf (stderr, "%s: %s\n", slot_name[i], msg);
1378 usrp_basic_tx::set_pga (int which_amp, double gain)
1380 return common_set_pga(C_TX, which_amp, gain);
1384 usrp_basic_tx::pga (int which_amp) const
1386 return common_pga(C_TX, which_amp);
1390 usrp_basic_tx::pga_min() const
1392 return common_pga_min(C_TX);
1396 usrp_basic_tx::pga_max() const
1398 return common_pga_max(C_TX);
1402 usrp_basic_tx::pga_db_per_step() const
1404 return common_pga_db_per_step(C_TX);
1408 usrp_basic_tx::_write_oe (int which_side, int value, int mask)
1410 return _common_write_oe(C_TX, which_side, value, mask);
1414 usrp_basic_tx::write_io (int which_side, int value, int mask)
1416 return common_write_io(C_TX, which_side, value, mask);
1420 usrp_basic_tx::read_io (int which_side, int *value)
1422 return common_read_io(C_TX, which_side, value);
1426 usrp_basic_tx::read_io (int which_side)
1428 return common_read_io(C_TX, which_side);
1432 usrp_basic_tx::write_refclk(int which_side, int value)
1434 return common_write_refclk(C_TX, which_side, value);
1438 usrp_basic_tx::write_atr_mask(int which_side, int value)
1440 return common_write_atr_mask(C_TX, which_side, value);
1444 usrp_basic_tx::write_atr_txval(int which_side, int value)
1446 return common_write_atr_txval(C_TX, which_side, value);
1450 usrp_basic_tx::write_atr_rxval(int which_side, int value)
1452 return common_write_atr_rxval(C_TX, which_side, value);
1456 usrp_basic_tx::write_aux_dac (int which_side, int which_dac, int value)
1458 return common_write_aux_dac(C_TX, which_side, which_dac, value);
1462 usrp_basic_tx::read_aux_adc (int which_side, int which_adc, int *value)
1464 return common_read_aux_adc(C_TX, which_side, which_adc, value);
1468 usrp_basic_tx::read_aux_adc (int which_side, int which_adc)
1470 return common_read_aux_adc(C_TX, which_side, which_adc);
1474 usrp_basic_tx::block_size () const { return d_ephandle->block_size(); }