3 * Copyright 2003,2004 Free Software Foundation, Inc.
5 * This file is part of GNU Radio
7 * GNU Radio is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2, or (at your option)
12 * GNU Radio is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with GNU Radio; see the file COPYING. If not, write to
19 * the Free Software Foundation, Inc., 51 Franklin Street,
20 * Boston, MA 02110-1301, USA.
27 #include "usrp_basic.h"
28 #include "usrp_prims.h"
29 #include "usrp_interfaces.h"
30 #include "fpga_regs_common.h"
38 using namespace ad9862;
40 #define NELEM(x) (sizeof (x) / sizeof (x[0]))
42 // These set the buffer size used for each end point using the fast
43 // usb interface. The kernel ends up locking down this much memory.
45 static const int FUSB_BUFFER_SIZE = 2 * (1L << 20); // 2 MB (was 8 MB)
46 //static const int FUSB_BUFFER_SIZE = 256 * (1L << 10); // 256 kB
47 static const int FUSB_BLOCK_SIZE = fusb_sysconfig::max_block_size();
48 static const int FUSB_NBLOCKS = FUSB_BUFFER_SIZE / FUSB_BLOCK_SIZE;
51 static const double POLLING_INTERVAL = 0.1; // seconds
53 ////////////////////////////////////////////////////////////////
55 static struct usb_dev_handle *
56 open_rx_interface (struct usb_device *dev)
58 struct usb_dev_handle *udh = usrp_open_rx_interface (dev);
60 fprintf (stderr, "usrp_basic_rx: can't open rx interface\n");
66 static struct usb_dev_handle *
67 open_tx_interface (struct usb_device *dev)
69 struct usb_dev_handle *udh = usrp_open_tx_interface (dev);
71 fprintf (stderr, "usrp_basic_tx: can't open tx interface\n");
78 //////////////////////////////////////////////////////////////////
82 ////////////////////////////////////////////////////////////////
89 // These settings give us:
90 // CLKOUT1 = CLKIN = 64 MHz
91 // CLKOUT2 = CLKIN = 64 MHz
92 // ADC is clocked at 64 MHz
93 // DAC is clocked at 128 MHz
95 static unsigned char common_regs[] = {
97 REG_DLL, (DLL_DISABLE_INTERNAL_XTAL_OSC
100 REG_CLKOUT, CLKOUT2_EQ_DLL_OVER_2,
101 REG_AUX_ADC_CLK, AUX_ADC_CLK_CLK_OVER_4
105 usrp_basic::usrp_basic (int which_board,
106 struct usb_dev_handle *
107 open_interface (struct usb_device *dev),
108 const std::string fpga_filename,
109 const std::string firmware_filename)
111 d_usb_data_rate (16000000), // SWAG, see below
112 d_bytes_per_poll ((int) (POLLING_INTERVAL * d_usb_data_rate)),
116 * SWAG: Scientific Wild Ass Guess.
118 * d_usb_data_rate is used only to determine how often to poll for over- and under-runs.
119 * We defualt it to 1/2 of our best case. Classes derived from usrp_basic (e.g.,
120 * usrp_standard_tx and usrp_standard_rx) call set_usb_data_rate() to tell us the
121 * actual rate. This doesn't change our throughput, that's determined by the signal
122 * processing code in the FPGA (which we know nothing about), and the system limits
123 * determined by libusb, fusb_*, and the underlying drivers.
125 memset (d_fpga_shadows, 0, sizeof (d_fpga_shadows));
127 usrp_one_time_init ();
129 if (!usrp_load_standard_bits (which_board, false, fpga_filename, firmware_filename))
130 throw std::runtime_error ("usrp_basic/usrp_load_standard_bits");
132 struct usb_device *dev = usrp_find_device (which_board);
134 fprintf (stderr, "usrp_basic: can't find usrp[%d]\n", which_board);
135 throw std::runtime_error ("usrp_basic/usrp_find_device");
138 if (!(usrp_usrp_p(dev) && usrp_hw_rev(dev) >= 1)){
139 fprintf (stderr, "usrp_basic: sorry, this code only works with USRP revs >= 1\n");
140 throw std::runtime_error ("usrp_basic/bad_rev");
143 if ((d_udh = open_interface (dev)) == 0)
144 throw std::runtime_error ("usrp_basic/open_interface");
146 // initialize registers that are common to rx and tx
148 if (!usrp_9862_write_many_all (d_udh, common_regs, sizeof (common_regs))){
149 fprintf (stderr, "usrp_basic: failed to init common AD9862 regs\n");
150 throw std::runtime_error ("usrp_basic/init_9862");
153 _write_fpga_reg (FR_MODE, 0); // ensure we're in normal mode
154 _write_fpga_reg (FR_DEBUG_EN, 0); // disable debug outputs
157 usrp_basic::~usrp_basic ()
176 usrp_basic::set_usb_data_rate (int usb_data_rate)
178 d_usb_data_rate = usb_data_rate;
179 d_bytes_per_poll = (int) (usb_data_rate * POLLING_INTERVAL);
183 usrp_basic::write_aux_dac (int slot, int which_dac, int value)
185 return usrp_write_aux_dac (d_udh, slot, which_dac, value);
189 usrp_basic::read_aux_adc (int slot, int which_adc, int *value)
191 return usrp_read_aux_adc (d_udh, slot, which_adc, value);
195 usrp_basic::read_aux_adc (int slot, int which_adc)
198 if (!read_aux_adc (slot, which_adc, &value))
205 usrp_basic::write_eeprom (int i2c_addr, int eeprom_offset, const std::string buf)
207 return usrp_eeprom_write (d_udh, i2c_addr, eeprom_offset, buf.data (), buf.size ());
211 usrp_basic::read_eeprom (int i2c_addr, int eeprom_offset, int len)
218 if (!usrp_eeprom_read (d_udh, i2c_addr, eeprom_offset, buf, len))
221 return std::string (buf, len);
225 usrp_basic::write_i2c (int i2c_addr, const std::string buf)
227 return usrp_i2c_write (d_udh, i2c_addr, buf.data (), buf.size ());
231 usrp_basic::read_i2c (int i2c_addr, int len)
238 if (!usrp_i2c_read (d_udh, i2c_addr, buf, len))
241 return std::string (buf, len);
245 usrp_basic::serial_number()
247 return usrp_serial_number(d_udh);
250 // ----------------------------------------------------------------
253 usrp_basic::set_adc_offset (int which, int offset)
255 if (which < 0 || which > 3)
258 return _write_fpga_reg (FR_ADC_OFFSET_0 + which, offset);
262 usrp_basic::set_dac_offset (int which, int offset, int offset_pin)
264 if (which < 0 || which > 3)
267 int which_codec = which >> 1;
268 int tx_a = (which & 0x1) == 0;
269 int lo = ((offset & 0x3) << 6) | (offset_pin & 0x1);
270 int hi = (offset >> 2);
274 ok = _write_9862 (which_codec, REG_TX_A_OFFSET_LO, lo);
275 ok &= _write_9862 (which_codec, REG_TX_A_OFFSET_HI, hi);
278 ok = _write_9862 (which_codec, REG_TX_B_OFFSET_LO, lo);
279 ok &= _write_9862 (which_codec, REG_TX_B_OFFSET_HI, hi);
285 usrp_basic::set_adc_buffer_bypass (int which, bool bypass)
287 if (which < 0 || which > 3)
290 int codec = which >> 1;
291 int reg = (which & 1) == 0 ? REG_RX_A : REG_RX_B;
293 unsigned char cur_rx;
294 unsigned char cur_pwr_dn;
296 // If the input buffer is bypassed, we need to power it down too.
298 bool ok = _read_9862 (codec, reg, &cur_rx);
299 ok &= _read_9862 (codec, REG_RX_PWR_DN, &cur_pwr_dn);
304 cur_rx |= RX_X_BYPASS_INPUT_BUFFER;
305 cur_pwr_dn |= ((which & 1) == 0) ? RX_PWR_DN_BUF_A : RX_PWR_DN_BUF_B;
308 cur_rx &= ~RX_X_BYPASS_INPUT_BUFFER;
309 cur_pwr_dn &= ~(((which & 1) == 0) ? RX_PWR_DN_BUF_A : RX_PWR_DN_BUF_B);
312 ok &= _write_9862 (codec, reg, cur_rx);
313 ok &= _write_9862 (codec, REG_RX_PWR_DN, cur_pwr_dn);
317 // ----------------------------------------------------------------
320 usrp_basic::_write_fpga_reg (int regno, int value)
323 fprintf (stdout, "_write_fpga_reg(%3d, 0x%08x)\n", regno, value);
327 if (regno >= 0 && regno < MAX_REGS)
328 d_fpga_shadows[regno] = value;
330 return usrp_write_fpga_reg (d_udh, regno, value);
334 usrp_basic::_write_fpga_reg_masked (int regno, int value, int mask)
336 //Only use this for registers who actually use a mask in the verilog firmware, like FR_RX_MASTER_SLAVE
337 //value is a 16 bits value and mask is a 16 bits mask
339 fprintf (stdout, "_write_fpga_reg_masked(%3d, 0x%04x,0x%04x)\n", regno, value, mask);
343 if (regno >= 0 && regno < MAX_REGS)
344 d_fpga_shadows[regno] = value;
346 return usrp_write_fpga_reg (d_udh, regno, (value & 0xffff) | ((mask & 0xffff)<<16));
351 usrp_basic::_read_fpga_reg (int regno, int *value)
353 return usrp_read_fpga_reg (d_udh, regno, value);
357 usrp_basic::_read_fpga_reg (int regno)
360 if (!_read_fpga_reg (regno, &value))
366 usrp_basic::_write_9862 (int which_codec, int regno, unsigned char value)
369 // FIXME really want to enable logging in usrp_prims:usrp_9862_write
370 fprintf(stdout, "_write_9862(codec = %d, regno = %2d, val = 0x%02x)\n", which_codec, regno, value);
374 return usrp_9862_write (d_udh, which_codec, regno, value);
379 usrp_basic::_read_9862 (int which_codec, int regno, unsigned char *value) const
381 return usrp_9862_read (d_udh, which_codec, regno, value);
385 usrp_basic::_read_9862 (int which_codec, int regno) const
388 if (!_read_9862 (which_codec, regno, &value))
394 usrp_basic::_write_spi (int optional_header, int enables, int format, std::string buf)
396 return usrp_spi_write (d_udh, optional_header, enables, format,
397 buf.data(), buf.size());
401 usrp_basic::_read_spi (int optional_header, int enables, int format, int len)
408 if (!usrp_spi_read (d_udh, optional_header, enables, format, buf, len))
411 return std::string (buf, len);
416 usrp_basic::_set_led (int which, bool on)
418 return usrp_set_led (d_udh, which, on);
421 ////////////////////////////////////////////////////////////////
425 ////////////////////////////////////////////////////////////////
427 static unsigned char rx_init_regs[] = {
429 REG_RX_A, 0, // minimum gain = 0x00 (max gain = 0x14)
430 REG_RX_B, 0, // minimum gain = 0x00 (max gain = 0x14)
431 REG_RX_MISC, (RX_MISC_HS_DUTY_CYCLE | RX_MISC_CLK_DUTY),
432 REG_RX_IF, (RX_IF_USE_CLKOUT1
434 REG_RX_DIGITAL, (RX_DIGITAL_2_CHAN)
438 usrp_basic_rx::usrp_basic_rx (int which_board, int fusb_block_size, int fusb_nblocks,
439 const std::string fpga_filename,
440 const std::string firmware_filename
442 : usrp_basic (which_board, open_rx_interface, fpga_filename, firmware_filename),
443 d_devhandle (0), d_ephandle (0),
444 d_bytes_seen (0), d_first_read (true),
447 // initialize rx specific registers
449 if (!usrp_9862_write_many_all (d_udh, rx_init_regs, sizeof (rx_init_regs))){
450 fprintf (stderr, "usrp_basic_rx: failed to init AD9862 RX regs\n");
451 throw std::runtime_error ("usrp_basic_rx/init_9862");
455 // FIXME power down 2nd codec rx path
456 usrp_9862_write (d_udh, 1, REG_RX_PWR_DN, 0x1); // power down everything
459 // Reset the rx path and leave it disabled.
460 set_rx_enable (false);
461 usrp_set_fpga_rx_reset (d_udh, true);
462 usrp_set_fpga_rx_reset (d_udh, false);
464 set_fpga_rx_sample_rate_divisor (2); // usually correct
466 set_dc_offset_cl_enable(0xf, 0xf); // enable DC offset removal control loops
468 probe_rx_slots (false);
470 // check fusb buffering parameters
472 if (fusb_block_size < 0 || fusb_block_size > FUSB_BLOCK_SIZE)
473 throw std::out_of_range ("usrp_basic_rx: invalid fusb_block_size");
475 if (fusb_nblocks < 0)
476 throw std::out_of_range ("usrp_basic_rx: invalid fusb_nblocks");
478 if (fusb_block_size == 0)
479 fusb_block_size = FUSB_BLOCK_SIZE;
481 if (fusb_nblocks == 0)
482 fusb_nblocks = std::max (1, FUSB_BUFFER_SIZE / fusb_block_size);
484 d_devhandle = fusb_sysconfig::make_devhandle (d_udh);
485 d_ephandle = d_devhandle->make_ephandle (USRP_RX_ENDPOINT, true,
486 fusb_block_size, fusb_nblocks);
488 _write_fpga_reg(FR_ATR_MASK_1, 0); // zero Rx side Auto Transmit/Receive regs
489 _write_fpga_reg(FR_ATR_TXVAL_1, 0);
490 _write_fpga_reg(FR_ATR_RXVAL_1, 0);
491 _write_fpga_reg(FR_ATR_MASK_3, 0);
492 _write_fpga_reg(FR_ATR_TXVAL_3, 0);
493 _write_fpga_reg(FR_ATR_RXVAL_3, 0);
496 static unsigned char rx_fini_regs[] = {
497 REG_RX_PWR_DN, 0x1 // power down everything
500 usrp_basic_rx::~usrp_basic_rx ()
502 if (!set_rx_enable (false)){
503 fprintf (stderr, "usrp_basic_rx: set_fpga_rx_enable failed\n");
511 if (!usrp_9862_write_many_all (d_udh, rx_fini_regs, sizeof (rx_fini_regs))){
512 fprintf (stderr, "usrp_basic_rx: failed to fini AD9862 RX regs\n");
518 usrp_basic_rx::start ()
520 if (!usrp_basic::start ()) // invoke parent's method
523 // fire off reads before asserting rx_enable
525 if (!d_ephandle->start ()){
526 fprintf (stderr, "usrp_basic_rx: failed to start end point streaming");
531 if (!set_rx_enable (true)){
532 fprintf (stderr, "usrp_basic_rx: set_rx_enable failed\n");
541 usrp_basic_rx::stop ()
543 bool ok = usrp_basic::stop();
545 if (!d_ephandle->stop()){
546 fprintf (stderr, "usrp_basic_rx: failed to stop end point streaming");
550 if (!set_rx_enable(false)){
551 fprintf (stderr, "usrp_basic_rx: set_rx_enable(false) failed\n");
559 usrp_basic_rx::make (int which_board, int fusb_block_size, int fusb_nblocks,
560 const std::string fpga_filename,
561 const std::string firmware_filename)
563 usrp_basic_rx *u = 0;
566 u = new usrp_basic_rx (which_board, fusb_block_size, fusb_nblocks,
567 fpga_filename, firmware_filename);
579 usrp_basic_rx::set_fpga_rx_sample_rate_divisor (unsigned int div)
581 return _write_fpga_reg (FR_RX_SAMPLE_RATE_DIV, div - 1);
586 * \brief read data from the D/A's via the FPGA.
587 * \p len must be a multiple of 512 bytes.
589 * \returns the number of bytes read, or -1 on error.
591 * If overrun is non-NULL it will be set true iff an RX overrun is detected.
594 usrp_basic_rx::read (void *buf, int len, bool *overrun)
601 if (len < 0 || (len % 512) != 0){
602 fprintf (stderr, "usrp_basic_rx::read: invalid length = %d\n", len);
606 r = d_ephandle->read (buf, len);
611 * In many cases, the FPGA reports an rx overrun right after we
612 * enable the Rx path. If this is our first read, check for the
613 * overrun to clear the condition, then ignore the result.
615 if (0 && d_first_read){ // FIXME
616 d_first_read = false;
618 usrp_check_rx_overrun (d_udh, &bogus_overrun);
621 if (overrun != 0 && d_bytes_seen >= d_bytes_per_poll){
623 if (!usrp_check_rx_overrun (d_udh, overrun)){
624 fprintf (stderr, "usrp_basic_rx: usrp_check_rx_overrun failed\n");
633 usrp_basic_rx::set_rx_enable (bool on)
636 return usrp_set_fpga_rx_enable (d_udh, on);
639 // conditional disable, return prev state
641 usrp_basic_rx::disable_rx ()
643 bool enabled = rx_enable ();
645 set_rx_enable (false);
651 usrp_basic_rx::restore_rx (bool on)
653 if (on != rx_enable ())
658 usrp_basic_rx::set_pga (int which, double gain)
660 if (which < 0 || which > 3)
663 gain = std::max (pga_min (), gain);
664 gain = std::min (pga_max (), gain);
666 int codec = which >> 1;
667 int reg = (which & 1) == 0 ? REG_RX_A : REG_RX_B;
669 // read current value to get input buffer bypass flag.
670 unsigned char cur_rx;
671 if (!_read_9862 (codec, reg, &cur_rx))
674 int int_gain = (int) rint ((gain - pga_min ()) / pga_db_per_step());
676 cur_rx = (cur_rx & RX_X_BYPASS_INPUT_BUFFER) | (int_gain & 0x7f);
677 return _write_9862 (codec, reg, cur_rx);
681 usrp_basic_rx::pga (int which) const
683 if (which < 0 || which > 3)
686 int codec = which >> 1;
687 int reg = (which & 1) == 0 ? REG_RX_A : REG_RX_B;
689 bool ok = _read_9862 (codec, reg, &v);
693 return (pga_db_per_step() * (v & 0x1f)) + pga_min();
697 slot_id_to_oe_reg (int slot_id)
699 static int reg[4] = { FR_OE_0, FR_OE_1, FR_OE_2, FR_OE_3 };
700 assert (0 <= slot_id && slot_id < 4);
705 slot_id_to_io_reg (int slot_id)
707 static int reg[4] = { FR_IO_0, FR_IO_1, FR_IO_2, FR_IO_3 };
708 assert (0 <= slot_id && slot_id < 4);
713 usrp_basic_rx::probe_rx_slots (bool verbose)
715 struct usrp_dboard_eeprom eeprom;
716 static int slot_id_map[2] = { SLOT_RX_A, SLOT_RX_B };
717 static const char *slot_name[2] = { "RX d'board A", "RX d'board B" };
719 for (int i = 0; i < 2; i++){
720 int slot_id = slot_id_map [i];
722 usrp_dbeeprom_status_t s = usrp_read_dboard_eeprom (d_udh, slot_id, &eeprom);
726 d_dbid[i] = eeprom.id;
727 msg = usrp_dbid_to_string (eeprom.id).c_str ();
728 set_adc_offset (2*i+0, eeprom.offset[0]);
729 set_adc_offset (2*i+1, eeprom.offset[1]);
730 _write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | eeprom.oe);
731 _write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
737 _write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | 0x0000);
738 _write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
741 case UDBE_INVALID_EEPROM:
743 msg = "Invalid EEPROM contents";
744 _write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | 0x0000);
745 _write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
755 fprintf (stderr, "%s: %s\n", slot_name[i], msg);
761 usrp_basic_rx::_write_oe (int which_dboard, int value, int mask)
763 if (! (0 <= which_dboard && which_dboard <= 1))
766 return _write_fpga_reg (slot_id_to_oe_reg (dboard_to_slot (which_dboard)),
767 (mask << 16) | (value & 0xffff));
771 usrp_basic_rx::write_io (int which_dboard, int value, int mask)
773 if (! (0 <= which_dboard && which_dboard <= 1))
776 return _write_fpga_reg (slot_id_to_io_reg (dboard_to_slot (which_dboard)),
777 (mask << 16) | (value & 0xffff));
781 usrp_basic_rx::read_io (int which_dboard, int *value)
783 if (! (0 <= which_dboard && which_dboard <= 1))
787 int reg = which_dboard + 1; // FIXME, *very* magic number (fix in serial_io.v)
788 bool ok = _read_fpga_reg (reg, &t);
792 *value = (t >> 16) & 0xffff; // FIXME, more magic
797 usrp_basic_rx::read_io (int which_dboard)
800 if (!read_io (which_dboard, &value))
806 usrp_basic_rx::write_aux_dac (int which_dboard, int which_dac, int value)
808 return usrp_basic::write_aux_dac (dboard_to_slot (which_dboard),
813 usrp_basic_rx::read_aux_adc (int which_dboard, int which_adc, int *value)
815 return usrp_basic::read_aux_adc (dboard_to_slot (which_dboard),
820 usrp_basic_rx::read_aux_adc (int which_dboard, int which_adc)
822 return usrp_basic::read_aux_adc (dboard_to_slot (which_dboard), which_adc);
826 usrp_basic_rx::block_size () const { return d_ephandle->block_size(); }
829 usrp_basic_rx::set_dc_offset_cl_enable(int bits, int mask)
831 return _write_fpga_reg(FR_DC_OFFSET_CL_EN,
832 (d_fpga_shadows[FR_DC_OFFSET_CL_EN] & ~mask) | (bits & mask));
835 ////////////////////////////////////////////////////////////////
839 ////////////////////////////////////////////////////////////////
843 // DAC input rate 64 MHz interleaved for a total input rate of 128 MHz
844 // DAC input is latched on rising edge of CLKOUT2
847 // coarse modulator disabled
850 static unsigned char tx_init_regs[] = {
852 REG_TX_A_OFFSET_LO, 0,
853 REG_TX_A_OFFSET_HI, 0,
854 REG_TX_B_OFFSET_LO, 0,
855 REG_TX_B_OFFSET_HI, 0,
856 REG_TX_A_GAIN, (TX_X_GAIN_COARSE_FULL | 0),
857 REG_TX_B_GAIN, (TX_X_GAIN_COARSE_FULL | 0),
858 REG_TX_PGA, 0xff, // maximum gain (0 dB)
860 REG_TX_IF, (TX_IF_USE_CLKOUT1
864 | TX_IF_INTERLEAVED),
865 REG_TX_DIGITAL, (TX_DIGITAL_2_DATA_PATHS
866 | TX_DIGITAL_INTERPOLATE_4X),
867 REG_TX_MODULATOR, (TX_MODULATOR_DISABLE_NCO
868 | TX_MODULATOR_COARSE_MODULATION_NONE),
869 REG_TX_NCO_FTW_7_0, 0,
870 REG_TX_NCO_FTW_15_8, 0,
871 REG_TX_NCO_FTW_23_16, 0
874 usrp_basic_tx::usrp_basic_tx (int which_board, int fusb_block_size, int fusb_nblocks,
875 const std::string fpga_filename,
876 const std::string firmware_filename)
877 : usrp_basic (which_board, open_tx_interface, fpga_filename, firmware_filename),
878 d_devhandle (0), d_ephandle (0),
879 d_bytes_seen (0), d_first_write (true),
882 if (!usrp_9862_write_many_all (d_udh, tx_init_regs, sizeof (tx_init_regs))){
883 fprintf (stderr, "usrp_basic_tx: failed to init AD9862 TX regs\n");
884 throw std::runtime_error ("usrp_basic_tx/init_9862");
888 // FIXME power down 2nd codec tx path
889 usrp_9862_write (d_udh, 1, REG_TX_PWR_DN,
890 (TX_PWR_DN_TX_DIGITAL
891 | TX_PWR_DN_TX_ANALOG_BOTH));
894 // Reset the tx path and leave it disabled.
895 set_tx_enable (false);
896 usrp_set_fpga_tx_reset (d_udh, true);
897 usrp_set_fpga_tx_reset (d_udh, false);
899 set_fpga_tx_sample_rate_divisor (4); // we're using interp x4
901 probe_tx_slots (false);
903 // check fusb buffering parameters
905 if (fusb_block_size < 0 || fusb_block_size > FUSB_BLOCK_SIZE)
906 throw std::out_of_range ("usrp_basic_rx: invalid fusb_block_size");
908 if (fusb_nblocks < 0)
909 throw std::out_of_range ("usrp_basic_rx: invalid fusb_nblocks");
911 if (fusb_block_size == 0)
912 fusb_block_size = FUSB_BLOCK_SIZE;
914 if (fusb_nblocks == 0)
915 fusb_nblocks = std::max (1, FUSB_BUFFER_SIZE / fusb_block_size);
917 d_devhandle = fusb_sysconfig::make_devhandle (d_udh);
918 d_ephandle = d_devhandle->make_ephandle (USRP_TX_ENDPOINT, false,
919 fusb_block_size, fusb_nblocks);
921 _write_fpga_reg(FR_ATR_MASK_0, 0); // zero Tx side Auto Transmit/Receive regs
922 _write_fpga_reg(FR_ATR_TXVAL_0, 0);
923 _write_fpga_reg(FR_ATR_RXVAL_0, 0);
924 _write_fpga_reg(FR_ATR_MASK_2, 0);
925 _write_fpga_reg(FR_ATR_TXVAL_2, 0);
926 _write_fpga_reg(FR_ATR_RXVAL_2, 0);
930 static unsigned char tx_fini_regs[] = {
931 REG_TX_PWR_DN, (TX_PWR_DN_TX_DIGITAL
932 | TX_PWR_DN_TX_ANALOG_BOTH),
933 REG_TX_MODULATOR, (TX_MODULATOR_DISABLE_NCO
934 | TX_MODULATOR_COARSE_MODULATION_NONE)
937 usrp_basic_tx::~usrp_basic_tx ()
943 if (!usrp_9862_write_many_all (d_udh, tx_fini_regs, sizeof (tx_fini_regs))){
944 fprintf (stderr, "usrp_basic_tx: failed to fini AD9862 TX regs\n");
949 usrp_basic_tx::start ()
951 if (!usrp_basic::start ())
954 if (!set_tx_enable (true)){
955 fprintf (stderr, "usrp_basic_tx: set_tx_enable failed\n");
960 if (!d_ephandle->start ()){
961 fprintf (stderr, "usrp_basic_tx: failed to start end point streaming");
970 usrp_basic_tx::stop ()
972 bool ok = usrp_basic::stop ();
974 if (!set_tx_enable (false)){
975 fprintf (stderr, "usrp_basic_tx: set_tx_enable(false) failed\n");
979 if (!d_ephandle->stop ()){
980 fprintf (stderr, "usrp_basic_tx: failed to stop end point streaming");
988 usrp_basic_tx::make (int which_board, int fusb_block_size, int fusb_nblocks,
989 const std::string fpga_filename,
990 const std::string firmware_filename)
992 usrp_basic_tx *u = 0;
995 u = new usrp_basic_tx (which_board, fusb_block_size, fusb_nblocks,
996 fpga_filename, firmware_filename);
1008 usrp_basic_tx::set_fpga_tx_sample_rate_divisor (unsigned int div)
1010 return _write_fpga_reg (FR_TX_SAMPLE_RATE_DIV, div - 1);
1014 * \brief Write data to the A/D's via the FPGA.
1016 * \p len must be a multiple of 512 bytes.
1017 * \returns number of bytes written or -1 on error.
1019 * if \p underrun is non-NULL, it will be set to true iff
1020 * a transmit underrun condition is detected.
1023 usrp_basic_tx::write (const void *buf, int len, bool *underrun)
1030 if (len < 0 || (len % 512) != 0){
1031 fprintf (stderr, "usrp_basic_tx::write: invalid length = %d\n", len);
1035 r = d_ephandle->write (buf, len);
1040 * In many cases, the FPGA reports an tx underrun right after we
1041 * enable the Tx path. If this is our first write, check for the
1042 * underrun to clear the condition, then ignore the result.
1044 if (d_first_write && d_bytes_seen >= 4 * FUSB_BLOCK_SIZE){
1045 d_first_write = false;
1046 bool bogus_underrun;
1047 usrp_check_tx_underrun (d_udh, &bogus_underrun);
1050 if (underrun != 0 && d_bytes_seen >= d_bytes_per_poll){
1052 if (!usrp_check_tx_underrun (d_udh, underrun)){
1053 fprintf (stderr, "usrp_basic_tx: usrp_check_tx_underrun failed\n");
1062 usrp_basic_tx::wait_for_completion ()
1064 d_ephandle->wait_for_completion ();
1068 usrp_basic_tx::set_tx_enable (bool on)
1071 // fprintf (stderr, "set_tx_enable %d\n", on);
1072 return usrp_set_fpga_tx_enable (d_udh, on);
1075 // conditional disable, return prev state
1077 usrp_basic_tx::disable_tx ()
1079 bool enabled = tx_enable ();
1081 set_tx_enable (false);
1087 usrp_basic_tx::restore_tx (bool on)
1089 if (on != tx_enable ())
1094 usrp_basic_tx::set_pga (int which, double gain)
1096 if (which < 0 || which > 3)
1099 gain = std::max (pga_min (), gain);
1100 gain = std::min (pga_max (), gain);
1102 int codec = which >> 1; // 0 and 1 are same, as are 2 and 3
1104 int int_gain = (int) rint ((gain - pga_min ()) / pga_db_per_step());
1106 return _write_9862 (codec, REG_TX_PGA, int_gain);
1110 usrp_basic_tx::pga (int which) const
1112 if (which < 0 || which > 3)
1115 int codec = which >> 1;
1117 bool ok = _read_9862 (codec, REG_TX_PGA, &v);
1121 return (pga_db_per_step() * v) + pga_min();
1125 usrp_basic_tx::probe_tx_slots (bool verbose)
1127 struct usrp_dboard_eeprom eeprom;
1128 static int slot_id_map[2] = { SLOT_TX_A, SLOT_TX_B };
1129 static const char *slot_name[2] = { "TX d'board A", "TX d'board B" };
1131 for (int i = 0; i < 2; i++){
1132 int slot_id = slot_id_map [i];
1133 const char *msg = 0;
1134 usrp_dbeeprom_status_t s = usrp_read_dboard_eeprom (d_udh, slot_id, &eeprom);
1138 d_dbid[i] = eeprom.id;
1139 msg = usrp_dbid_to_string (eeprom.id).c_str ();
1140 // FIXME, figure out interpretation of dc offset for TX d'boards
1141 // offset = (eeprom.offset[1] << 16) | (eeprom.offset[0] & 0xffff);
1142 _write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | eeprom.oe);
1143 _write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
1146 case UDBE_NO_EEPROM:
1149 _write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | 0x0000);
1150 _write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
1153 case UDBE_INVALID_EEPROM:
1155 msg = "Invalid EEPROM contents";
1156 _write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | 0x0000);
1157 _write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
1167 fprintf (stderr, "%s: %s\n", slot_name[i], msg);
1173 usrp_basic_tx::_write_oe (int which_dboard, int value, int mask)
1175 if (! (0 <= which_dboard && which_dboard <= 1))
1178 return _write_fpga_reg (slot_id_to_oe_reg (dboard_to_slot (which_dboard)),
1179 (mask << 16) | (value & 0xffff));
1183 usrp_basic_tx::write_io (int which_dboard, int value, int mask)
1185 if (! (0 <= which_dboard && which_dboard <= 1))
1188 return _write_fpga_reg (slot_id_to_io_reg (dboard_to_slot (which_dboard)),
1189 (mask << 16) | (value & 0xffff));
1193 usrp_basic_tx::read_io (int which_dboard, int *value)
1195 if (! (0 <= which_dboard && which_dboard <= 1))
1199 int reg = which_dboard + 1; // FIXME, *very* magic number (fix in serial_io.v)
1200 bool ok = _read_fpga_reg (reg, &t);
1204 *value = t & 0xffff; // FIXME, more magic
1209 usrp_basic_tx::read_io (int which_dboard)
1212 if (!read_io (which_dboard, &value))
1218 usrp_basic_tx::write_aux_dac (int which_dboard, int which_dac, int value)
1220 return usrp_basic::write_aux_dac (dboard_to_slot (which_dboard),
1225 usrp_basic_tx::read_aux_adc (int which_dboard, int which_adc, int *value)
1227 return usrp_basic::read_aux_adc (dboard_to_slot (which_dboard),
1232 usrp_basic_tx::read_aux_adc (int which_dboard, int which_adc)
1234 return usrp_basic::read_aux_adc (dboard_to_slot (which_dboard), which_adc);
1238 usrp_basic_tx::block_size () const { return d_ephandle->block_size(); }