3 * Copyright 2003,2004,2008,2009 Free Software Foundation, Inc.
5 * This file is part of GNU Radio
7 * GNU Radio is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 3, or (at your option)
12 * GNU Radio is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with GNU Radio; see the file COPYING. If not, write to
19 * the Free Software Foundation, Inc., 51 Franklin Street,
20 * Boston, MA 02110-1301, USA.
27 #include <usrp/usrp_basic.h>
28 #include "usrp/usrp_prims.h"
29 #include "usrp_interfaces.h"
30 #include "fpga_regs_common.h"
31 #include "fpga_regs_standard.h"
33 #include "db_boards.h"
34 #include <libusb-1.0/libusb.h>
42 using namespace ad9862;
44 #define NELEM(x) (sizeof (x) / sizeof (x[0]))
46 // These set the buffer size used for each end point using the fast
47 // usb interface. The kernel ends up locking down this much memory.
49 static const int FUSB_BUFFER_SIZE = fusb_sysconfig::default_buffer_size();
50 static const int FUSB_BLOCK_SIZE = fusb_sysconfig::max_block_size();
51 static const int FUSB_NBLOCKS = FUSB_BUFFER_SIZE / FUSB_BLOCK_SIZE;
54 static const double POLLING_INTERVAL = 0.1; // seconds
56 ////////////////////////////////////////////////////////////////
58 static struct libusb_device_handle *
59 open_rx_interface (struct libusb_device *dev)
61 struct libusb_device_handle *udh = usrp_open_rx_interface (dev);
63 fprintf (stderr, "usrp_basic_rx: can't open rx interface\n");
68 static struct libusb_device_handle *
69 open_tx_interface (struct libusb_device *dev)
71 struct libusb_device_handle *udh = usrp_open_tx_interface (dev);
73 fprintf (stderr, "usrp_basic_tx: can't open tx interface\n");
79 //////////////////////////////////////////////////////////////////
83 ////////////////////////////////////////////////////////////////
90 // These settings give us:
91 // CLKOUT1 = CLKIN = 64 MHz
92 // CLKOUT2 = CLKIN = 64 MHz
93 // ADC is clocked at 64 MHz
94 // DAC is clocked at 128 MHz
96 static unsigned char common_regs[] = {
98 REG_DLL, (DLL_DISABLE_INTERNAL_XTAL_OSC
101 REG_CLKOUT, CLKOUT2_EQ_DLL_OVER_2,
102 REG_AUX_ADC_CLK, AUX_ADC_CLK_CLK_OVER_4
106 usrp_basic::usrp_basic (int which_board,
107 struct libusb_device_handle *
108 open_interface (struct libusb_device *dev),
109 const std::string fpga_filename,
110 const std::string firmware_filename)
112 d_usb_data_rate (16000000), // SWAG, see below
113 d_bytes_per_poll ((int) (POLLING_INTERVAL * d_usb_data_rate)),
114 d_verbose (false), d_fpga_master_clock_freq(64000000), d_db(2)
117 * SWAG: Scientific Wild Ass Guess.
119 * d_usb_data_rate is used only to determine how often to poll for over- and under-runs.
120 * We defualt it to 1/2 of our best case. Classes derived from usrp_basic (e.g.,
121 * usrp_standard_tx and usrp_standard_rx) call set_usb_data_rate() to tell us the
122 * actual rate. This doesn't change our throughput, that's determined by the signal
123 * processing code in the FPGA (which we know nothing about), and the system limits
124 * determined by libusb, fusb_*, and the underlying drivers.
126 memset (d_fpga_shadows, 0, sizeof (d_fpga_shadows));
128 usrp_one_time_init ();
130 if (!usrp_load_standard_bits (which_board, false, fpga_filename, firmware_filename))
131 throw std::runtime_error ("usrp_basic/usrp_load_standard_bits");
133 struct libusb_device *dev = usrp_find_device (which_board);
135 fprintf (stderr, "usrp_basic: can't find usrp[%d]\n", which_board);
136 throw std::runtime_error ("usrp_basic/usrp_find_device");
139 if (!(usrp_usrp_p(dev) && usrp_hw_rev(dev) >= 1)){
140 fprintf (stderr, "usrp_basic: sorry, this code only works with USRP revs >= 1\n");
141 throw std::runtime_error ("usrp_basic/bad_rev");
144 if ((d_udh = open_interface (dev)) == 0)
145 throw std::runtime_error ("usrp_basic/open_interface");
147 // initialize registers that are common to rx and tx
149 if (!usrp_9862_write_many_all (d_udh, common_regs, sizeof (common_regs))){
150 fprintf (stderr, "usrp_basic: failed to init common AD9862 regs\n");
151 throw std::runtime_error ("usrp_basic/init_9862");
154 _write_fpga_reg (FR_MODE, 0); // ensure we're in normal mode
155 _write_fpga_reg (FR_DEBUG_EN, 0); // disable debug outputs
159 usrp_basic::shutdown_daughterboards()
161 // nuke d'boards before we close down USB in ~usrp_basic
162 // shutdown() will do any board shutdown while the USRP can still
164 for(size_t i = 0; i < d_db.size(); i++)
165 for(size_t j = 0; j < d_db[i].size(); j++)
166 d_db[i][j]->shutdown();
169 usrp_basic::~usrp_basic ()
171 // shutdown_daughterboards(); // call from ~usrp_basic_{tx,rx}
173 d_db.resize(0); // forget db shared ptrs
176 libusb_close (d_udh);
178 // There's no reference count on the number of times libusb is initialized.
179 // libusb_init can be called multiple times, but libusb_exit shuts down
180 // everything. Leave libusb running for now. Need to add a count so that it
183 //libusb_exit (NULL);
187 usrp_basic::init_db(usrp_basic_sptr u)
190 throw std::invalid_argument("u is not this");
192 d_db[0] = instantiate_dbs(d_dbid[0], u, 0);
193 d_db[1] = instantiate_dbs(d_dbid[1], u, 1);
196 std::vector<db_base_sptr>
197 usrp_basic::db(int which_side)
199 which_side &= 0x1; // clamp it to avoid any reporting any errors
200 return d_db[which_side];
204 usrp_basic::is_valid(const usrp_subdev_spec &ss)
206 if (ss.side < 0 || ss.side > 1)
209 if (ss.subdev < 0 || ss.subdev >= d_db[ss.side].size())
216 usrp_basic::selected_subdev(const usrp_subdev_spec &ss)
219 throw std::invalid_argument("invalid subdev_spec");
221 return d_db[ss.side][ss.subdev];
237 usrp_basic::set_usb_data_rate (int usb_data_rate)
239 d_usb_data_rate = usb_data_rate;
240 d_bytes_per_poll = (int) (usb_data_rate * POLLING_INTERVAL);
244 usrp_basic::_write_aux_dac (int slot, int which_dac, int value)
246 return usrp_write_aux_dac (d_udh, slot, which_dac, value);
250 usrp_basic::_read_aux_adc (int slot, int which_adc, int *value)
252 return usrp_read_aux_adc (d_udh, slot, which_adc, value);
256 usrp_basic::_read_aux_adc (int slot, int which_adc)
259 if (!_read_aux_adc (slot, which_adc, &value))
266 usrp_basic::write_eeprom (int i2c_addr, int eeprom_offset, const std::string buf)
268 return usrp_eeprom_write (d_udh, i2c_addr, eeprom_offset, buf.data (), buf.size ());
272 usrp_basic::read_eeprom (int i2c_addr, int eeprom_offset, int len)
279 if (!usrp_eeprom_read (d_udh, i2c_addr, eeprom_offset, buf, len))
282 return std::string (buf, len);
286 usrp_basic::write_i2c (int i2c_addr, const std::string buf)
288 return usrp_i2c_write (d_udh, i2c_addr, buf.data (), buf.size ());
292 usrp_basic::read_i2c (int i2c_addr, int len)
299 if (!usrp_i2c_read (d_udh, i2c_addr, buf, len))
302 return std::string (buf, len);
306 usrp_basic::serial_number()
308 return usrp_serial_number(d_udh);
311 // ----------------------------------------------------------------
314 usrp_basic::set_adc_offset (int which_adc, int offset)
316 if (which_adc < 0 || which_adc > 3)
319 return _write_fpga_reg (FR_ADC_OFFSET_0 + which_adc, offset);
323 usrp_basic::set_dac_offset (int which_dac, int offset, int offset_pin)
325 if (which_dac < 0 || which_dac > 3)
328 int which_codec = which_dac >> 1;
329 int tx_a = (which_dac & 0x1) == 0;
330 int lo = ((offset & 0x3) << 6) | (offset_pin & 0x1);
331 int hi = (offset >> 2);
335 ok = _write_9862 (which_codec, REG_TX_A_OFFSET_LO, lo);
336 ok &= _write_9862 (which_codec, REG_TX_A_OFFSET_HI, hi);
339 ok = _write_9862 (which_codec, REG_TX_B_OFFSET_LO, lo);
340 ok &= _write_9862 (which_codec, REG_TX_B_OFFSET_HI, hi);
346 usrp_basic::set_adc_buffer_bypass (int which_adc, bool bypass)
348 if (which_adc < 0 || which_adc > 3)
351 int codec = which_adc >> 1;
352 int reg = (which_adc & 1) == 0 ? REG_RX_A : REG_RX_B;
354 unsigned char cur_rx;
355 unsigned char cur_pwr_dn;
357 // If the input buffer is bypassed, we need to power it down too.
359 bool ok = _read_9862 (codec, reg, &cur_rx);
360 ok &= _read_9862 (codec, REG_RX_PWR_DN, &cur_pwr_dn);
365 cur_rx |= RX_X_BYPASS_INPUT_BUFFER;
366 cur_pwr_dn |= ((which_adc & 1) == 0) ? RX_PWR_DN_BUF_A : RX_PWR_DN_BUF_B;
369 cur_rx &= ~RX_X_BYPASS_INPUT_BUFFER;
370 cur_pwr_dn &= ~(((which_adc & 1) == 0) ? RX_PWR_DN_BUF_A : RX_PWR_DN_BUF_B);
373 ok &= _write_9862 (codec, reg, cur_rx);
374 ok &= _write_9862 (codec, REG_RX_PWR_DN, cur_pwr_dn);
379 usrp_basic::set_dc_offset_cl_enable(int bits, int mask)
381 return _write_fpga_reg(FR_DC_OFFSET_CL_EN,
382 (d_fpga_shadows[FR_DC_OFFSET_CL_EN] & ~mask) | (bits & mask));
385 // ----------------------------------------------------------------
388 usrp_basic::_write_fpga_reg (int regno, int value)
391 fprintf (stdout, "_write_fpga_reg(%3d, 0x%08x)\n", regno, value);
395 if (regno >= 0 && regno < MAX_REGS)
396 d_fpga_shadows[regno] = value;
398 return usrp_write_fpga_reg (d_udh, regno, value);
402 usrp_basic::_write_fpga_reg_masked (int regno, int value, int mask)
404 //Only use this for registers who actually use a mask in the verilog firmware, like FR_RX_MASTER_SLAVE
405 //value is a 16 bits value and mask is a 16 bits mask
407 fprintf (stdout, "_write_fpga_reg_masked(%3d, 0x%04x,0x%04x)\n", regno, value, mask);
411 if (regno >= 0 && regno < MAX_REGS)
412 d_fpga_shadows[regno] = value;
414 return usrp_write_fpga_reg (d_udh, regno, (value & 0xffff) | ((mask & 0xffff)<<16));
419 usrp_basic::_read_fpga_reg (int regno, int *value)
421 return usrp_read_fpga_reg (d_udh, regno, value);
425 usrp_basic::_read_fpga_reg (int regno)
428 if (!_read_fpga_reg (regno, &value))
434 usrp_basic::_write_9862 (int which_codec, int regno, unsigned char value)
437 // FIXME really want to enable logging in usrp_prims:usrp_9862_write
438 fprintf(stdout, "_write_9862(codec = %d, regno = %2d, val = 0x%02x)\n", which_codec, regno, value);
442 return usrp_9862_write (d_udh, which_codec, regno, value);
447 usrp_basic::_read_9862 (int which_codec, int regno, unsigned char *value) const
449 return usrp_9862_read (d_udh, which_codec, regno, value);
453 usrp_basic::_read_9862 (int which_codec, int regno) const
456 if (!_read_9862 (which_codec, regno, &value))
462 usrp_basic::_write_spi (int optional_header, int enables, int format, std::string buf)
464 return usrp_spi_write (d_udh, optional_header, enables, format,
465 buf.data(), buf.size());
469 usrp_basic::_read_spi (int optional_header, int enables, int format, int len)
476 if (!usrp_spi_read (d_udh, optional_header, enables, format, buf, len))
479 return std::string (buf, len);
484 usrp_basic::_set_led (int which_led, bool on)
486 return usrp_set_led (d_udh, which_led, on);
490 usrp_basic::write_atr_tx_delay(int value)
492 return _write_fpga_reg(FR_ATR_TX_DELAY, value);
496 usrp_basic::write_atr_rx_delay(int value)
498 return _write_fpga_reg(FR_ATR_RX_DELAY, value);
502 * ----------------------------------------------------------------
503 * Routines to access and control daughterboard specific i/o
504 * ----------------------------------------------------------------
507 slot_id_to_oe_reg (int slot_id)
509 static int reg[4] = { FR_OE_0, FR_OE_1, FR_OE_2, FR_OE_3 };
510 assert (0 <= slot_id && slot_id < 4);
515 slot_id_to_io_reg (int slot_id)
517 static int reg[4] = { FR_IO_0, FR_IO_1, FR_IO_2, FR_IO_3 };
518 assert (0 <= slot_id && slot_id < 4);
523 slot_id_to_refclk_reg(int slot_id)
525 static int reg[4] = { FR_TX_A_REFCLK, FR_RX_A_REFCLK, FR_TX_B_REFCLK, FR_RX_B_REFCLK };
526 assert (0 <= slot_id && slot_id < 4);
531 slot_id_to_atr_mask_reg(int slot_id)
533 static int reg[4] = { FR_ATR_MASK_0, FR_ATR_MASK_1, FR_ATR_MASK_2, FR_ATR_MASK_3 };
534 assert (0 <= slot_id && slot_id < 4);
539 slot_id_to_atr_txval_reg(int slot_id)
541 static int reg[4] = { FR_ATR_TXVAL_0, FR_ATR_TXVAL_1, FR_ATR_TXVAL_2, FR_ATR_TXVAL_3 };
542 assert (0 <= slot_id && slot_id < 4);
547 slot_id_to_atr_rxval_reg(int slot_id)
549 static int reg[4] = { FR_ATR_RXVAL_0, FR_ATR_RXVAL_1, FR_ATR_RXVAL_2, FR_ATR_RXVAL_3 };
550 assert (0 <= slot_id && slot_id < 4);
555 to_slot(txrx_t txrx, int which_side)
561 return ((which_side & 0x1) << 1) | ((txrx & 0x1) == C_RX);
565 usrp_basic::common_set_pga(txrx_t txrx, int which_amp, double gain)
567 if (which_amp < 0 || which_amp > 3)
570 gain = std::min(common_pga_max(txrx),
571 std::max(common_pga_min(txrx), gain));
573 int codec = which_amp >> 1;
574 int int_gain = (int) rint((gain - common_pga_min(txrx)) / common_pga_db_per_step(txrx));
576 if (txrx == C_TX){ // 0 and 1 are same, as are 2 and 3
577 return _write_9862(codec, REG_TX_PGA, int_gain);
580 int reg = (which_amp & 1) == 0 ? REG_RX_A : REG_RX_B;
582 // read current value to get input buffer bypass flag.
583 unsigned char cur_rx;
584 if (!_read_9862(codec, reg, &cur_rx))
587 cur_rx = (cur_rx & RX_X_BYPASS_INPUT_BUFFER) | (int_gain & 0x7f);
588 return _write_9862(codec, reg, cur_rx);
593 usrp_basic::common_pga(txrx_t txrx, int which_amp) const
595 if (which_amp < 0 || which_amp > 3)
599 int codec = which_amp >> 1;
601 bool ok = _read_9862 (codec, REG_TX_PGA, &v);
605 return (pga_db_per_step() * v) + pga_min();
608 int codec = which_amp >> 1;
609 int reg = (which_amp & 1) == 0 ? REG_RX_A : REG_RX_B;
611 bool ok = _read_9862 (codec, reg, &v);
615 return (pga_db_per_step() * (v & 0x1f)) + pga_min();
620 usrp_basic::common_pga_min(txrx_t txrx) const
629 usrp_basic::common_pga_max(txrx_t txrx) const
638 usrp_basic::common_pga_db_per_step(txrx_t txrx) const
647 usrp_basic::_common_write_oe(txrx_t txrx, int which_side, int value, int mask)
649 if (! (0 <= which_side && which_side <= 1))
652 return _write_fpga_reg(slot_id_to_oe_reg(to_slot(txrx, which_side)),
653 (mask << 16) | (value & 0xffff));
657 usrp_basic::common_write_io(txrx_t txrx, int which_side, int value, int mask)
659 if (! (0 <= which_side && which_side <= 1))
662 return _write_fpga_reg(slot_id_to_io_reg(to_slot(txrx, which_side)),
663 (mask << 16) | (value & 0xffff));
667 usrp_basic::common_read_io(txrx_t txrx, int which_side, int *value)
669 if (! (0 <= which_side && which_side <= 1))
673 int reg = which_side + 1; // FIXME, *very* magic number (fix in serial_io.v)
674 bool ok = _read_fpga_reg(reg, &t);
679 *value = t & 0xffff; // FIXME, more magic
683 *value = (t >> 16) & 0xffff; // FIXME, more magic
689 usrp_basic::common_read_io(txrx_t txrx, int which_side)
692 if (!common_read_io(txrx, which_side, &value))
698 usrp_basic::common_write_refclk(txrx_t txrx, int which_side, int value)
700 if (! (0 <= which_side && which_side <= 1))
703 return _write_fpga_reg(slot_id_to_refclk_reg(to_slot(txrx, which_side)),
708 usrp_basic::common_write_atr_mask(txrx_t txrx, int which_side, int value)
710 if (! (0 <= which_side && which_side <= 1))
713 return _write_fpga_reg(slot_id_to_atr_mask_reg(to_slot(txrx, which_side)),
718 usrp_basic::common_write_atr_txval(txrx_t txrx, int which_side, int value)
720 if (! (0 <= which_side && which_side <= 1))
723 return _write_fpga_reg(slot_id_to_atr_txval_reg(to_slot(txrx, which_side)),
728 usrp_basic::common_write_atr_rxval(txrx_t txrx, int which_side, int value)
730 if (! (0 <= which_side && which_side <= 1))
733 return _write_fpga_reg(slot_id_to_atr_rxval_reg(to_slot(txrx, which_side)),
738 usrp_basic::common_write_aux_dac(txrx_t txrx, int which_side, int which_dac, int value)
740 return _write_aux_dac(to_slot(txrx, which_side), which_dac, value);
744 usrp_basic::common_read_aux_adc(txrx_t txrx, int which_side, int which_adc, int *value)
746 return _read_aux_adc(to_slot(txrx, which_side), which_adc, value);
750 usrp_basic::common_read_aux_adc(txrx_t txrx, int which_side, int which_adc)
752 return _read_aux_adc(to_slot(txrx, which_side), which_adc);
756 ////////////////////////////////////////////////////////////////
760 ////////////////////////////////////////////////////////////////
762 static unsigned char rx_init_regs[] = {
764 REG_RX_A, 0, // minimum gain = 0x00 (max gain = 0x14)
765 REG_RX_B, 0, // minimum gain = 0x00 (max gain = 0x14)
766 REG_RX_MISC, (RX_MISC_HS_DUTY_CYCLE | RX_MISC_CLK_DUTY),
767 REG_RX_IF, (RX_IF_USE_CLKOUT1
769 REG_RX_DIGITAL, (RX_DIGITAL_2_CHAN)
773 usrp_basic_rx::usrp_basic_rx (int which_board, int fusb_block_size, int fusb_nblocks,
774 const std::string fpga_filename,
775 const std::string firmware_filename
777 : usrp_basic (which_board, open_rx_interface, fpga_filename, firmware_filename),
778 d_devhandle (0), d_ephandle (0),
779 d_bytes_seen (0), d_first_read (true),
782 // initialize rx specific registers
784 if (!usrp_9862_write_many_all (d_udh, rx_init_regs, sizeof (rx_init_regs))){
785 fprintf (stderr, "usrp_basic_rx: failed to init AD9862 RX regs\n");
786 throw std::runtime_error ("usrp_basic_rx/init_9862");
790 // FIXME power down 2nd codec rx path
791 usrp_9862_write (d_udh, 1, REG_RX_PWR_DN, 0x1); // power down everything
794 // Reset the rx path and leave it disabled.
795 set_rx_enable (false);
796 usrp_set_fpga_rx_reset (d_udh, true);
797 usrp_set_fpga_rx_reset (d_udh, false);
799 set_fpga_rx_sample_rate_divisor (2); // usually correct
801 set_dc_offset_cl_enable(0xf, 0xf); // enable DC offset removal control loops
803 probe_rx_slots (false);
805 //d_db[0] = instantiate_dbs(d_dbid[0], this, 0);
806 //d_db[1] = instantiate_dbs(d_dbid[1], this, 1);
808 // check fusb buffering parameters
810 if (fusb_block_size < 0 || fusb_block_size > FUSB_BLOCK_SIZE)
811 throw std::out_of_range ("usrp_basic_rx: invalid fusb_block_size");
813 if (fusb_nblocks < 0)
814 throw std::out_of_range ("usrp_basic_rx: invalid fusb_nblocks");
816 if (fusb_block_size == 0)
817 fusb_block_size = fusb_sysconfig::default_block_size();
819 if (fusb_nblocks == 0)
820 fusb_nblocks = std::max (1, FUSB_BUFFER_SIZE / fusb_block_size);
822 d_devhandle = fusb_sysconfig::make_devhandle (d_udh);
823 d_ephandle = d_devhandle->make_ephandle (USRP_RX_ENDPOINT, true,
824 fusb_block_size, fusb_nblocks);
826 write_atr_mask(0, 0); // zero Rx A Auto Transmit/Receive regs
827 write_atr_txval(0, 0);
828 write_atr_rxval(0, 0);
829 write_atr_mask(1, 0); // zero Rx B Auto Transmit/Receive regs
830 write_atr_txval(1, 0);
831 write_atr_rxval(1, 0);
834 static unsigned char rx_fini_regs[] = {
835 REG_RX_PWR_DN, 0x1 // power down everything
838 usrp_basic_rx::~usrp_basic_rx ()
840 if (!set_rx_enable (false)){
841 fprintf (stderr, "usrp_basic_rx: set_fpga_rx_enable failed\n");
848 if (!usrp_9862_write_many_all (d_udh, rx_fini_regs, sizeof (rx_fini_regs))){
849 fprintf (stderr, "usrp_basic_rx: failed to fini AD9862 RX regs\n");
852 shutdown_daughterboards();
857 usrp_basic_rx::start ()
859 if (!usrp_basic::start ()) // invoke parent's method
862 // fire off reads before asserting rx_enable
864 if (!d_ephandle->start ()){
865 fprintf (stderr, "usrp_basic_rx: failed to start end point streaming");
869 if (!set_rx_enable (true)){
870 fprintf (stderr, "usrp_basic_rx: set_rx_enable failed\n");
878 usrp_basic_rx::stop ()
880 bool ok = usrp_basic::stop();
882 if (!set_rx_enable(false)){
883 fprintf (stderr, "usrp_basic_rx: set_rx_enable(false) failed\n");
887 if (!d_ephandle->stop()){
888 fprintf (stderr, "usrp_basic_rx: failed to stop end point streaming");
896 usrp_basic_rx::make (int which_board, int fusb_block_size, int fusb_nblocks,
897 const std::string fpga_filename,
898 const std::string firmware_filename)
900 usrp_basic_rx *u = 0;
903 u = new usrp_basic_rx (which_board, fusb_block_size, fusb_nblocks,
904 fpga_filename, firmware_filename);
916 usrp_basic_rx::set_fpga_rx_sample_rate_divisor (unsigned int div)
918 return _write_fpga_reg (FR_RX_SAMPLE_RATE_DIV, div - 1);
923 * \brief read data from the D/A's via the FPGA.
924 * \p len must be a multiple of 512 bytes.
926 * \returns the number of bytes read, or -1 on error.
928 * If overrun is non-NULL it will be set true iff an RX overrun is detected.
931 usrp_basic_rx::read (void *buf, int len, bool *overrun)
938 if (len < 0 || (len % 512) != 0){
939 fprintf (stderr, "usrp_basic_rx::read: invalid length = %d\n", len);
943 r = d_ephandle->read (buf, len);
948 * In many cases, the FPGA reports an rx overrun right after we
949 * enable the Rx path. If this is our first read, check for the
950 * overrun to clear the condition, then ignore the result.
952 if (0 && d_first_read){ // FIXME
953 d_first_read = false;
955 usrp_check_rx_overrun (d_udh, &bogus_overrun);
958 if (overrun != 0 && d_bytes_seen >= d_bytes_per_poll){
960 if (!usrp_check_rx_overrun (d_udh, overrun)){
961 fprintf (stderr, "usrp_basic_rx: usrp_check_rx_overrun failed\n");
969 usrp_basic_rx::set_rx_enable (bool on)
972 return usrp_set_fpga_rx_enable (d_udh, on);
975 // conditional disable, return prev state
977 usrp_basic_rx::disable_rx ()
979 bool enabled = rx_enable ();
981 set_rx_enable (false);
987 usrp_basic_rx::restore_rx (bool on)
989 if (on != rx_enable ())
994 usrp_basic_rx::probe_rx_slots (bool verbose)
996 struct usrp_dboard_eeprom eeprom;
997 static int slot_id_map[2] = { SLOT_RX_A, SLOT_RX_B };
998 static const char *slot_name[2] = { "RX d'board A", "RX d'board B" };
1000 for (int i = 0; i < 2; i++){
1001 int slot_id = slot_id_map [i];
1002 const char *msg = 0;
1003 usrp_dbeeprom_status_t s = usrp_read_dboard_eeprom (d_udh, slot_id, &eeprom);
1007 d_dbid[i] = eeprom.id;
1008 msg = usrp_dbid_to_string (eeprom.id).c_str ();
1009 set_adc_offset (2*i+0, eeprom.offset[0]);
1010 set_adc_offset (2*i+1, eeprom.offset[1]);
1011 _write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | eeprom.oe);
1012 _write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
1015 case UDBE_NO_EEPROM:
1018 _write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | 0x0000);
1019 _write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
1022 case UDBE_INVALID_EEPROM:
1024 msg = "Invalid EEPROM contents";
1025 _write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | 0x0000);
1026 _write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
1036 fprintf (stderr, "%s: %s\n", slot_name[i], msg);
1042 usrp_basic_rx::set_pga (int which_amp, double gain)
1044 return common_set_pga(C_RX, which_amp, gain);
1048 usrp_basic_rx::pga(int which_amp) const
1050 return common_pga(C_RX, which_amp);
1054 usrp_basic_rx::pga_min() const
1056 return common_pga_min(C_RX);
1060 usrp_basic_rx::pga_max() const
1062 return common_pga_max(C_RX);
1066 usrp_basic_rx::pga_db_per_step() const
1068 return common_pga_db_per_step(C_RX);
1072 usrp_basic_rx::_write_oe (int which_side, int value, int mask)
1074 return _common_write_oe(C_RX, which_side, value, mask);
1078 usrp_basic_rx::write_io (int which_side, int value, int mask)
1080 return common_write_io(C_RX, which_side, value, mask);
1084 usrp_basic_rx::read_io (int which_side, int *value)
1086 return common_read_io(C_RX, which_side, value);
1090 usrp_basic_rx::read_io (int which_side)
1092 return common_read_io(C_RX, which_side);
1096 usrp_basic_rx::write_refclk(int which_side, int value)
1098 return common_write_refclk(C_RX, which_side, value);
1102 usrp_basic_rx::write_atr_mask(int which_side, int value)
1104 return common_write_atr_mask(C_RX, which_side, value);
1108 usrp_basic_rx::write_atr_txval(int which_side, int value)
1110 return common_write_atr_txval(C_RX, which_side, value);
1114 usrp_basic_rx::write_atr_rxval(int which_side, int value)
1116 return common_write_atr_rxval(C_RX, which_side, value);
1120 usrp_basic_rx::write_aux_dac (int which_side, int which_dac, int value)
1122 return common_write_aux_dac(C_RX, which_side, which_dac, value);
1126 usrp_basic_rx::read_aux_adc (int which_side, int which_adc, int *value)
1128 return common_read_aux_adc(C_RX, which_side, which_adc, value);
1132 usrp_basic_rx::read_aux_adc (int which_side, int which_adc)
1134 return common_read_aux_adc(C_RX, which_side, which_adc);
1138 usrp_basic_rx::block_size () const { return d_ephandle->block_size(); }
1140 ////////////////////////////////////////////////////////////////
1144 ////////////////////////////////////////////////////////////////
1148 // DAC input rate 64 MHz interleaved for a total input rate of 128 MHz
1149 // DAC input is latched on rising edge of CLKOUT2
1152 // coarse modulator disabled
1155 static unsigned char tx_init_regs[] = {
1157 REG_TX_A_OFFSET_LO, 0,
1158 REG_TX_A_OFFSET_HI, 0,
1159 REG_TX_B_OFFSET_LO, 0,
1160 REG_TX_B_OFFSET_HI, 0,
1161 REG_TX_A_GAIN, (TX_X_GAIN_COARSE_FULL | 0),
1162 REG_TX_B_GAIN, (TX_X_GAIN_COARSE_FULL | 0),
1163 REG_TX_PGA, 0xff, // maximum gain (0 dB)
1165 REG_TX_IF, (TX_IF_USE_CLKOUT1
1169 | TX_IF_INTERLEAVED),
1170 REG_TX_DIGITAL, (TX_DIGITAL_2_DATA_PATHS
1171 | TX_DIGITAL_INTERPOLATE_4X),
1172 REG_TX_MODULATOR, (TX_MODULATOR_DISABLE_NCO
1173 | TX_MODULATOR_COARSE_MODULATION_NONE),
1174 REG_TX_NCO_FTW_7_0, 0,
1175 REG_TX_NCO_FTW_15_8, 0,
1176 REG_TX_NCO_FTW_23_16, 0
1179 usrp_basic_tx::usrp_basic_tx (int which_board, int fusb_block_size, int fusb_nblocks,
1180 const std::string fpga_filename,
1181 const std::string firmware_filename)
1182 : usrp_basic (which_board, open_tx_interface, fpga_filename, firmware_filename),
1183 d_devhandle (0), d_ephandle (0),
1184 d_bytes_seen (0), d_first_write (true),
1187 if (!usrp_9862_write_many_all (d_udh, tx_init_regs, sizeof (tx_init_regs))){
1188 fprintf (stderr, "usrp_basic_tx: failed to init AD9862 TX regs\n");
1189 throw std::runtime_error ("usrp_basic_tx/init_9862");
1193 // FIXME power down 2nd codec tx path
1194 usrp_9862_write (d_udh, 1, REG_TX_PWR_DN,
1195 (TX_PWR_DN_TX_DIGITAL
1196 | TX_PWR_DN_TX_ANALOG_BOTH));
1199 // Reset the tx path and leave it disabled.
1200 set_tx_enable (false);
1201 usrp_set_fpga_tx_reset (d_udh, true);
1202 usrp_set_fpga_tx_reset (d_udh, false);
1204 set_fpga_tx_sample_rate_divisor (4); // we're using interp x4
1206 probe_tx_slots (false);
1208 //d_db[0] = instantiate_dbs(d_dbid[0], this, 0);
1209 //d_db[1] = instantiate_dbs(d_dbid[1], this, 1);
1211 // check fusb buffering parameters
1213 if (fusb_block_size < 0 || fusb_block_size > FUSB_BLOCK_SIZE)
1214 throw std::out_of_range ("usrp_basic_rx: invalid fusb_block_size");
1216 if (fusb_nblocks < 0)
1217 throw std::out_of_range ("usrp_basic_rx: invalid fusb_nblocks");
1219 if (fusb_block_size == 0)
1220 fusb_block_size = FUSB_BLOCK_SIZE;
1222 if (fusb_nblocks == 0)
1223 fusb_nblocks = std::max (1, FUSB_BUFFER_SIZE / fusb_block_size);
1225 d_devhandle = fusb_sysconfig::make_devhandle (d_udh);
1226 d_ephandle = d_devhandle->make_ephandle (USRP_TX_ENDPOINT, false,
1227 fusb_block_size, fusb_nblocks);
1229 write_atr_mask(0, 0); // zero Tx A Auto Transmit/Receive regs
1230 write_atr_txval(0, 0);
1231 write_atr_rxval(0, 0);
1232 write_atr_mask(1, 0); // zero Tx B Auto Transmit/Receive regs
1233 write_atr_txval(1, 0);
1234 write_atr_rxval(1, 0);
1238 static unsigned char tx_fini_regs[] = {
1239 REG_TX_PWR_DN, (TX_PWR_DN_TX_DIGITAL
1240 | TX_PWR_DN_TX_ANALOG_BOTH),
1241 REG_TX_MODULATOR, (TX_MODULATOR_DISABLE_NCO
1242 | TX_MODULATOR_COARSE_MODULATION_NONE)
1245 usrp_basic_tx::~usrp_basic_tx ()
1247 d_ephandle->stop ();
1251 if (!usrp_9862_write_many_all (d_udh, tx_fini_regs, sizeof (tx_fini_regs))){
1252 fprintf (stderr, "usrp_basic_tx: failed to fini AD9862 TX regs\n");
1255 shutdown_daughterboards();
1259 usrp_basic_tx::start ()
1261 if (!usrp_basic::start ())
1264 if (!set_tx_enable (true)){
1265 fprintf (stderr, "usrp_basic_tx: set_tx_enable failed\n");
1269 if (!d_ephandle->start ()){
1270 fprintf (stderr, "usrp_basic_tx: failed to start end point streaming");
1278 usrp_basic_tx::stop ()
1280 bool ok = usrp_basic::stop ();
1282 if (!d_ephandle->stop ()){
1283 fprintf (stderr, "usrp_basic_tx: failed to stop end point streaming");
1287 if (!set_tx_enable (false)){
1288 fprintf (stderr, "usrp_basic_tx: set_tx_enable(false) failed\n");
1296 usrp_basic_tx::make (int which_board, int fusb_block_size, int fusb_nblocks,
1297 const std::string fpga_filename,
1298 const std::string firmware_filename)
1300 usrp_basic_tx *u = 0;
1303 u = new usrp_basic_tx (which_board, fusb_block_size, fusb_nblocks,
1304 fpga_filename, firmware_filename);
1316 usrp_basic_tx::set_fpga_tx_sample_rate_divisor (unsigned int div)
1318 return _write_fpga_reg (FR_TX_SAMPLE_RATE_DIV, div - 1);
1322 * \brief Write data to the A/D's via the FPGA.
1324 * \p len must be a multiple of 512 bytes.
1325 * \returns number of bytes written or -1 on error.
1327 * if \p underrun is non-NULL, it will be set to true iff
1328 * a transmit underrun condition is detected.
1331 usrp_basic_tx::write (const void *buf, int len, bool *underrun)
1338 if (len < 0 || (len % 512) != 0){
1339 fprintf (stderr, "usrp_basic_tx::write: invalid length = %d\n", len);
1343 r = d_ephandle->write (buf, len);
1348 * In many cases, the FPGA reports an tx underrun right after we
1349 * enable the Tx path. If this is our first write, check for the
1350 * underrun to clear the condition, then ignore the result.
1352 if (d_first_write && d_bytes_seen >= 4 * FUSB_BLOCK_SIZE){
1353 d_first_write = false;
1354 bool bogus_underrun;
1355 usrp_check_tx_underrun (d_udh, &bogus_underrun);
1358 if (underrun != 0 && d_bytes_seen >= d_bytes_per_poll){
1360 if (!usrp_check_tx_underrun (d_udh, underrun)){
1361 fprintf (stderr, "usrp_basic_tx: usrp_check_tx_underrun failed\n");
1369 usrp_basic_tx::wait_for_completion ()
1371 d_ephandle->wait_for_completion ();
1375 usrp_basic_tx::set_tx_enable (bool on)
1378 // fprintf (stderr, "set_tx_enable %d\n", on);
1379 return usrp_set_fpga_tx_enable (d_udh, on);
1382 // conditional disable, return prev state
1384 usrp_basic_tx::disable_tx ()
1386 bool enabled = tx_enable ();
1388 set_tx_enable (false);
1394 usrp_basic_tx::restore_tx (bool on)
1396 if (on != tx_enable ())
1401 usrp_basic_tx::probe_tx_slots (bool verbose)
1403 struct usrp_dboard_eeprom eeprom;
1404 static int slot_id_map[2] = { SLOT_TX_A, SLOT_TX_B };
1405 static const char *slot_name[2] = { "TX d'board A", "TX d'board B" };
1407 for (int i = 0; i < 2; i++){
1408 int slot_id = slot_id_map [i];
1409 const char *msg = 0;
1410 usrp_dbeeprom_status_t s = usrp_read_dboard_eeprom (d_udh, slot_id, &eeprom);
1414 d_dbid[i] = eeprom.id;
1415 msg = usrp_dbid_to_string (eeprom.id).c_str ();
1416 // FIXME, figure out interpretation of dc offset for TX d'boards
1417 // offset = (eeprom.offset[1] << 16) | (eeprom.offset[0] & 0xffff);
1418 _write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | eeprom.oe);
1419 _write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
1422 case UDBE_NO_EEPROM:
1425 _write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | 0x0000);
1426 _write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
1429 case UDBE_INVALID_EEPROM:
1431 msg = "Invalid EEPROM contents";
1432 _write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | 0x0000);
1433 _write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
1443 fprintf (stderr, "%s: %s\n", slot_name[i], msg);
1449 usrp_basic_tx::set_pga (int which_amp, double gain)
1451 return common_set_pga(C_TX, which_amp, gain);
1455 usrp_basic_tx::pga (int which_amp) const
1457 return common_pga(C_TX, which_amp);
1461 usrp_basic_tx::pga_min() const
1463 return common_pga_min(C_TX);
1467 usrp_basic_tx::pga_max() const
1469 return common_pga_max(C_TX);
1473 usrp_basic_tx::pga_db_per_step() const
1475 return common_pga_db_per_step(C_TX);
1479 usrp_basic_tx::_write_oe (int which_side, int value, int mask)
1481 return _common_write_oe(C_TX, which_side, value, mask);
1485 usrp_basic_tx::write_io (int which_side, int value, int mask)
1487 return common_write_io(C_TX, which_side, value, mask);
1491 usrp_basic_tx::read_io (int which_side, int *value)
1493 return common_read_io(C_TX, which_side, value);
1497 usrp_basic_tx::read_io (int which_side)
1499 return common_read_io(C_TX, which_side);
1503 usrp_basic_tx::write_refclk(int which_side, int value)
1505 return common_write_refclk(C_TX, which_side, value);
1509 usrp_basic_tx::write_atr_mask(int which_side, int value)
1511 return common_write_atr_mask(C_TX, which_side, value);
1515 usrp_basic_tx::write_atr_txval(int which_side, int value)
1517 return common_write_atr_txval(C_TX, which_side, value);
1521 usrp_basic_tx::write_atr_rxval(int which_side, int value)
1523 return common_write_atr_rxval(C_TX, which_side, value);
1527 usrp_basic_tx::write_aux_dac (int which_side, int which_dac, int value)
1529 return common_write_aux_dac(C_TX, which_side, which_dac, value);
1533 usrp_basic_tx::read_aux_adc (int which_side, int which_adc, int *value)
1535 return common_read_aux_adc(C_TX, which_side, which_adc, value);
1539 usrp_basic_tx::read_aux_adc (int which_side, int which_adc)
1541 return common_read_aux_adc(C_TX, which_side, which_adc);
1545 usrp_basic_tx::block_size () const { return d_ephandle->block_size(); }