3 * Copyright 2003,2004,2008,2009 Free Software Foundation, Inc.
5 * This file is part of GNU Radio
7 * GNU Radio is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 3, or (at your option)
12 * GNU Radio is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with GNU Radio; see the file COPYING. If not, write to
19 * the Free Software Foundation, Inc., 51 Franklin Street,
20 * Boston, MA 02110-1301, USA.
27 #include "usrp/usrp_basic.h"
28 #include "usrp/usrp_prims.h"
29 #include "usrp_interfaces.h"
30 #include "fpga_regs_common.h"
31 #include "fpga_regs_standard.h"
33 #include "db_boards.h"
41 using namespace ad9862;
43 #define NELEM(x) (sizeof (x) / sizeof (x[0]))
45 // These set the buffer size used for each end point using the fast
46 // usb interface. The kernel ends up locking down this much memory.
48 static const int FUSB_BUFFER_SIZE = fusb_sysconfig::default_buffer_size();
49 static const int FUSB_BLOCK_SIZE = fusb_sysconfig::max_block_size();
50 static const int FUSB_NBLOCKS = FUSB_BUFFER_SIZE / FUSB_BLOCK_SIZE;
53 static const double POLLING_INTERVAL = 0.1; // seconds
55 ////////////////////////////////////////////////////////////////
57 static libusb_device_handle *
58 open_rx_interface (libusb_device *dev)
60 libusb_device_handle *udh = usrp_open_rx_interface (dev);
62 fprintf (stderr, "usrp_basic_rx: can't open rx interface\n");
67 static libusb_device_handle *
68 open_tx_interface (libusb_device *dev)
70 libusb_device_handle *udh = usrp_open_tx_interface (dev);
72 fprintf (stderr, "usrp_basic_tx: can't open tx interface\n");
77 //////////////////////////////////////////////////////////////////
81 ////////////////////////////////////////////////////////////////
87 // These settings give us:
88 // CLKOUT1 = CLKIN = 64 MHz
89 // CLKOUT2 = CLKIN = 64 MHz
90 // ADC is clocked at 64 MHz
91 // DAC is clocked at 128 MHz
93 static unsigned char common_regs[] = {
95 REG_DLL, (DLL_DISABLE_INTERNAL_XTAL_OSC
98 REG_CLKOUT, CLKOUT2_EQ_DLL_OVER_2,
99 REG_AUX_ADC_CLK, AUX_ADC_CLK_CLK_OVER_4
102 usrp_basic::usrp_basic (int which_board,
103 libusb_device_handle *
104 open_interface (libusb_device *dev),
105 const std::string fpga_filename,
106 const std::string firmware_filename)
107 : d_udh (0), d_ctx (0),
108 d_usb_data_rate (16000000), // SWAG, see below
109 d_bytes_per_poll ((int) (POLLING_INTERVAL * d_usb_data_rate)),
110 d_verbose (false), d_fpga_master_clock_freq(64000000), d_db(2)
113 * SWAG: Scientific Wild Ass Guess.
115 * d_usb_data_rate is used only to determine how often to poll for over- and
116 * under-runs. We defualt it to 1/2 of our best case. Classes derived from
117 * usrp_basic (e.g., usrp_standard_tx and usrp_standard_rx) call
118 * set_usb_data_rate() to tell us the actual rate. This doesn't change our
119 * throughput, that's determined by the signal processing code in the FPGA
120 * (which we know nothing about), and the system limits determined by libusb,
121 * fusb_*, and the underlying drivers.
123 memset (d_fpga_shadows, 0, sizeof (d_fpga_shadows));
125 usrp_one_time_init (&d_ctx);
127 if (!usrp_load_standard_bits (which_board, false, fpga_filename,
128 firmware_filename, d_ctx))
129 throw std::runtime_error ("usrp_basic/usrp_load_standard_bits");
131 libusb_device *dev = usrp_find_device (which_board, false, d_ctx);
133 fprintf (stderr, "usrp_basic: can't find usrp[%d]\n", which_board);
134 throw std::runtime_error ("usrp_basic/usrp_find_device");
137 if (!(usrp_usrp_p(dev) && usrp_hw_rev(dev) >= 1)){
138 fprintf (stderr, "usrp_basic: sorry, this code only works with USRP revs >= 1\n");
139 throw std::runtime_error ("usrp_basic/bad_rev");
142 if ((d_udh = open_interface (dev)) == 0)
143 throw std::runtime_error ("usrp_basic/open_interface");
145 // initialize registers that are common to rx and tx
147 if (!usrp_9862_write_many_all (d_udh, common_regs, sizeof (common_regs))) {
148 fprintf (stderr, "usrp_basic: failed to init common AD9862 regs\n");
149 throw std::runtime_error ("usrp_basic/init_9862");
152 _write_fpga_reg (FR_MODE, 0); // ensure we're in normal mode
153 _write_fpga_reg (FR_DEBUG_EN, 0); // disable debug outputs
157 usrp_basic::~usrp_basic ()
159 d_db.resize(0); // forget db shared ptrs
162 usrp_close_interface (d_udh);
168 usrp_basic::shutdown_daughterboards()
170 // nuke d'boards before we close down USB in ~usrp_basic
171 // shutdown() will do any board shutdown while the USRP can still
173 for(size_t i = 0; i < d_db.size(); i++)
174 for(size_t j = 0; j < d_db[i].size(); j++)
175 d_db[i][j]->shutdown();
179 usrp_basic::init_db(usrp_basic_sptr u)
182 throw std::invalid_argument("u is not this");
184 d_db[0] = instantiate_dbs(d_dbid[0], u, 0);
185 d_db[1] = instantiate_dbs(d_dbid[1], u, 1);
188 std::vector<db_base_sptr>
189 usrp_basic::db(int which_side)
191 which_side &= 0x1; // clamp it to avoid any reporting any errors
192 return d_db[which_side];
196 usrp_basic::is_valid(const usrp_subdev_spec &ss)
198 if (ss.side < 0 || ss.side > 1)
201 if (ss.subdev < 0 || ss.subdev >= d_db[ss.side].size())
208 usrp_basic::selected_subdev(const usrp_subdev_spec &ss)
211 throw std::invalid_argument("invalid subdev_spec");
213 return d_db[ss.side][ss.subdev];
229 usrp_basic::set_usb_data_rate (int usb_data_rate)
231 d_usb_data_rate = usb_data_rate;
232 d_bytes_per_poll = (int) (usb_data_rate * POLLING_INTERVAL);
236 usrp_basic::_write_aux_dac (int slot, int which_dac, int value)
238 return usrp_write_aux_dac (d_udh, slot, which_dac, value);
242 usrp_basic::_read_aux_adc (int slot, int which_adc, int *value)
244 return usrp_read_aux_adc (d_udh, slot, which_adc, value);
248 usrp_basic::_read_aux_adc (int slot, int which_adc)
251 if (!_read_aux_adc (slot, which_adc, &value))
258 usrp_basic::write_eeprom (int i2c_addr, int eeprom_offset, const std::string buf)
260 return usrp_eeprom_write (d_udh, i2c_addr, eeprom_offset, buf.data (), buf.size ());
264 usrp_basic::read_eeprom (int i2c_addr, int eeprom_offset, int len)
271 if (!usrp_eeprom_read (d_udh, i2c_addr, eeprom_offset, buf, len))
274 return std::string (buf, len);
278 usrp_basic::write_i2c (int i2c_addr, const std::string buf)
280 return usrp_i2c_write (d_udh, i2c_addr, buf.data (), buf.size ());
284 usrp_basic::read_i2c (int i2c_addr, int len)
291 if (!usrp_i2c_read (d_udh, i2c_addr, buf, len))
294 return std::string (buf, len);
298 usrp_basic::serial_number()
300 return usrp_serial_number(d_udh);
303 // ----------------------------------------------------------------
306 usrp_basic::set_adc_offset (int which_adc, int offset)
308 if (which_adc < 0 || which_adc > 3)
311 return _write_fpga_reg (FR_ADC_OFFSET_0 + which_adc, offset);
315 usrp_basic::set_dac_offset (int which_dac, int offset, int offset_pin)
317 if (which_dac < 0 || which_dac > 3)
320 int which_codec = which_dac >> 1;
321 int tx_a = (which_dac & 0x1) == 0;
322 int lo = ((offset & 0x3) << 6) | (offset_pin & 0x1);
323 int hi = (offset >> 2);
327 ok = _write_9862 (which_codec, REG_TX_A_OFFSET_LO, lo);
328 ok &= _write_9862 (which_codec, REG_TX_A_OFFSET_HI, hi);
331 ok = _write_9862 (which_codec, REG_TX_B_OFFSET_LO, lo);
332 ok &= _write_9862 (which_codec, REG_TX_B_OFFSET_HI, hi);
338 usrp_basic::set_adc_buffer_bypass (int which_adc, bool bypass)
340 if (which_adc < 0 || which_adc > 3)
343 int codec = which_adc >> 1;
344 int reg = (which_adc & 1) == 0 ? REG_RX_A : REG_RX_B;
346 unsigned char cur_rx;
347 unsigned char cur_pwr_dn;
349 // If the input buffer is bypassed, we need to power it down too.
351 bool ok = _read_9862 (codec, reg, &cur_rx);
352 ok &= _read_9862 (codec, REG_RX_PWR_DN, &cur_pwr_dn);
357 cur_rx |= RX_X_BYPASS_INPUT_BUFFER;
358 cur_pwr_dn |= ((which_adc & 1) == 0) ? RX_PWR_DN_BUF_A : RX_PWR_DN_BUF_B;
361 cur_rx &= ~RX_X_BYPASS_INPUT_BUFFER;
362 cur_pwr_dn &= ~(((which_adc & 1) == 0) ? RX_PWR_DN_BUF_A : RX_PWR_DN_BUF_B);
365 ok &= _write_9862 (codec, reg, cur_rx);
366 ok &= _write_9862 (codec, REG_RX_PWR_DN, cur_pwr_dn);
371 usrp_basic::set_dc_offset_cl_enable(int bits, int mask)
373 return _write_fpga_reg(FR_DC_OFFSET_CL_EN,
374 (d_fpga_shadows[FR_DC_OFFSET_CL_EN] & ~mask) | (bits & mask));
377 // ----------------------------------------------------------------
380 usrp_basic::_write_fpga_reg (int regno, int value)
383 fprintf (stdout, "_write_fpga_reg(%3d, 0x%08x)\n", regno, value);
387 if (regno >= 0 && regno < MAX_REGS)
388 d_fpga_shadows[regno] = value;
390 return usrp_write_fpga_reg (d_udh, regno, value);
394 usrp_basic::_write_fpga_reg_masked (int regno, int value, int mask)
396 //Only use this for registers who actually use a mask in the verilog firmware, like FR_RX_MASTER_SLAVE
397 //value is a 16 bits value and mask is a 16 bits mask
399 fprintf (stdout, "_write_fpga_reg_masked(%3d, 0x%04x,0x%04x)\n", regno, value, mask);
403 if (regno >= 0 && regno < MAX_REGS)
404 d_fpga_shadows[regno] = value;
406 return usrp_write_fpga_reg (d_udh, regno, (value & 0xffff) | ((mask & 0xffff)<<16));
411 usrp_basic::_read_fpga_reg (int regno, int *value)
413 return usrp_read_fpga_reg (d_udh, regno, value);
417 usrp_basic::_read_fpga_reg (int regno)
420 if (!_read_fpga_reg (regno, &value))
426 usrp_basic::_write_9862 (int which_codec, int regno, unsigned char value)
429 // FIXME really want to enable logging in usrp_prims:usrp_9862_write
430 fprintf(stdout, "_write_9862(codec = %d, regno = %2d, val = 0x%02x)\n", which_codec, regno, value);
434 return usrp_9862_write (d_udh, which_codec, regno, value);
439 usrp_basic::_read_9862 (int which_codec, int regno, unsigned char *value) const
441 return usrp_9862_read (d_udh, which_codec, regno, value);
445 usrp_basic::_read_9862 (int which_codec, int regno) const
448 if (!_read_9862 (which_codec, regno, &value))
454 usrp_basic::_write_spi (int optional_header, int enables, int format, std::string buf)
456 return usrp_spi_write (d_udh, optional_header, enables, format,
457 buf.data(), buf.size());
461 usrp_basic::_read_spi (int optional_header, int enables, int format, int len)
468 if (!usrp_spi_read (d_udh, optional_header, enables, format, buf, len))
471 return std::string (buf, len);
476 usrp_basic::_set_led (int which_led, bool on)
478 return usrp_set_led (d_udh, which_led, on);
482 usrp_basic::write_atr_tx_delay(int value)
484 return _write_fpga_reg(FR_ATR_TX_DELAY, value);
488 usrp_basic::write_atr_rx_delay(int value)
490 return _write_fpga_reg(FR_ATR_RX_DELAY, value);
494 * ----------------------------------------------------------------
495 * Routines to access and control daughterboard specific i/o
496 * ----------------------------------------------------------------
499 slot_id_to_oe_reg (int slot_id)
501 static int reg[4] = { FR_OE_0, FR_OE_1, FR_OE_2, FR_OE_3 };
502 assert (0 <= slot_id && slot_id < 4);
507 slot_id_to_io_reg (int slot_id)
509 static int reg[4] = { FR_IO_0, FR_IO_1, FR_IO_2, FR_IO_3 };
510 assert (0 <= slot_id && slot_id < 4);
515 slot_id_to_refclk_reg(int slot_id)
517 static int reg[4] = { FR_TX_A_REFCLK, FR_RX_A_REFCLK, FR_TX_B_REFCLK, FR_RX_B_REFCLK };
518 assert (0 <= slot_id && slot_id < 4);
523 slot_id_to_atr_mask_reg(int slot_id)
525 static int reg[4] = { FR_ATR_MASK_0, FR_ATR_MASK_1, FR_ATR_MASK_2, FR_ATR_MASK_3 };
526 assert (0 <= slot_id && slot_id < 4);
531 slot_id_to_atr_txval_reg(int slot_id)
533 static int reg[4] = { FR_ATR_TXVAL_0, FR_ATR_TXVAL_1, FR_ATR_TXVAL_2, FR_ATR_TXVAL_3 };
534 assert (0 <= slot_id && slot_id < 4);
539 slot_id_to_atr_rxval_reg(int slot_id)
541 static int reg[4] = { FR_ATR_RXVAL_0, FR_ATR_RXVAL_1, FR_ATR_RXVAL_2, FR_ATR_RXVAL_3 };
542 assert (0 <= slot_id && slot_id < 4);
547 to_slot(txrx_t txrx, int which_side)
553 return ((which_side & 0x1) << 1) | ((txrx & 0x1) == C_RX);
557 usrp_basic::common_set_pga(txrx_t txrx, int which_amp, double gain)
559 if (which_amp < 0 || which_amp > 3)
562 gain = std::min(common_pga_max(txrx),
563 std::max(common_pga_min(txrx), gain));
565 int codec = which_amp >> 1;
566 int int_gain = (int) rint((gain - common_pga_min(txrx)) / common_pga_db_per_step(txrx));
568 if (txrx == C_TX){ // 0 and 1 are same, as are 2 and 3
569 return _write_9862(codec, REG_TX_PGA, int_gain);
572 int reg = (which_amp & 1) == 0 ? REG_RX_A : REG_RX_B;
574 // read current value to get input buffer bypass flag.
575 unsigned char cur_rx;
576 if (!_read_9862(codec, reg, &cur_rx))
579 cur_rx = (cur_rx & RX_X_BYPASS_INPUT_BUFFER) | (int_gain & 0x7f);
580 return _write_9862(codec, reg, cur_rx);
585 usrp_basic::common_pga(txrx_t txrx, int which_amp) const
587 if (which_amp < 0 || which_amp > 3)
591 int codec = which_amp >> 1;
593 bool ok = _read_9862 (codec, REG_TX_PGA, &v);
597 return (pga_db_per_step() * v) + pga_min();
600 int codec = which_amp >> 1;
601 int reg = (which_amp & 1) == 0 ? REG_RX_A : REG_RX_B;
603 bool ok = _read_9862 (codec, reg, &v);
607 return (pga_db_per_step() * (v & 0x1f)) + pga_min();
612 usrp_basic::common_pga_min(txrx_t txrx) const
621 usrp_basic::common_pga_max(txrx_t txrx) const
630 usrp_basic::common_pga_db_per_step(txrx_t txrx) const
639 usrp_basic::_common_write_oe(txrx_t txrx, int which_side, int value, int mask)
641 if (! (0 <= which_side && which_side <= 1))
644 return _write_fpga_reg(slot_id_to_oe_reg(to_slot(txrx, which_side)),
645 (mask << 16) | (value & 0xffff));
649 usrp_basic::common_write_io(txrx_t txrx, int which_side, int value, int mask)
651 if (! (0 <= which_side && which_side <= 1))
654 return _write_fpga_reg(slot_id_to_io_reg(to_slot(txrx, which_side)),
655 (mask << 16) | (value & 0xffff));
659 usrp_basic::common_read_io(txrx_t txrx, int which_side, int *value)
661 if (! (0 <= which_side && which_side <= 1))
665 int reg = which_side + 1; // FIXME, *very* magic number (fix in serial_io.v)
666 bool ok = _read_fpga_reg(reg, &t);
671 *value = t & 0xffff; // FIXME, more magic
675 *value = (t >> 16) & 0xffff; // FIXME, more magic
681 usrp_basic::common_read_io(txrx_t txrx, int which_side)
684 if (!common_read_io(txrx, which_side, &value))
690 usrp_basic::common_write_refclk(txrx_t txrx, int which_side, int value)
692 if (! (0 <= which_side && which_side <= 1))
695 return _write_fpga_reg(slot_id_to_refclk_reg(to_slot(txrx, which_side)),
700 usrp_basic::common_write_atr_mask(txrx_t txrx, int which_side, int value)
702 if (! (0 <= which_side && which_side <= 1))
705 return _write_fpga_reg(slot_id_to_atr_mask_reg(to_slot(txrx, which_side)),
710 usrp_basic::common_write_atr_txval(txrx_t txrx, int which_side, int value)
712 if (! (0 <= which_side && which_side <= 1))
715 return _write_fpga_reg(slot_id_to_atr_txval_reg(to_slot(txrx, which_side)),
720 usrp_basic::common_write_atr_rxval(txrx_t txrx, int which_side, int value)
722 if (! (0 <= which_side && which_side <= 1))
725 return _write_fpga_reg(slot_id_to_atr_rxval_reg(to_slot(txrx, which_side)),
730 usrp_basic::common_write_aux_dac(txrx_t txrx, int which_side, int which_dac, int value)
732 return _write_aux_dac(to_slot(txrx, which_side), which_dac, value);
736 usrp_basic::common_read_aux_adc(txrx_t txrx, int which_side, int which_adc, int *value)
738 return _read_aux_adc(to_slot(txrx, which_side), which_adc, value);
742 usrp_basic::common_read_aux_adc(txrx_t txrx, int which_side, int which_adc)
744 return _read_aux_adc(to_slot(txrx, which_side), which_adc);
748 ////////////////////////////////////////////////////////////////
752 ////////////////////////////////////////////////////////////////
754 static unsigned char rx_init_regs[] = {
756 REG_RX_A, 0, // minimum gain = 0x00 (max gain = 0x14)
757 REG_RX_B, 0, // minimum gain = 0x00 (max gain = 0x14)
758 REG_RX_MISC, (RX_MISC_HS_DUTY_CYCLE | RX_MISC_CLK_DUTY),
759 REG_RX_IF, (RX_IF_USE_CLKOUT1
761 REG_RX_DIGITAL, (RX_DIGITAL_2_CHAN)
765 usrp_basic_rx::usrp_basic_rx (int which_board, int fusb_block_size, int fusb_nblocks,
766 const std::string fpga_filename,
767 const std::string firmware_filename
769 : usrp_basic (which_board, open_rx_interface, fpga_filename, firmware_filename),
770 d_devhandle (0), d_ephandle (0),
771 d_bytes_seen (0), d_first_read (true),
774 // initialize rx specific registers
776 if (!usrp_9862_write_many_all (d_udh, rx_init_regs, sizeof (rx_init_regs))){
777 fprintf (stderr, "usrp_basic_rx: failed to init AD9862 RX regs\n");
778 throw std::runtime_error ("usrp_basic_rx/init_9862");
782 // FIXME power down 2nd codec rx path
783 usrp_9862_write (d_udh, 1, REG_RX_PWR_DN, 0x1); // power down everything
786 // Reset the rx path and leave it disabled.
787 set_rx_enable (false);
788 usrp_set_fpga_rx_reset (d_udh, true);
789 usrp_set_fpga_rx_reset (d_udh, false);
791 set_fpga_rx_sample_rate_divisor (2); // usually correct
793 set_dc_offset_cl_enable(0xf, 0xf); // enable DC offset removal control loops
795 probe_rx_slots (false);
797 //d_db[0] = instantiate_dbs(d_dbid[0], this, 0);
798 //d_db[1] = instantiate_dbs(d_dbid[1], this, 1);
800 // check fusb buffering parameters
802 if (fusb_block_size < 0 || fusb_block_size > FUSB_BLOCK_SIZE)
803 throw std::out_of_range ("usrp_basic_rx: invalid fusb_block_size");
805 if (fusb_nblocks < 0)
806 throw std::out_of_range ("usrp_basic_rx: invalid fusb_nblocks");
808 if (fusb_block_size == 0)
809 fusb_block_size = fusb_sysconfig::default_block_size();
811 if (fusb_nblocks == 0)
812 fusb_nblocks = std::max (1, FUSB_BUFFER_SIZE / fusb_block_size);
814 d_devhandle = fusb_sysconfig::make_devhandle (d_udh, d_ctx);
815 d_ephandle = d_devhandle->make_ephandle (USRP_RX_ENDPOINT, true,
816 fusb_block_size, fusb_nblocks);
818 write_atr_mask(0, 0); // zero Rx A Auto Transmit/Receive regs
819 write_atr_txval(0, 0);
820 write_atr_rxval(0, 0);
821 write_atr_mask(1, 0); // zero Rx B Auto Transmit/Receive regs
822 write_atr_txval(1, 0);
823 write_atr_rxval(1, 0);
826 static unsigned char rx_fini_regs[] = {
827 REG_RX_PWR_DN, 0x1 // power down everything
830 usrp_basic_rx::~usrp_basic_rx ()
832 if (!set_rx_enable (false)){
833 fprintf (stderr, "usrp_basic_rx: set_fpga_rx_enable failed\n");
840 if (!usrp_9862_write_many_all (d_udh, rx_fini_regs, sizeof (rx_fini_regs))){
841 fprintf (stderr, "usrp_basic_rx: failed to fini AD9862 RX regs\n");
844 shutdown_daughterboards();
849 usrp_basic_rx::start ()
851 if (!usrp_basic::start ()) // invoke parent's method
854 // fire off reads before asserting rx_enable
856 if (!d_ephandle->start ()){
857 fprintf (stderr, "usrp_basic_rx: failed to start end point streaming");
861 if (!set_rx_enable (true)){
862 fprintf (stderr, "usrp_basic_rx: set_rx_enable failed\n");
870 usrp_basic_rx::stop ()
872 bool ok = usrp_basic::stop();
874 if (!set_rx_enable(false)){
875 fprintf (stderr, "usrp_basic_rx: set_rx_enable(false) failed\n");
879 if (!d_ephandle->stop()){
880 fprintf (stderr, "usrp_basic_rx: failed to stop end point streaming");
888 usrp_basic_rx::make (int which_board, int fusb_block_size, int fusb_nblocks,
889 const std::string fpga_filename,
890 const std::string firmware_filename)
892 usrp_basic_rx *u = 0;
895 u = new usrp_basic_rx (which_board, fusb_block_size, fusb_nblocks,
896 fpga_filename, firmware_filename);
908 usrp_basic_rx::set_fpga_rx_sample_rate_divisor (unsigned int div)
910 return _write_fpga_reg (FR_RX_SAMPLE_RATE_DIV, div - 1);
915 * \brief read data from the D/A's via the FPGA.
916 * \p len must be a multiple of 512 bytes.
918 * \returns the number of bytes read, or -1 on error.
920 * If overrun is non-NULL it will be set true iff an RX overrun is detected.
923 usrp_basic_rx::read (void *buf, int len, bool *overrun)
930 if (len < 0 || (len % 512) != 0){
931 fprintf (stderr, "usrp_basic_rx::read: invalid length = %d\n", len);
935 r = d_ephandle->read (buf, len);
940 * In many cases, the FPGA reports an rx overrun right after we
941 * enable the Rx path. If this is our first read, check for the
942 * overrun to clear the condition, then ignore the result.
944 if (0 && d_first_read){ // FIXME
945 d_first_read = false;
947 usrp_check_rx_overrun (d_udh, &bogus_overrun);
950 if (overrun != 0 && d_bytes_seen >= d_bytes_per_poll){
952 if (!usrp_check_rx_overrun (d_udh, overrun)){
953 fprintf (stderr, "usrp_basic_rx: usrp_check_rx_overrun failed\n");
961 usrp_basic_rx::set_rx_enable (bool on)
964 return usrp_set_fpga_rx_enable (d_udh, on);
967 // conditional disable, return prev state
969 usrp_basic_rx::disable_rx ()
971 bool enabled = rx_enable ();
973 set_rx_enable (false);
979 usrp_basic_rx::restore_rx (bool on)
981 if (on != rx_enable ())
986 usrp_basic_rx::probe_rx_slots (bool verbose)
988 struct usrp_dboard_eeprom eeprom;
989 static int slot_id_map[2] = { SLOT_RX_A, SLOT_RX_B };
990 static const char *slot_name[2] = { "RX d'board A", "RX d'board B" };
992 for (int i = 0; i < 2; i++){
993 int slot_id = slot_id_map [i];
995 usrp_dbeeprom_status_t s = usrp_read_dboard_eeprom (d_udh, slot_id, &eeprom);
999 d_dbid[i] = eeprom.id;
1000 msg = usrp_dbid_to_string (eeprom.id).c_str ();
1001 set_adc_offset (2*i+0, eeprom.offset[0]);
1002 set_adc_offset (2*i+1, eeprom.offset[1]);
1003 _write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | eeprom.oe);
1004 _write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
1007 case UDBE_NO_EEPROM:
1010 _write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | 0x0000);
1011 _write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
1014 case UDBE_INVALID_EEPROM:
1016 msg = "Invalid EEPROM contents";
1017 _write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | 0x0000);
1018 _write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
1028 fprintf (stderr, "%s: %s\n", slot_name[i], msg);
1034 usrp_basic_rx::set_pga (int which_amp, double gain)
1036 return common_set_pga(C_RX, which_amp, gain);
1040 usrp_basic_rx::pga(int which_amp) const
1042 return common_pga(C_RX, which_amp);
1046 usrp_basic_rx::pga_min() const
1048 return common_pga_min(C_RX);
1052 usrp_basic_rx::pga_max() const
1054 return common_pga_max(C_RX);
1058 usrp_basic_rx::pga_db_per_step() const
1060 return common_pga_db_per_step(C_RX);
1064 usrp_basic_rx::_write_oe (int which_side, int value, int mask)
1066 return _common_write_oe(C_RX, which_side, value, mask);
1070 usrp_basic_rx::write_io (int which_side, int value, int mask)
1072 return common_write_io(C_RX, which_side, value, mask);
1076 usrp_basic_rx::read_io (int which_side, int *value)
1078 return common_read_io(C_RX, which_side, value);
1082 usrp_basic_rx::read_io (int which_side)
1084 return common_read_io(C_RX, which_side);
1088 usrp_basic_rx::write_refclk(int which_side, int value)
1090 return common_write_refclk(C_RX, which_side, value);
1094 usrp_basic_rx::write_atr_mask(int which_side, int value)
1096 return common_write_atr_mask(C_RX, which_side, value);
1100 usrp_basic_rx::write_atr_txval(int which_side, int value)
1102 return common_write_atr_txval(C_RX, which_side, value);
1106 usrp_basic_rx::write_atr_rxval(int which_side, int value)
1108 return common_write_atr_rxval(C_RX, which_side, value);
1112 usrp_basic_rx::write_aux_dac (int which_side, int which_dac, int value)
1114 return common_write_aux_dac(C_RX, which_side, which_dac, value);
1118 usrp_basic_rx::read_aux_adc (int which_side, int which_adc, int *value)
1120 return common_read_aux_adc(C_RX, which_side, which_adc, value);
1124 usrp_basic_rx::read_aux_adc (int which_side, int which_adc)
1126 return common_read_aux_adc(C_RX, which_side, which_adc);
1130 usrp_basic_rx::block_size () const { return d_ephandle->block_size(); }
1132 ////////////////////////////////////////////////////////////////
1136 ////////////////////////////////////////////////////////////////
1140 // DAC input rate 64 MHz interleaved for a total input rate of 128 MHz
1141 // DAC input is latched on rising edge of CLKOUT2
1144 // coarse modulator disabled
1147 static unsigned char tx_init_regs[] = {
1149 REG_TX_A_OFFSET_LO, 0,
1150 REG_TX_A_OFFSET_HI, 0,
1151 REG_TX_B_OFFSET_LO, 0,
1152 REG_TX_B_OFFSET_HI, 0,
1153 REG_TX_A_GAIN, (TX_X_GAIN_COARSE_FULL | 0),
1154 REG_TX_B_GAIN, (TX_X_GAIN_COARSE_FULL | 0),
1155 REG_TX_PGA, 0xff, // maximum gain (0 dB)
1157 REG_TX_IF, (TX_IF_USE_CLKOUT1
1161 | TX_IF_INTERLEAVED),
1162 REG_TX_DIGITAL, (TX_DIGITAL_2_DATA_PATHS
1163 | TX_DIGITAL_INTERPOLATE_4X),
1164 REG_TX_MODULATOR, (TX_MODULATOR_DISABLE_NCO
1165 | TX_MODULATOR_COARSE_MODULATION_NONE),
1166 REG_TX_NCO_FTW_7_0, 0,
1167 REG_TX_NCO_FTW_15_8, 0,
1168 REG_TX_NCO_FTW_23_16, 0
1171 usrp_basic_tx::usrp_basic_tx (int which_board, int fusb_block_size, int fusb_nblocks,
1172 const std::string fpga_filename,
1173 const std::string firmware_filename)
1174 : usrp_basic (which_board, open_tx_interface, fpga_filename, firmware_filename),
1175 d_devhandle (0), d_ephandle (0),
1176 d_bytes_seen (0), d_first_write (true),
1179 if (!usrp_9862_write_many_all (d_udh, tx_init_regs, sizeof (tx_init_regs))){
1180 fprintf (stderr, "usrp_basic_tx: failed to init AD9862 TX regs\n");
1181 throw std::runtime_error ("usrp_basic_tx/init_9862");
1185 // FIXME power down 2nd codec tx path
1186 usrp_9862_write (d_udh, 1, REG_TX_PWR_DN,
1187 (TX_PWR_DN_TX_DIGITAL
1188 | TX_PWR_DN_TX_ANALOG_BOTH));
1191 // Reset the tx path and leave it disabled.
1192 set_tx_enable (false);
1193 usrp_set_fpga_tx_reset (d_udh, true);
1194 usrp_set_fpga_tx_reset (d_udh, false);
1196 set_fpga_tx_sample_rate_divisor (4); // we're using interp x4
1198 probe_tx_slots (false);
1200 //d_db[0] = instantiate_dbs(d_dbid[0], this, 0);
1201 //d_db[1] = instantiate_dbs(d_dbid[1], this, 1);
1203 // check fusb buffering parameters
1205 if (fusb_block_size < 0 || fusb_block_size > FUSB_BLOCK_SIZE)
1206 throw std::out_of_range ("usrp_basic_rx: invalid fusb_block_size");
1208 if (fusb_nblocks < 0)
1209 throw std::out_of_range ("usrp_basic_rx: invalid fusb_nblocks");
1211 if (fusb_block_size == 0)
1212 fusb_block_size = FUSB_BLOCK_SIZE;
1214 if (fusb_nblocks == 0)
1215 fusb_nblocks = std::max (1, FUSB_BUFFER_SIZE / fusb_block_size);
1217 d_devhandle = fusb_sysconfig::make_devhandle (d_udh, d_ctx);
1218 d_ephandle = d_devhandle->make_ephandle (USRP_TX_ENDPOINT, false,
1219 fusb_block_size, fusb_nblocks);
1221 write_atr_mask(0, 0); // zero Tx A Auto Transmit/Receive regs
1222 write_atr_txval(0, 0);
1223 write_atr_rxval(0, 0);
1224 write_atr_mask(1, 0); // zero Tx B Auto Transmit/Receive regs
1225 write_atr_txval(1, 0);
1226 write_atr_rxval(1, 0);
1230 static unsigned char tx_fini_regs[] = {
1231 REG_TX_PWR_DN, (TX_PWR_DN_TX_DIGITAL
1232 | TX_PWR_DN_TX_ANALOG_BOTH),
1233 REG_TX_MODULATOR, (TX_MODULATOR_DISABLE_NCO
1234 | TX_MODULATOR_COARSE_MODULATION_NONE)
1237 usrp_basic_tx::~usrp_basic_tx ()
1239 d_ephandle->stop ();
1243 if (!usrp_9862_write_many_all (d_udh, tx_fini_regs, sizeof (tx_fini_regs))){
1244 fprintf (stderr, "usrp_basic_tx: failed to fini AD9862 TX regs\n");
1247 shutdown_daughterboards();
1251 usrp_basic_tx::start ()
1253 if (!usrp_basic::start ())
1256 if (!set_tx_enable (true)){
1257 fprintf (stderr, "usrp_basic_tx: set_tx_enable failed\n");
1261 if (!d_ephandle->start ()){
1262 fprintf (stderr, "usrp_basic_tx: failed to start end point streaming");
1270 usrp_basic_tx::stop ()
1272 bool ok = usrp_basic::stop ();
1274 if (!d_ephandle->stop ()){
1275 fprintf (stderr, "usrp_basic_tx: failed to stop end point streaming");
1279 if (!set_tx_enable (false)){
1280 fprintf (stderr, "usrp_basic_tx: set_tx_enable(false) failed\n");
1288 usrp_basic_tx::make (int which_board, int fusb_block_size, int fusb_nblocks,
1289 const std::string fpga_filename,
1290 const std::string firmware_filename)
1292 usrp_basic_tx *u = 0;
1295 u = new usrp_basic_tx (which_board, fusb_block_size, fusb_nblocks,
1296 fpga_filename, firmware_filename);
1308 usrp_basic_tx::set_fpga_tx_sample_rate_divisor (unsigned int div)
1310 return _write_fpga_reg (FR_TX_SAMPLE_RATE_DIV, div - 1);
1314 * \brief Write data to the A/D's via the FPGA.
1316 * \p len must be a multiple of 512 bytes.
1317 * \returns number of bytes written or -1 on error.
1319 * if \p underrun is non-NULL, it will be set to true iff
1320 * a transmit underrun condition is detected.
1323 usrp_basic_tx::write (const void *buf, int len, bool *underrun)
1330 if (len < 0 || (len % 512) != 0){
1331 fprintf (stderr, "usrp_basic_tx::write: invalid length = %d\n", len);
1335 r = d_ephandle->write (buf, len);
1340 * In many cases, the FPGA reports an tx underrun right after we
1341 * enable the Tx path. If this is our first write, check for the
1342 * underrun to clear the condition, then ignore the result.
1344 if (d_first_write && d_bytes_seen >= 4 * FUSB_BLOCK_SIZE){
1345 d_first_write = false;
1346 bool bogus_underrun;
1347 usrp_check_tx_underrun (d_udh, &bogus_underrun);
1350 if (underrun != 0 && d_bytes_seen >= d_bytes_per_poll){
1352 if (!usrp_check_tx_underrun (d_udh, underrun)){
1353 fprintf (stderr, "usrp_basic_tx: usrp_check_tx_underrun failed\n");
1361 usrp_basic_tx::wait_for_completion ()
1363 d_ephandle->wait_for_completion ();
1367 usrp_basic_tx::set_tx_enable (bool on)
1370 // fprintf (stderr, "set_tx_enable %d\n", on);
1371 return usrp_set_fpga_tx_enable (d_udh, on);
1374 // conditional disable, return prev state
1376 usrp_basic_tx::disable_tx ()
1378 bool enabled = tx_enable ();
1380 set_tx_enable (false);
1386 usrp_basic_tx::restore_tx (bool on)
1388 if (on != tx_enable ())
1393 usrp_basic_tx::probe_tx_slots (bool verbose)
1395 struct usrp_dboard_eeprom eeprom;
1396 static int slot_id_map[2] = { SLOT_TX_A, SLOT_TX_B };
1397 static const char *slot_name[2] = { "TX d'board A", "TX d'board B" };
1399 for (int i = 0; i < 2; i++){
1400 int slot_id = slot_id_map [i];
1401 const char *msg = 0;
1402 usrp_dbeeprom_status_t s = usrp_read_dboard_eeprom (d_udh, slot_id, &eeprom);
1406 d_dbid[i] = eeprom.id;
1407 msg = usrp_dbid_to_string (eeprom.id).c_str ();
1408 // FIXME, figure out interpretation of dc offset for TX d'boards
1409 // offset = (eeprom.offset[1] << 16) | (eeprom.offset[0] & 0xffff);
1410 _write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | eeprom.oe);
1411 _write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
1414 case UDBE_NO_EEPROM:
1417 _write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | 0x0000);
1418 _write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
1421 case UDBE_INVALID_EEPROM:
1423 msg = "Invalid EEPROM contents";
1424 _write_fpga_reg (slot_id_to_oe_reg(slot_id), (0xffff << 16) | 0x0000);
1425 _write_fpga_reg (slot_id_to_io_reg(slot_id), (0xffff << 16) | 0x0000);
1435 fprintf (stderr, "%s: %s\n", slot_name[i], msg);
1441 usrp_basic_tx::set_pga (int which_amp, double gain)
1443 return common_set_pga(C_TX, which_amp, gain);
1447 usrp_basic_tx::pga (int which_amp) const
1449 return common_pga(C_TX, which_amp);
1453 usrp_basic_tx::pga_min() const
1455 return common_pga_min(C_TX);
1459 usrp_basic_tx::pga_max() const
1461 return common_pga_max(C_TX);
1465 usrp_basic_tx::pga_db_per_step() const
1467 return common_pga_db_per_step(C_TX);
1471 usrp_basic_tx::_write_oe (int which_side, int value, int mask)
1473 return _common_write_oe(C_TX, which_side, value, mask);
1477 usrp_basic_tx::write_io (int which_side, int value, int mask)
1479 return common_write_io(C_TX, which_side, value, mask);
1483 usrp_basic_tx::read_io (int which_side, int *value)
1485 return common_read_io(C_TX, which_side, value);
1489 usrp_basic_tx::read_io (int which_side)
1491 return common_read_io(C_TX, which_side);
1495 usrp_basic_tx::write_refclk(int which_side, int value)
1497 return common_write_refclk(C_TX, which_side, value);
1501 usrp_basic_tx::write_atr_mask(int which_side, int value)
1503 return common_write_atr_mask(C_TX, which_side, value);
1507 usrp_basic_tx::write_atr_txval(int which_side, int value)
1509 return common_write_atr_txval(C_TX, which_side, value);
1513 usrp_basic_tx::write_atr_rxval(int which_side, int value)
1515 return common_write_atr_rxval(C_TX, which_side, value);
1519 usrp_basic_tx::write_aux_dac (int which_side, int which_dac, int value)
1521 return common_write_aux_dac(C_TX, which_side, which_dac, value);
1525 usrp_basic_tx::read_aux_adc (int which_side, int which_adc, int *value)
1527 return common_read_aux_adc(C_TX, which_side, which_adc, value);
1531 usrp_basic_tx::read_aux_adc (int which_side, int which_adc)
1533 return common_read_aux_adc(C_TX, which_side, which_adc);
1537 usrp_basic_tx::block_size () const { return d_ephandle->block_size(); }