3 * Copyright 2003,2004,2008 Free Software Foundation, Inc.
5 * This file is part of GNU Radio
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8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 3, or (at your option)
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13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with GNU Radio; see the file COPYING. If not, write to
19 * the Free Software Foundation, Inc., 51 Franklin Street,
20 * Boston, MA 02110-1301, USA.
24 * ----------------------------------------------------------------------
25 * Mid level interface to the Universal Software Radio Peripheral (Rev 1)
27 * These classes implement the basic functionality for talking to the
28 * USRP. They try to be as independent of the signal processing code
29 * in FPGA as possible. They implement access to the low level
30 * peripherals on the board, provide a common way for reading and
31 * writing registers in the FPGA, and provide the high speed interface
32 * to streaming data across the USB.
34 * It is expected that subclasses will be derived that provide
35 * access to the functionality to a particular FPGA configuration.
36 * ----------------------------------------------------------------------
39 #ifndef INCLUDED_USRP_BASIC_H
40 #define INCLUDED_USRP_BASIC_H
43 #include <usrp_slots.h>
46 #include <boost/utility.hpp>
47 #include <usrp_subdev_spec.h>
49 struct usb_dev_handle;
59 * \brief abstract base class for usrp operations
62 class usrp_basic : boost::noncopyable
65 void shutdown_daughterboards();
68 struct usb_dev_handle *d_udh;
69 int d_usb_data_rate; // bytes/sec
70 int d_bytes_per_poll; // how often to poll for overruns
72 long d_fpga_master_clock_freq;
74 static const int MAX_REGS = 128;
75 unsigned int d_fpga_shadows[MAX_REGS];
77 int d_dbid[2]; // daughterboard ID's (side A, side B)
80 * Shared pointers to subclasses of db_base.
82 * The outer vector is of length 2 (0 = side A, 1 = side B). The
83 * inner vectors are of length 1, 2 or 3 depending on the number of
84 * subdevices implemented by the daugherboard. At this time, only
85 * the Basic Rx and LF Rx implement more than 1 subdevice.
87 std::vector< std::vector<db_base_sptr> > d_db;
89 //! One time call, made only only from usrp_standard_*::make after shared_ptr is created.
90 void init_db(usrp_basic_sptr u);
93 usrp_basic (int which_board,
94 struct usb_dev_handle *open_interface (struct usb_device *dev),
95 const std::string fpga_filename = "",
96 const std::string firmware_filename = "");
99 * \brief advise usrp_basic of usb data rate (bytes/sec)
101 * N.B., this doesn't tweak any hardware. Derived classes
102 * should call this to inform us of the data rate whenever it's
103 * first set or if it changes.
105 * \param usb_data_rate bytes/sec
107 void set_usb_data_rate (int usb_data_rate);
110 * \brief Write auxiliary digital to analog converter.
112 * \param slot Which Tx or Rx slot to write.
113 * N.B., SLOT_TX_A and SLOT_RX_A share the same AUX DAC's.
114 * SLOT_TX_B and SLOT_RX_B share the same AUX DAC's.
115 * \param which_dac [0,3] RX slots must use only 0 and 1. TX slots must use only 2 and 3.
116 * \param value [0,4095]
117 * \returns true iff successful
119 bool _write_aux_dac (int slot, int which_dac, int value);
122 * \brief Read auxiliary analog to digital converter.
124 * \param slot 2-bit slot number. E.g., SLOT_TX_A
125 * \param which_adc [0,1]
126 * \param value return 12-bit value [0,4095]
127 * \returns true iff successful
129 bool _read_aux_adc (int slot, int which_adc, int *value);
132 * \brief Read auxiliary analog to digital converter.
134 * \param slot 2-bit slot number. E.g., SLOT_TX_A
135 * \param which_adc [0,1]
136 * \returns value in the range [0,4095] if successful, else READ_FAILED.
138 int _read_aux_adc (int slot, int which_adc);
142 virtual ~usrp_basic ();
146 * Return a vector of vectors that contain shared pointers
147 * to the daughterboard instance(s) associated with the specified side.
149 * It is an error to use the returned objects after the usrp_basic
150 * object has been destroyed.
152 std::vector<std::vector<db_base_sptr> > db() const { return d_db; }
155 * Return a vector of size >= 1 that contains shared pointers
156 * to the daughterboard instance(s) associated with the specified side.
158 * \param which_side [0,1] which daughterboard
160 * It is an error to use the returned objects after the usrp_basic
161 * object has been destroyed.
163 std::vector<db_base_sptr> db(int which_side);
166 * \brief is the subdev_spec valid?
168 bool is_valid(const usrp_subdev_spec &ss);
171 * \brief given a subdev_spec, return the corresponding daughterboard object.
172 * \throws std::invalid_ argument if ss is invalid.
174 * \param ss specifies the side and subdevice
176 db_base_sptr selected_subdev(const usrp_subdev_spec &ss);
179 * \brief return frequency of master oscillator on USRP
181 long fpga_master_clock_freq () const { return d_fpga_master_clock_freq; }
184 * Tell API that the master oscillator on the USRP is operating at a non-standard
185 * fixed frequency. This is only needed for custom USRP hardware modified to
186 * operate at a different frequency from the default factory configuration. This
187 * function must be called prior to any other API function.
188 * \param master_clock USRP2 FPGA master clock frequency in Hz (10..64 MHz)
190 void set_fpga_master_clock_freq (long master_clock) { d_fpga_master_clock_freq = master_clock; }
193 * \returns usb data rate in bytes/sec
195 int usb_data_rate () const { return d_usb_data_rate; }
197 void set_verbose (bool on) { d_verbose = on; }
199 //! magic value used on alternate register read interfaces
200 static const int READ_FAILED = -99999;
203 * \brief Write EEPROM on motherboard or any daughterboard.
204 * \param i2c_addr I2C bus address of EEPROM
205 * \param eeprom_offset byte offset in EEPROM to begin writing
206 * \param buf the data to write
207 * \returns true iff sucessful
209 bool write_eeprom (int i2c_addr, int eeprom_offset, const std::string buf);
212 * \brief Read EEPROM on motherboard or any daughterboard.
213 * \param i2c_addr I2C bus address of EEPROM
214 * \param eeprom_offset byte offset in EEPROM to begin reading
215 * \param len number of bytes to read
216 * \returns the data read if successful, else a zero length string.
218 std::string read_eeprom (int i2c_addr, int eeprom_offset, int len);
221 * \brief Write to I2C peripheral
222 * \param i2c_addr I2C bus address (7-bits)
223 * \param buf the data to write
224 * \returns true iff successful
225 * Writes are limited to a maximum of of 64 bytes.
227 bool write_i2c (int i2c_addr, const std::string buf);
230 * \brief Read from I2C peripheral
231 * \param i2c_addr I2C bus address (7-bits)
232 * \param len number of bytes to read
233 * \returns the data read if successful, else a zero length string.
234 * Reads are limited to a maximum of 64 bytes.
236 std::string read_i2c (int i2c_addr, int len);
239 * \brief Set ADC offset correction
240 * \param which_adc which ADC[0,3]: 0 = RX_A I, 1 = RX_A Q...
241 * \param offset 16-bit value to subtract from raw ADC input.
243 bool set_adc_offset (int which_adc, int offset);
246 * \brief Set DAC offset correction
247 * \param which_dac which DAC[0,3]: 0 = TX_A I, 1 = TX_A Q...
248 * \param offset 10-bit offset value (ambiguous format: See AD9862 datasheet).
249 * \param offset_pin 1-bit value. If 0 offset applied to -ve differential pin;
250 * If 1 offset applied to +ve differential pin.
252 bool set_dac_offset (int which_dac, int offset, int offset_pin);
255 * \brief Control ADC input buffer
256 * \param which_adc which ADC[0,3]
257 * \param bypass if non-zero, bypass input buffer and connect input
258 * directly to switched cap SHA input of RxPGA.
260 bool set_adc_buffer_bypass (int which_adc, bool bypass);
263 * \brief Enable/disable automatic DC offset removal control loop in FPGA
265 * \param bits which control loops to enable
266 * \param mask which \p bits to pay attention to
268 * If the corresponding bit is set, enable the automatic DC
269 * offset correction control loop.
272 * The 4 low bits are significant:
280 * By default the control loop is enabled on all ADC's.
282 bool set_dc_offset_cl_enable(int bits, int mask);
285 * \brief return the usrp's serial number.
287 * \returns non-zero length string iff successful.
289 std::string serial_number();
292 * \brief Return daughterboard ID for given side [0,1].
294 * \param which_side [0,1] which daughterboard
296 * \return daughterboard id >= 0 if successful
297 * \return -1 if no daugherboard
298 * \return -2 if invalid EEPROM on daughterboard
300 virtual int daughterboard_id (int which_side) const = 0;
303 * \brief Clock ticks to delay rising of T/R signal
304 * \sa write_atr_mask, write_atr_txval, write_atr_rxval
306 bool write_atr_tx_delay(int value);
309 * \brief Clock ticks to delay falling edge of T/R signal
310 * \sa write_atr_mask, write_atr_txval, write_atr_rxval
312 bool write_atr_rx_delay(int value);
315 \f // ================================================================
316 // Routines to access and control daughterboard specific i/o
318 // Those with a common_ prefix access either the Tx or Rx side depending
319 // on the txrx parameter. Those without the common_ prefix are virtual
320 // and are overriden in usrp_basic_rx and usrp_basic_tx to access the
321 // the Rx or Tx sides automatically. We provide the common_ versions
322 // for those daughterboards such as the WBX and XCVR2450 that share
323 // h/w resources (such as the LO) between the Tx and Rx sides.
325 // ----------------------------------------------------------------
326 // BEGIN common_ daughterboard control functions
329 * \brief Set Programmable Gain Amplifier(PGA)
331 * \param txrx Tx or Rx?
332 * \param which_amp which amp [0,3]
333 * \param gain_in_db gain value(linear in dB)
335 * gain is rounded to closest setting supported by hardware.
337 * \returns true iff sucessful.
339 * \sa pga_min(), pga_max(), pga_db_per_step()
341 bool common_set_pga(txrx_t txrx, int which_amp, double gain_in_db);
344 * \brief Return programmable gain amplifier gain setting in dB.
346 * \param txrx Tx or Rx?
347 * \param which_amp which amp [0,3]
349 double common_pga(txrx_t txrx, int which_amp) const;
352 * \brief Return minimum legal PGA gain in dB.
353 * \param txrx Tx or Rx?
355 double common_pga_min(txrx_t txrx) const;
358 * \brief Return maximum legal PGA gain in dB.
359 * \param txrx Tx or Rx?
361 double common_pga_max(txrx_t txrx) const;
364 * \brief Return hardware step size of PGA(linear in dB).
365 * \param txrx Tx or Rx?
367 double common_pga_db_per_step(txrx_t txrx) const;
370 * \brief Write direction register(output enables) for pins that go to daughterboard.
372 * \param txrx Tx or Rx?
373 * \param which_side [0,1] which size
374 * \param value value to write into register
375 * \param mask which bits of value to write into reg
377 * Each d'board has 16-bits of general purpose i/o.
378 * Setting the bit makes it an output from the FPGA to the d'board.
380 * This register is initialized based on a value stored in the
381 * d'board EEPROM. In general, you shouldn't be using this routine
382 * without a very good reason. Using this method incorrectly will
383 * kill your USRP motherboard and/or daughterboard.
385 bool _common_write_oe(txrx_t txrx, int which_side, int value, int mask);
388 * \brief Write daughterboard i/o pin value
390 * \param txrx Tx or Rx?
391 * \param which_side [0,1] which d'board
392 * \param value value to write into register
393 * \param mask which bits of value to write into reg
395 bool common_write_io(txrx_t txrx, int which_side, int value, int mask);
398 * \brief Read daughterboard i/o pin value
400 * \param txrx Tx or Rx?
401 * \param which_side [0,1] which d'board
402 * \param value output
404 bool common_read_io(txrx_t txrx, int which_side, int *value);
407 * \brief Read daughterboard i/o pin value
409 * \param txrx Tx or Rx?
410 * \param which_side [0,1] which d'board
411 * \returns register value if successful, else READ_FAILED
413 int common_read_io(txrx_t txrx, int which_side);
416 * \brief Write daughterboard refclk config register
418 * \param txrx Tx or Rx?
419 * \param which_side [0,1] which d'board
420 * \param value value to write into register, see below
423 * Control whether a reference clock is sent to the daughterboards,
424 * and what frequency. The refclk is sent on d'board i/o pin 0.
427 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
428 * +-----------------------------------------------+-+------------+
429 * | Reserved (Must be zero) |E| DIVISOR |
430 * +-----------------------------------------------+-+------------+
432 * Bit 7 -- 1 turns on refclk, 0 allows IO use
433 * Bits 6:0 Divider value
436 bool common_write_refclk(txrx_t txrx, int which_side, int value);
439 * \brief Automatic Transmit/Receive switching
442 * If automatic transmit/receive (ATR) switching is enabled in the
443 * FR_ATR_CTL register, the presence or absence of data in the FPGA
444 * transmit fifo selects between two sets of values for each of the 4
445 * banks of daughterboard i/o pins.
447 * Each daughterboard slot has 3 16-bit registers associated with it:
448 * FR_ATR_MASK_*, FR_ATR_TXVAL_* and FR_ATR_RXVAL_*
450 * FR_ATR_MASK_{0,1,2,3}:
452 * These registers determine which of the daugherboard i/o pins are
453 * affected by ATR switching. If a bit in the mask is set, the
454 * corresponding i/o bit is controlled by ATR, else it's output
455 * value comes from the normal i/o pin output register:
458 * FR_ATR_TXVAL_{0,1,2,3}:
459 * FR_ATR_RXVAL_{0,1,2,3}:
461 * If the Tx fifo contains data, then the bits from TXVAL that are
462 * selected by MASK are output. Otherwise, the bits from RXVAL that
463 * are selected by MASK are output.
466 bool common_write_atr_mask(txrx_t txrx, int which_side, int value);
467 bool common_write_atr_txval(txrx_t txrx, int which_side, int value);
468 bool common_write_atr_rxval(txrx_t txrx, int which_side, int value);
471 * \brief Write auxiliary digital to analog converter.
473 * \param txrx Tx or Rx?
474 * \param which_side [0,1] which d'board
475 * N.B., SLOT_TX_A and SLOT_RX_A share the same AUX DAC's.
476 * SLOT_TX_B and SLOT_RX_B share the same AUX DAC's.
477 * \param which_dac [2,3] TX slots must use only 2 and 3.
478 * \param value [0,4095]
479 * \returns true iff successful
481 bool common_write_aux_dac(txrx_t txrx, int which_side, int which_dac, int value);
484 * \brief Read auxiliary analog to digital converter.
486 * \param txrx Tx or Rx?
487 * \param which_side [0,1] which d'board
488 * \param which_adc [0,1]
489 * \param value return 12-bit value [0,4095]
490 * \returns true iff successful
492 bool common_read_aux_adc(txrx_t txrx, int which_side, int which_adc, int *value);
495 * \brief Read auxiliary analog to digital converter.
497 * \param txrx Tx or Rx?
498 * \param which_side [0,1] which d'board
499 * \param which_adc [0,1]
500 * \returns value in the range [0,4095] if successful, else READ_FAILED.
502 int common_read_aux_adc(txrx_t txrx, int which_side, int which_adc);
504 // END common_ daughterboard control functions
\f
505 // ----------------------------------------------------------------
506 // BEGIN virtual daughterboard control functions
509 * \brief Set Programmable Gain Amplifier (PGA)
511 * \param which_amp which amp [0,3]
512 * \param gain_in_db gain value (linear in dB)
514 * gain is rounded to closest setting supported by hardware.
516 * \returns true iff sucessful.
518 * \sa pga_min(), pga_max(), pga_db_per_step()
520 virtual bool set_pga (int which_amp, double gain_in_db) = 0;
523 * \brief Return programmable gain amplifier gain setting in dB.
525 * \param which_amp which amp [0,3]
527 virtual double pga (int which_amp) const = 0;
530 * \brief Return minimum legal PGA gain in dB.
532 virtual double pga_min () const = 0;
535 * \brief Return maximum legal PGA gain in dB.
537 virtual double pga_max () const = 0;
540 * \brief Return hardware step size of PGA (linear in dB).
542 virtual double pga_db_per_step () const = 0;
545 * \brief Write direction register (output enables) for pins that go to daughterboard.
547 * \param which_side [0,1] which size
548 * \param value value to write into register
549 * \param mask which bits of value to write into reg
551 * Each d'board has 16-bits of general purpose i/o.
552 * Setting the bit makes it an output from the FPGA to the d'board.
554 * This register is initialized based on a value stored in the
555 * d'board EEPROM. In general, you shouldn't be using this routine
556 * without a very good reason. Using this method incorrectly will
557 * kill your USRP motherboard and/or daughterboard.
559 virtual bool _write_oe (int which_side, int value, int mask) = 0;
562 * \brief Write daughterboard i/o pin value
564 * \param which_side [0,1] which d'board
565 * \param value value to write into register
566 * \param mask which bits of value to write into reg
568 virtual bool write_io (int which_side, int value, int mask) = 0;
571 * \brief Read daughterboard i/o pin value
573 * \param which_side [0,1] which d'board
574 * \param value output
576 virtual bool read_io (int which_side, int *value) = 0;
579 * \brief Read daughterboard i/o pin value
581 * \param which_side [0,1] which d'board
582 * \returns register value if successful, else READ_FAILED
584 virtual int read_io (int which_side) = 0;
587 * \brief Write daughterboard refclk config register
589 * \param which_side [0,1] which d'board
590 * \param value value to write into register, see below
593 * Control whether a reference clock is sent to the daughterboards,
594 * and what frequency. The refclk is sent on d'board i/o pin 0.
597 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
598 * +-----------------------------------------------+-+------------+
599 * | Reserved (Must be zero) |E| DIVISOR |
600 * +-----------------------------------------------+-+------------+
602 * Bit 7 -- 1 turns on refclk, 0 allows IO use
603 * Bits 6:0 Divider value
606 virtual bool write_refclk(int which_side, int value) = 0;
608 virtual bool write_atr_mask(int which_side, int value) = 0;
609 virtual bool write_atr_txval(int which_side, int value) = 0;
610 virtual bool write_atr_rxval(int which_side, int value) = 0;
613 * \brief Write auxiliary digital to analog converter.
615 * \param which_side [0,1] which d'board
616 * N.B., SLOT_TX_A and SLOT_RX_A share the same AUX DAC's.
617 * SLOT_TX_B and SLOT_RX_B share the same AUX DAC's.
618 * \param which_dac [2,3] TX slots must use only 2 and 3.
619 * \param value [0,4095]
620 * \returns true iff successful
622 virtual bool write_aux_dac (int which_side, int which_dac, int value) = 0;
625 * \brief Read auxiliary analog to digital converter.
627 * \param which_side [0,1] which d'board
628 * \param which_adc [0,1]
629 * \param value return 12-bit value [0,4095]
630 * \returns true iff successful
632 virtual bool read_aux_adc (int which_side, int which_adc, int *value) = 0;
635 * \brief Read auxiliary analog to digital converter.
637 * \param which_side [0,1] which d'board
638 * \param which_adc [0,1]
639 * \returns value in the range [0,4095] if successful, else READ_FAILED.
641 virtual int read_aux_adc (int which_side, int which_adc) = 0;
644 * \brief returns current fusb block size
646 virtual int block_size() const = 0;
649 * \brief returns A/D or D/A converter rate in Hz
651 virtual long converter_rate() const = 0;
653 // END virtual daughterboard control functions
\f
655 // ----------------------------------------------------------------
656 // Low level implementation routines.
657 // You probably shouldn't be using these...
660 bool _set_led (int which_led, bool on);
663 * \brief Write FPGA register.
664 * \param regno 7-bit register number
665 * \param value 32-bit value
666 * \returns true iff successful
668 bool _write_fpga_reg (int regno, int value); //< 7-bit regno, 32-bit value
671 * \brief Read FPGA register.
672 * \param regno 7-bit register number
673 * \param value 32-bit value
674 * \returns true iff successful
676 bool _read_fpga_reg (int regno, int *value); //< 7-bit regno, 32-bit value
679 * \brief Read FPGA register.
680 * \param regno 7-bit register number
681 * \returns register value if successful, else READ_FAILED
683 int _read_fpga_reg (int regno);
686 * \brief Write FPGA register with mask.
687 * \param regno 7-bit register number
688 * \param value 16-bit value
689 * \param mask 16-bit value
690 * \returns true if successful
691 * Only use this for registers who actually implement a mask in the verilog firmware, like FR_RX_MASTER_SLAVE
693 bool _write_fpga_reg_masked (int regno, int value, int mask);
696 * \brief Write AD9862 register.
697 * \param which_codec 0 or 1
698 * \param regno 6-bit register number
699 * \param value 8-bit value
700 * \returns true iff successful
702 bool _write_9862 (int which_codec, int regno, unsigned char value);
705 * \brief Read AD9862 register.
706 * \param which_codec 0 or 1
707 * \param regno 6-bit register number
708 * \param value 8-bit value
709 * \returns true iff successful
711 bool _read_9862 (int which_codec, int regno, unsigned char *value) const;
714 * \brief Read AD9862 register.
715 * \param which_codec 0 or 1
716 * \param regno 6-bit register number
717 * \returns register value if successful, else READ_FAILED
719 int _read_9862 (int which_codec, int regno) const;
722 * \brief Write data to SPI bus peripheral.
724 * \param optional_header 0,1 or 2 bytes to write before buf.
725 * \param enables bitmask of peripherals to write. See usrp_spi_defs.h
726 * \param format transaction format. See usrp_spi_defs.h SPI_FMT_*
727 * \param buf the data to write
728 * \returns true iff successful
729 * Writes are limited to a maximum of 64 bytes.
731 * If \p format specifies that optional_header bytes are present, they are
732 * written to the peripheral immediately prior to writing \p buf.
734 bool _write_spi (int optional_header, int enables, int format, std::string buf);
737 * \brief Read data from SPI bus peripheral.
739 * \param optional_header 0,1 or 2 bytes to write before buf.
740 * \param enables bitmask of peripheral to read. See usrp_spi_defs.h
741 * \param format transaction format. See usrp_spi_defs.h SPI_FMT_*
742 * \param len number of bytes to read. Must be in [0,64].
743 * \returns the data read if sucessful, else a zero length string.
745 * Reads are limited to a maximum of 64 bytes.
747 * If \p format specifies that optional_header bytes are present, they
748 * are written to the peripheral first. Then \p len bytes are read from
749 * the peripheral and returned.
751 std::string _read_spi (int optional_header, int enables, int format, int len);
754 * \brief Start data transfers.
755 * Called in base class to derived class order.
760 * \brief Stop data transfers.
761 * Called in base class to derived class order.
767 * \brief class for accessing the receive side of the USRP
770 class usrp_basic_rx : public usrp_basic
773 fusb_devhandle *d_devhandle;
774 fusb_ephandle *d_ephandle;
775 int d_bytes_seen; // how many bytes we've seen
781 * \param which_board Which USRP board on usb (not particularly useful; use 0)
782 * \param fusb_block_size fast usb xfer block size. Must be a multiple of 512.
783 * Use zero for a reasonable default.
784 * \param fusb_nblocks number of fast usb URBs to allocate. Use zero for a reasonable default.
785 * \param fpga_filename name of the rbf file to load
786 * \param firmware_filename name of ihx file to load
788 usrp_basic_rx (int which_board,
789 int fusb_block_size=0,
791 const std::string fpga_filename = "",
792 const std::string firmware_filename = ""
793 ); // throws if trouble
795 bool set_rx_enable (bool on);
796 bool rx_enable () const { return d_rx_enable; }
798 bool disable_rx (); // conditional disable, return prev state
799 void restore_rx (bool on); // conditional set
801 void probe_rx_slots (bool verbose);
807 * \brief invokes constructor, returns instance or 0 if trouble
809 * \param which_board Which USRP board on usb (not particularly useful; use 0)
810 * \param fusb_block_size fast usb xfer block size. Must be a multiple of 512.
811 * Use zero for a reasonable default.
812 * \param fusb_nblocks number of fast usb URBs to allocate. Use zero for a reasonable default.
813 * \param fpga_filename name of file that contains image to load into FPGA
814 * \param firmware_filename name of file that contains image to load into FX2
816 static usrp_basic_rx *make (int which_board,
817 int fusb_block_size=0,
819 const std::string fpga_filename = "",
820 const std::string firmware_filename = ""
824 * \brief tell the fpga the rate rx samples are coming from the A/D's
826 * div = fpga_master_clock_freq () / sample_rate
828 * sample_rate is determined by a myriad of registers
829 * in the 9862. That's why you have to tell us, so
830 * we can tell the fpga.
832 bool set_fpga_rx_sample_rate_divisor (unsigned int div);
835 * \brief read data from the D/A's via the FPGA.
836 * \p len must be a multiple of 512 bytes.
838 * \returns the number of bytes read, or -1 on error.
840 * If overrun is non-NULL it will be set true iff an RX overrun is detected.
842 int read (void *buf, int len, bool *overrun);
845 //! sampling rate of A/D converter
846 virtual long converter_rate() const { return fpga_master_clock_freq(); } // 64M
847 long adc_rate() const { return converter_rate(); }
848 int daughterboard_id (int which_side) const { return d_dbid[which_side & 0x1]; }
850 bool set_pga (int which_amp, double gain_in_db);
851 double pga (int which_amp) const;
852 double pga_min () const;
853 double pga_max () const;
854 double pga_db_per_step () const;
856 bool _write_oe (int which_side, int value, int mask);
857 bool write_io (int which_side, int value, int mask);
858 bool read_io (int which_side, int *value);
859 int read_io (int which_side);
860 bool write_refclk(int which_side, int value);
861 bool write_atr_mask(int which_side, int value);
862 bool write_atr_txval(int which_side, int value);
863 bool write_atr_rxval(int which_side, int value);
865 bool write_aux_dac (int which_side, int which_dac, int value);
866 bool read_aux_adc (int which_side, int which_adc, int *value);
867 int read_aux_adc (int which_side, int which_adc);
869 int block_size() const;
871 // called in base class to derived class order
877 * \brief class for accessing the transmit side of the USRP
880 class usrp_basic_tx : public usrp_basic
883 fusb_devhandle *d_devhandle;
884 fusb_ephandle *d_ephandle;
885 int d_bytes_seen; // how many bytes we've seen
891 * \param which_board Which USRP board on usb (not particularly useful; use 0)
892 * \param fusb_block_size fast usb xfer block size. Must be a multiple of 512.
893 * Use zero for a reasonable default.
894 * \param fusb_nblocks number of fast usb URBs to allocate. Use zero for a reasonable default.
895 * \param fpga_filename name of file that contains image to load into FPGA
896 * \param firmware_filename name of file that contains image to load into FX2
898 usrp_basic_tx (int which_board,
899 int fusb_block_size=0,
901 const std::string fpga_filename = "",
902 const std::string firmware_filename = ""
903 ); // throws if trouble
905 bool set_tx_enable (bool on);
906 bool tx_enable () const { return d_tx_enable; }
908 bool disable_tx (); // conditional disable, return prev state
909 void restore_tx (bool on); // conditional set
911 void probe_tx_slots (bool verbose);
918 * \brief invokes constructor, returns instance or 0 if trouble
920 * \param which_board Which USRP board on usb (not particularly useful; use 0)
921 * \param fusb_block_size fast usb xfer block size. Must be a multiple of 512.
922 * Use zero for a reasonable default.
923 * \param fusb_nblocks number of fast usb URBs to allocate. Use zero for a reasonable default.
924 * \param fpga_filename name of file that contains image to load into FPGA
925 * \param firmware_filename name of file that contains image to load into FX2
927 static usrp_basic_tx *make (int which_board, int fusb_block_size=0, int fusb_nblocks=0,
928 const std::string fpga_filename = "",
929 const std::string firmware_filename = ""
933 * \brief tell the fpga the rate tx samples are going to the D/A's
935 * div = fpga_master_clock_freq () * 2
937 * sample_rate is determined by a myriad of registers
938 * in the 9862. That's why you have to tell us, so
939 * we can tell the fpga.
941 bool set_fpga_tx_sample_rate_divisor (unsigned int div);
944 * \brief Write data to the A/D's via the FPGA.
946 * \p len must be a multiple of 512 bytes.
947 * \returns number of bytes written or -1 on error.
949 * if \p underrun is non-NULL, it will be set to true iff
950 * a transmit underrun condition is detected.
952 int write (const void *buf, int len, bool *underrun);
955 * Block until all outstanding writes have completed.
956 * This is typically used to assist with benchmarking
958 void wait_for_completion ();
960 //! sampling rate of D/A converter
961 virtual long converter_rate() const { return fpga_master_clock_freq () * 2; } // 128M
962 long dac_rate() const { return converter_rate(); }
963 int daughterboard_id (int which_side) const { return d_dbid[which_side & 0x1]; }
965 bool set_pga (int which_amp, double gain_in_db);
966 double pga (int which_amp) const;
967 double pga_min () const;
968 double pga_max () const;
969 double pga_db_per_step () const;
971 bool _write_oe (int which_side, int value, int mask);
972 bool write_io (int which_side, int value, int mask);
973 bool read_io (int which_side, int *value);
974 int read_io (int which_side);
975 bool write_refclk(int which_side, int value);
976 bool write_atr_mask(int which_side, int value);
977 bool write_atr_txval(int which_side, int value);
978 bool write_atr_rxval(int which_side, int value);
980 bool write_aux_dac (int which_side, int which_dac, int value);
981 bool read_aux_adc (int which_side, int which_adc, int *value);
982 int read_aux_adc (int which_side, int which_adc);
984 int block_size() const;
986 // called in base class to derived class order