4 * Copyright 2003,2004,2008 Free Software Foundation, Inc.
6 * This file is part of GNU Radio
8 * GNU Radio is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 3, or (at your option)
13 * GNU Radio is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with GNU Radio; see the file COPYING. If not, write to
20 * the Free Software Foundation, Inc., 51 Franklin Street,
21 * Boston, MA 02110-1301, USA.
25 * ----------------------------------------------------------------------
26 * Mid level interface to the Universal Software Radio Peripheral (Rev 1)
28 * These classes implement the basic functionality for talking to the
29 * USRP. They try to be as independent of the signal processing code
30 * in FPGA as possible. They implement access to the low level
31 * peripherals on the board, provide a common way for reading and
32 * writing registers in the FPGA, and provide the high speed interface
33 * to streaming data across the USB.
35 * It is expected that subclasses will be derived that provide
36 * access to the functionality to a particular FPGA configuration.
37 * ----------------------------------------------------------------------
40 #ifndef INCLUDED_USRP_BASIC_H
41 #define INCLUDED_USRP_BASIC_H
44 #include <usrp_slots.h>
47 #include <boost/utility.hpp>
48 #include <usrp_subdev_spec.h>
50 struct usb_dev_handle;
60 * \brief abstract base class for usrp operations
62 class usrp_basic : boost::noncopyable
65 void shutdown_daughterboards();
68 struct usb_dev_handle *d_udh;
69 int d_usb_data_rate; // bytes/sec
70 int d_bytes_per_poll; // how often to poll for overruns
73 static const int MAX_REGS = 128;
74 unsigned int d_fpga_shadows[MAX_REGS];
76 int d_dbid[2]; // daughterboard ID's (side A, side B)
79 * Shared pointers to subclasses of db_base.
81 * The outer vector is of length 2 (0 = side A, 1 = side B). The
82 * inner vectors are of length 1, 2 or 3 depending on the number of
83 * subdevices implemented by the daugherboard. At this time, only
84 * the Basic Rx and LF Rx implement more than 1 subdevice.
86 std::vector< std::vector<db_base_sptr> > d_db;
88 //! One time call, made only only from usrp_standard_*::make after shared_ptr is created.
89 void init_db(usrp_basic_sptr u);
92 usrp_basic (int which_board,
93 struct usb_dev_handle *open_interface (struct usb_device *dev),
94 const std::string fpga_filename = "",
95 const std::string firmware_filename = "");
98 * \brief advise usrp_basic of usb data rate (bytes/sec)
100 * N.B., this doesn't tweak any hardware. Derived classes
101 * should call this to inform us of the data rate whenever it's
102 * first set or if it changes.
104 * \param usb_data_rate bytes/sec
106 void set_usb_data_rate (int usb_data_rate);
109 * \brief Write auxiliary digital to analog converter.
111 * \param slot Which Tx or Rx slot to write.
112 * N.B., SLOT_TX_A and SLOT_RX_A share the same AUX DAC's.
113 * SLOT_TX_B and SLOT_RX_B share the same AUX DAC's.
114 * \param which_dac [0,3] RX slots must use only 0 and 1. TX slots must use only 2 and 3.
115 * \param value [0,4095]
116 * \returns true iff successful
118 bool _write_aux_dac (int slot, int which_dac, int value);
121 * \brief Read auxiliary analog to digital converter.
123 * \param slot 2-bit slot number. E.g., SLOT_TX_A
124 * \param which_adc [0,1]
125 * \param value return 12-bit value [0,4095]
126 * \returns true iff successful
128 bool _read_aux_adc (int slot, int which_adc, int *value);
131 * \brief Read auxiliary analog to digital converter.
133 * \param slot 2-bit slot number. E.g., SLOT_TX_A
134 * \param which_adc [0,1]
135 * \returns value in the range [0,4095] if successful, else READ_FAILED.
137 int _read_aux_adc (int slot, int which_adc);
141 virtual ~usrp_basic ();
145 * Return a vector of vectors that contain shared pointers
146 * to the daughterboard instance(s) associated with the specified side.
148 * It is an error to use the returned objects after the usrp_basic
149 * object has been destroyed.
151 std::vector<std::vector<db_base_sptr> > db() const { return d_db; }
154 * Return a vector of size >= 1 that contains shared pointers
155 * to the daughterboard instance(s) associated with the specified side.
157 * \param which_side [0,1] which daughterboard
159 * It is an error to use the returned objects after the usrp_basic
160 * object has been destroyed.
162 std::vector<db_base_sptr> db(int which_side);
165 * \brief is the subdev_spec valid?
167 bool is_valid(const usrp_subdev_spec &ss);
170 * \brief given a subdev_spec, return the corresponding daughterboard object.
171 * \throws std::invalid_ argument if ss is invalid.
173 * \param ss specifies the side and subdevice
175 db_base_sptr selected_subdev(const usrp_subdev_spec &ss);
178 * \brief return frequency of master oscillator on USRP
180 long fpga_master_clock_freq () const { return 64000000; }
183 * \returns usb data rate in bytes/sec
185 int usb_data_rate () const { return d_usb_data_rate; }
187 void set_verbose (bool on) { d_verbose = on; }
189 //! magic value used on alternate register read interfaces
190 static const int READ_FAILED = -99999;
193 * \brief Write EEPROM on motherboard or any daughterboard.
194 * \param i2c_addr I2C bus address of EEPROM
195 * \param eeprom_offset byte offset in EEPROM to begin writing
196 * \param buf the data to write
197 * \returns true iff sucessful
199 bool write_eeprom (int i2c_addr, int eeprom_offset, const std::string buf);
202 * \brief Read EEPROM on motherboard or any daughterboard.
203 * \param i2c_addr I2C bus address of EEPROM
204 * \param eeprom_offset byte offset in EEPROM to begin reading
205 * \param len number of bytes to read
206 * \returns the data read if successful, else a zero length string.
208 std::string read_eeprom (int i2c_addr, int eeprom_offset, int len);
211 * \brief Write to I2C peripheral
212 * \param i2c_addr I2C bus address (7-bits)
213 * \param buf the data to write
214 * \returns true iff successful
215 * Writes are limited to a maximum of of 64 bytes.
217 bool write_i2c (int i2c_addr, const std::string buf);
220 * \brief Read from I2C peripheral
221 * \param i2c_addr I2C bus address (7-bits)
222 * \param len number of bytes to read
223 * \returns the data read if successful, else a zero length string.
224 * Reads are limited to a maximum of 64 bytes.
226 std::string read_i2c (int i2c_addr, int len);
229 * \brief Set ADC offset correction
230 * \param which which ADC[0,3]: 0 = RX_A I, 1 = RX_A Q...
231 * \param offset 16-bit value to subtract from raw ADC input.
233 bool set_adc_offset (int which_adc, int offset);
236 * \brief Set DAC offset correction
237 * \param which which DAC[0,3]: 0 = TX_A I, 1 = TX_A Q...
238 * \param offset 10-bit offset value (ambiguous format: See AD9862 datasheet).
239 * \param offset_pin 1-bit value. If 0 offset applied to -ve differential pin;
240 * If 1 offset applied to +ve differential pin.
242 bool set_dac_offset (int which_dac, int offset, int offset_pin);
245 * \brief Control ADC input buffer
246 * \param which_adc which ADC[0,3]
247 * \param bypass if non-zero, bypass input buffer and connect input
248 * directly to switched cap SHA input of RxPGA.
250 bool set_adc_buffer_bypass (int which_adc, bool bypass);
253 * \brief Enable/disable automatic DC offset removal control loop in FPGA
255 * \param bits which control loops to enable
256 * \param mask which \p bits to pay attention to
258 * If the corresponding bit is set, enable the automatic DC
259 * offset correction control loop.
262 * The 4 low bits are significant:
270 * By default the control loop is enabled on all ADC's.
272 bool set_dc_offset_cl_enable(int bits, int mask);
275 * \brief return the usrp's serial number.
277 * \returns non-zero length string iff successful.
279 std::string serial_number();
282 * \brief Return daughterboard ID for given side [0,1].
284 * \param which_side [0,1] which daughterboard
286 * \return daughterboard id >= 0 if successful
287 * \return -1 if no daugherboard
288 * \return -2 if invalid EEPROM on daughterboard
290 virtual int daughterboard_id (int which_side) const = 0;
293 * \brief Clock ticks to delay rising of T/R signal
294 * \sa write_atr_mask, write_atr_txval, write_atr_rxval
296 bool write_atr_tx_delay(int value);
299 * \brief Clock ticks to delay falling edge of T/R signal
300 * \sa write_atr_mask, write_atr_txval, write_atr_rxval
302 bool write_atr_rx_delay(int value);
305 \f // ================================================================
306 // Routines to access and control daughterboard specific i/o
308 // Those with a common_ prefix access either the Tx or Rx side depending
309 // on the txrx parameter. Those without the common_ prefix are virtual
310 // and are overriden in usrp_basic_rx and usrp_basic_tx to access the
311 // the Rx or Tx sides automatically. We provide the common_ versions
312 // for those daughterboards such as the WBX and XCVR2450 that share
313 // h/w resources (such as the LO) between the Tx and Rx sides.
315 // ----------------------------------------------------------------
316 // BEGIN common_ daughterboard control functions
319 * \brief Set Programmable Gain Amplifier(PGA)
321 * \param txrx Tx or Rx?
322 * \param which_amp which amp [0,3]
323 * \param gain_in_db gain value(linear in dB)
325 * gain is rounded to closest setting supported by hardware.
327 * \returns true iff sucessful.
329 * \sa pga_min(), pga_max(), pga_db_per_step()
331 bool common_set_pga(txrx_t txrx, int which_amp, double gain_in_db);
334 * \brief Return programmable gain amplifier gain setting in dB.
336 * \param txrx Tx or Rx?
337 * \param which_amp which amp [0,3]
339 double common_pga(txrx_t txrx, int which_amp) const;
342 * \brief Return minimum legal PGA gain in dB.
343 * \param txrx Tx or Rx?
345 double common_pga_min(txrx_t txrx) const;
348 * \brief Return maximum legal PGA gain in dB.
349 * \param txrx Tx or Rx?
351 double common_pga_max(txrx_t txrx) const;
354 * \brief Return hardware step size of PGA(linear in dB).
355 * \param txrx Tx or Rx?
357 double common_pga_db_per_step(txrx_t txrx) const;
360 * \brief Write direction register(output enables) for pins that go to daughterboard.
362 * \param txrx Tx or Rx?
363 * \param which_side [0,1] which size
364 * \param value value to write into register
365 * \param mask which bits of value to write into reg
367 * Each d'board has 16-bits of general purpose i/o.
368 * Setting the bit makes it an output from the FPGA to the d'board.
370 * This register is initialized based on a value stored in the
371 * d'board EEPROM. In general, you shouldn't be using this routine
372 * without a very good reason. Using this method incorrectly will
373 * kill your USRP motherboard and/or daughterboard.
375 bool _common_write_oe(txrx_t txrx, int which_side, int value, int mask);
378 * \brief Write daughterboard i/o pin value
380 * \param txrx Tx or Rx?
381 * \param which_side [0,1] which d'board
382 * \param value value to write into register
383 * \param mask which bits of value to write into reg
385 bool common_write_io(txrx_t txrx, int which_side, int value, int mask);
388 * \brief Read daughterboard i/o pin value
390 * \param txrx Tx or Rx?
391 * \param which_side [0,1] which d'board
392 * \param value output
394 bool common_read_io(txrx_t txrx, int which_side, int *value);
397 * \brief Read daughterboard i/o pin value
399 * \param txrx Tx or Rx?
400 * \param which_side [0,1] which d'board
401 * \returns register value if successful, else READ_FAILED
403 int common_read_io(txrx_t txrx, int which_side);
406 * \brief Write daughterboard refclk config register
408 * \param txrx Tx or Rx?
409 * \param which_side [0,1] which d'board
410 * \param value value to write into register, see below
413 * Control whether a reference clock is sent to the daughterboards,
414 * and what frequency. The refclk is sent on d'board i/o pin 0.
417 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
418 * +-----------------------------------------------+-+------------+
419 * | Reserved (Must be zero) |E| DIVISOR |
420 * +-----------------------------------------------+-+------------+
422 * Bit 7 -- 1 turns on refclk, 0 allows IO use
423 * Bits 6:0 Divider value
426 bool common_write_refclk(txrx_t txrx, int which_side, int value);
429 * \brief Automatic Transmit/Receive switching
432 * If automatic transmit/receive (ATR) switching is enabled in the
433 * FR_ATR_CTL register, the presence or absence of data in the FPGA
434 * transmit fifo selects between two sets of values for each of the 4
435 * banks of daughterboard i/o pins.
437 * Each daughterboard slot has 3 16-bit registers associated with it:
438 * FR_ATR_MASK_*, FR_ATR_TXVAL_* and FR_ATR_RXVAL_*
440 * FR_ATR_MASK_{0,1,2,3}:
442 * These registers determine which of the daugherboard i/o pins are
443 * affected by ATR switching. If a bit in the mask is set, the
444 * corresponding i/o bit is controlled by ATR, else it's output
445 * value comes from the normal i/o pin output register:
448 * FR_ATR_TXVAL_{0,1,2,3}:
449 * FR_ATR_RXVAL_{0,1,2,3}:
451 * If the Tx fifo contains data, then the bits from TXVAL that are
452 * selected by MASK are output. Otherwise, the bits from RXVAL that
453 * are selected by MASK are output.
456 bool common_write_atr_mask(txrx_t txrx, int which_side, int value);
457 bool common_write_atr_txval(txrx_t txrx, int which_side, int value);
458 bool common_write_atr_rxval(txrx_t txrx, int which_side, int value);
461 * \brief Write auxiliary digital to analog converter.
463 * \param txrx Tx or Rx?
464 * \param which_side [0,1] which d'board
465 * N.B., SLOT_TX_A and SLOT_RX_A share the same AUX DAC's.
466 * SLOT_TX_B and SLOT_RX_B share the same AUX DAC's.
467 * \param which_dac [2,3] TX slots must use only 2 and 3.
468 * \param value [0,4095]
469 * \returns true iff successful
471 bool common_write_aux_dac(txrx_t txrx, int which_side, int which_dac, int value);
474 * \brief Read auxiliary analog to digital converter.
476 * \param txrx Tx or Rx?
477 * \param which_side [0,1] which d'board
478 * \param which_adc [0,1]
479 * \param value return 12-bit value [0,4095]
480 * \returns true iff successful
482 bool common_read_aux_adc(txrx_t txrx, int which_side, int which_adc, int *value);
485 * \brief Read auxiliary analog to digital converter.
487 * \param txrx Tx or Rx?
488 * \param which_side [0,1] which d'board
489 * \param which_adc [0,1]
490 * \returns value in the range [0,4095] if successful, else READ_FAILED.
492 int common_read_aux_adc(txrx_t txrx, int which_side, int which_adc);
494 // END common_ daughterboard control functions
\f
495 // ----------------------------------------------------------------
496 // BEGIN virtual daughterboard control functions
499 * \brief Set Programmable Gain Amplifier (PGA)
501 * \param which_amp which amp [0,3]
502 * \param gain_in_db gain value (linear in dB)
504 * gain is rounded to closest setting supported by hardware.
506 * \returns true iff sucessful.
508 * \sa pga_min(), pga_max(), pga_db_per_step()
510 virtual bool set_pga (int which_amp, double gain_in_db) = 0;
513 * \brief Return programmable gain amplifier gain setting in dB.
515 * \param which_amp which amp [0,3]
517 virtual double pga (int which_amp) const = 0;
520 * \brief Return minimum legal PGA gain in dB.
522 virtual double pga_min () const = 0;
525 * \brief Return maximum legal PGA gain in dB.
527 virtual double pga_max () const = 0;
530 * \brief Return hardware step size of PGA (linear in dB).
532 virtual double pga_db_per_step () const = 0;
535 * \brief Write direction register (output enables) for pins that go to daughterboard.
537 * \param which_side [0,1] which size
538 * \param value value to write into register
539 * \param mask which bits of value to write into reg
541 * Each d'board has 16-bits of general purpose i/o.
542 * Setting the bit makes it an output from the FPGA to the d'board.
544 * This register is initialized based on a value stored in the
545 * d'board EEPROM. In general, you shouldn't be using this routine
546 * without a very good reason. Using this method incorrectly will
547 * kill your USRP motherboard and/or daughterboard.
549 virtual bool _write_oe (int which_side, int value, int mask) = 0;
552 * \brief Write daughterboard i/o pin value
554 * \param which_side [0,1] which d'board
555 * \param value value to write into register
556 * \param mask which bits of value to write into reg
558 virtual bool write_io (int which_side, int value, int mask) = 0;
561 * \brief Read daughterboard i/o pin value
563 * \param which_side [0,1] which d'board
564 * \param value output
566 virtual bool read_io (int which_side, int *value) = 0;
569 * \brief Read daughterboard i/o pin value
571 * \param which_side [0,1] which d'board
572 * \returns register value if successful, else READ_FAILED
574 virtual int read_io (int which_side) = 0;
577 * \brief Write daughterboard refclk config register
579 * \param which_side [0,1] which d'board
580 * \param value value to write into register, see below
583 * Control whether a reference clock is sent to the daughterboards,
584 * and what frequency. The refclk is sent on d'board i/o pin 0.
587 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
588 * +-----------------------------------------------+-+------------+
589 * | Reserved (Must be zero) |E| DIVISOR |
590 * +-----------------------------------------------+-+------------+
592 * Bit 7 -- 1 turns on refclk, 0 allows IO use
593 * Bits 6:0 Divider value
596 virtual bool write_refclk(int which_side, int value) = 0;
598 virtual bool write_atr_mask(int which_side, int value) = 0;
599 virtual bool write_atr_txval(int which_side, int value) = 0;
600 virtual bool write_atr_rxval(int which_side, int value) = 0;
603 * \brief Write auxiliary digital to analog converter.
605 * \param which_side [0,1] which d'board
606 * N.B., SLOT_TX_A and SLOT_RX_A share the same AUX DAC's.
607 * SLOT_TX_B and SLOT_RX_B share the same AUX DAC's.
608 * \param which_dac [2,3] TX slots must use only 2 and 3.
609 * \param value [0,4095]
610 * \returns true iff successful
612 virtual bool write_aux_dac (int which_side, int which_dac, int value) = 0;
615 * \brief Read auxiliary analog to digital converter.
617 * \param which_side [0,1] which d'board
618 * \param which_adc [0,1]
619 * \param value return 12-bit value [0,4095]
620 * \returns true iff successful
622 virtual bool read_aux_adc (int which_side, int which_adc, int *value) = 0;
625 * \brief Read auxiliary analog to digital converter.
627 * \param which_side [0,1] which d'board
628 * \param which_adc [0,1]
629 * \returns value in the range [0,4095] if successful, else READ_FAILED.
631 virtual int read_aux_adc (int which_side, int which_adc) = 0;
634 * \brief returns current fusb block size
636 virtual int block_size() const = 0;
639 * \brief returns A/D or D/A converter rate in Hz
641 virtual long converter_rate() const = 0;
643 // END virtual daughterboard control functions
\f
645 // ----------------------------------------------------------------
646 // Low level implementation routines.
647 // You probably shouldn't be using these...
650 bool _set_led (int which_led, bool on);
653 * \brief Write FPGA register.
654 * \param regno 7-bit register number
655 * \param value 32-bit value
656 * \returns true iff successful
658 bool _write_fpga_reg (int regno, int value); //< 7-bit regno, 32-bit value
661 * \brief Read FPGA register.
662 * \param regno 7-bit register number
663 * \param value 32-bit value
664 * \returns true iff successful
666 bool _read_fpga_reg (int regno, int *value); //< 7-bit regno, 32-bit value
669 * \brief Read FPGA register.
670 * \param regno 7-bit register number
671 * \returns register value if successful, else READ_FAILED
673 int _read_fpga_reg (int regno);
676 * \brief Write FPGA register with mask.
677 * \param regno 7-bit register number
678 * \param value 16-bit value
679 * \param mask 16-bit value
680 * \returns true if successful
681 * Only use this for registers who actually implement a mask in the verilog firmware, like FR_RX_MASTER_SLAVE
683 bool _write_fpga_reg_masked (int regno, int value, int mask);
686 * \brief Write AD9862 register.
687 * \param which_codec 0 or 1
688 * \param regno 6-bit register number
689 * \param value 8-bit value
690 * \returns true iff successful
692 bool _write_9862 (int which_codec, int regno, unsigned char value);
695 * \brief Read AD9862 register.
696 * \param which_codec 0 or 1
697 * \param regno 6-bit register number
698 * \param value 8-bit value
699 * \returns true iff successful
701 bool _read_9862 (int which_codec, int regno, unsigned char *value) const;
704 * \brief Read AD9862 register.
705 * \param which_codec 0 or 1
706 * \param regno 6-bit register number
707 * \returns register value if successful, else READ_FAILED
709 int _read_9862 (int which_codec, int regno) const;
712 * \brief Write data to SPI bus peripheral.
714 * \param optional_header 0,1 or 2 bytes to write before buf.
715 * \param enables bitmask of peripherals to write. See usrp_spi_defs.h
716 * \param format transaction format. See usrp_spi_defs.h SPI_FMT_*
717 * \param buf the data to write
718 * \returns true iff successful
719 * Writes are limited to a maximum of 64 bytes.
721 * If \p format specifies that optional_header bytes are present, they are
722 * written to the peripheral immediately prior to writing \p buf.
724 bool _write_spi (int optional_header, int enables, int format, std::string buf);
727 * \brief Read data from SPI bus peripheral.
729 * \param optional_header 0,1 or 2 bytes to write before buf.
730 * \param enables bitmask of peripheral to read. See usrp_spi_defs.h
731 * \param format transaction format. See usrp_spi_defs.h SPI_FMT_*
732 * \param len number of bytes to read. Must be in [0,64].
733 * \returns the data read if sucessful, else a zero length string.
735 * Reads are limited to a maximum of 64 bytes.
737 * If \p format specifies that optional_header bytes are present, they
738 * are written to the peripheral first. Then \p len bytes are read from
739 * the peripheral and returned.
741 std::string _read_spi (int optional_header, int enables, int format, int len);
744 * \brief Start data transfers.
745 * Called in base class to derived class order.
750 * \brief Stop data transfers.
751 * Called in base class to derived class order.
757 * \brief class for accessing the receive side of the USRP
759 class usrp_basic_rx : public usrp_basic
762 fusb_devhandle *d_devhandle;
763 fusb_ephandle *d_ephandle;
764 int d_bytes_seen; // how many bytes we've seen
770 * \param which_board Which USRP board on usb (not particularly useful; use 0)
771 * \param fusb_block_size fast usb xfer block size. Must be a multiple of 512.
772 * Use zero for a reasonable default.
773 * \param fusb_nblocks number of fast usb URBs to allocate. Use zero for a reasonable default.
775 usrp_basic_rx (int which_board,
776 int fusb_block_size=0,
778 const std::string fpga_filename = "",
779 const std::string firmware_filename = ""
780 ); // throws if trouble
782 bool set_rx_enable (bool on);
783 bool rx_enable () const { return d_rx_enable; }
785 bool disable_rx (); // conditional disable, return prev state
786 void restore_rx (bool on); // conditional set
788 void probe_rx_slots (bool verbose);
794 * \brief invokes constructor, returns instance or 0 if trouble
796 * \param which_board Which USRP board on usb (not particularly useful; use 0)
797 * \param fusb_block_size fast usb xfer block size. Must be a multiple of 512.
798 * Use zero for a reasonable default.
799 * \param fusb_nblocks number of fast usb URBs to allocate. Use zero for a reasonable default.
800 * \param fpga_filename name of file that contains image to load into FPGA
801 * \param firmware_filename name of file that contains image to load into FX2
803 static usrp_basic_rx *make (int which_board,
804 int fusb_block_size=0,
806 const std::string fpga_filename = "",
807 const std::string firmware_filename = ""
811 * \brief tell the fpga the rate rx samples are coming from the A/D's
813 * div = fpga_master_clock_freq () / sample_rate
815 * sample_rate is determined by a myriad of registers
816 * in the 9862. That's why you have to tell us, so
817 * we can tell the fpga.
819 bool set_fpga_rx_sample_rate_divisor (unsigned int div);
822 * \brief read data from the D/A's via the FPGA.
823 * \p len must be a multiple of 512 bytes.
825 * \returns the number of bytes read, or -1 on error.
827 * If overrun is non-NULL it will be set true iff an RX overrun is detected.
829 int read (void *buf, int len, bool *overrun);
832 //! sampling rate of A/D converter
833 virtual long converter_rate() const { return fpga_master_clock_freq(); } // 64M
834 long adc_rate() const { return converter_rate(); }
835 int daughterboard_id (int which_side) const { return d_dbid[which_side & 0x1]; }
837 bool set_pga (int which_amp, double gain_in_db);
838 double pga (int which_amp) const;
839 double pga_min () const;
840 double pga_max () const;
841 double pga_db_per_step () const;
843 bool _write_oe (int which_side, int value, int mask);
844 bool write_io (int which_side, int value, int mask);
845 bool read_io (int which_side, int *value);
846 int read_io (int which_side);
847 bool write_refclk(int which_side, int value);
848 bool write_atr_mask(int which_side, int value);
849 bool write_atr_txval(int which_side, int value);
850 bool write_atr_rxval(int which_side, int value);
852 bool write_aux_dac (int which_side, int which_dac, int value);
853 bool read_aux_adc (int which_side, int which_adc, int *value);
854 int read_aux_adc (int which_side, int which_adc);
856 int block_size() const;
858 // called in base class to derived class order
864 * \brief class for accessing the transmit side of the USRP
866 class usrp_basic_tx : public usrp_basic
869 fusb_devhandle *d_devhandle;
870 fusb_ephandle *d_ephandle;
871 int d_bytes_seen; // how many bytes we've seen
877 * \param which_board Which USRP board on usb (not particularly useful; use 0)
878 * \param fusb_block_size fast usb xfer block size. Must be a multiple of 512.
879 * Use zero for a reasonable default.
880 * \param fusb_nblocks number of fast usb URBs to allocate. Use zero for a reasonable default.
881 * \param fpga_filename name of file that contains image to load into FPGA
882 * \param firmware_filename name of file that contains image to load into FX2
884 usrp_basic_tx (int which_board,
885 int fusb_block_size=0,
887 const std::string fpga_filename = "",
888 const std::string firmware_filename = ""
889 ); // throws if trouble
891 bool set_tx_enable (bool on);
892 bool tx_enable () const { return d_tx_enable; }
894 bool disable_tx (); // conditional disable, return prev state
895 void restore_tx (bool on); // conditional set
897 void probe_tx_slots (bool verbose);
904 * \brief invokes constructor, returns instance or 0 if trouble
906 * \param which_board Which USRP board on usb (not particularly useful; use 0)
907 * \param fusb_block_size fast usb xfer block size. Must be a multiple of 512.
908 * Use zero for a reasonable default.
909 * \param fusb_nblocks number of fast usb URBs to allocate. Use zero for a reasonable default.
910 * \param fpga_filename name of file that contains image to load into FPGA
911 * \param firmware_filename name of file that contains image to load into FX2
913 static usrp_basic_tx *make (int which_board, int fusb_block_size=0, int fusb_nblocks=0,
914 const std::string fpga_filename = "",
915 const std::string firmware_filename = ""
919 * \brief tell the fpga the rate tx samples are going to the D/A's
921 * div = fpga_master_clock_freq () * 2
923 * sample_rate is determined by a myriad of registers
924 * in the 9862. That's why you have to tell us, so
925 * we can tell the fpga.
927 bool set_fpga_tx_sample_rate_divisor (unsigned int div);
930 * \brief Write data to the A/D's via the FPGA.
932 * \p len must be a multiple of 512 bytes.
933 * \returns number of bytes written or -1 on error.
935 * if \p underrun is non-NULL, it will be set to true iff
936 * a transmit underrun condition is detected.
938 int write (const void *buf, int len, bool *underrun);
941 * Block until all outstanding writes have completed.
942 * This is typically used to assist with benchmarking
944 void wait_for_completion ();
946 //! sampling rate of D/A converter
947 virtual long converter_rate() const { return fpga_master_clock_freq () * 2; } // 128M
948 long dac_rate() const { return converter_rate(); }
949 int daughterboard_id (int which_side) const { return d_dbid[which_side & 0x1]; }
951 bool set_pga (int which_amp, double gain_in_db);
952 double pga (int which_amp) const;
953 double pga_min () const;
954 double pga_max () const;
955 double pga_db_per_step () const;
957 bool _write_oe (int which_side, int value, int mask);
958 bool write_io (int which_side, int value, int mask);
959 bool read_io (int which_side, int *value);
960 int read_io (int which_side);
961 bool write_refclk(int which_side, int value);
962 bool write_atr_mask(int which_side, int value);
963 bool write_atr_txval(int which_side, int value);
964 bool write_atr_rxval(int which_side, int value);
966 bool write_aux_dac (int which_side, int which_dac, int value);
967 bool read_aux_adc (int which_side, int which_adc, int *value);
968 int read_aux_adc (int which_side, int which_adc);
970 int block_size() const;
972 // called in base class to derived class order