2 // Copyright 2008 Free Software Foundation, Inc.
4 // This file is part of GNU Radio
6 // GNU Radio is free software; you can redistribute it and/or modify
7 // it under the terms of the GNU General Public License as published by
8 // the Free Software Foundation; either asversion 3, or (at your option)
11 // GNU Radio is distributed in the hope that it will be useful,
12 // but WITHOUT ANY WARRANTY; without even the implied warranty of
13 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 // GNU General Public License for more details.
16 // You should have received a copy of the GNU General Public License
17 // along with GNU Radio; see the file COPYING. If not, write to
18 // the Free Software Foundation, Inc., 51 Franklin Street,
19 // Boston, MA 02110-1301, USA.
21 #include <db_xcvr2450.h>
22 #include <db_base_impl.h>
26 /* ------------------------------------------------------------------------
27 * A few comments about the XCVR2450:
29 * It is half-duplex. I.e., transmit and receive are mutually exclusive.
30 * There is a single LO for both the Tx and Rx sides.
31 * For our purposes the board is always either receiving or transmitting.
33 * Each board is uniquely identified by the *USRP hardware* instance and side
34 * This dictionary holds a weak reference to existing board controller so it
35 * can be created or retrieved as needed.
39 /*****************************************************************************/
42 xcvr2450::xcvr2450(usrp_basic_sptr _usrp, int which)
43 : d_weak_usrp(_usrp), d_which(which)
45 // Handler for Tv Rx daughterboards.
47 // @param usrp: instance of usrp.source_c
48 // @param which: which side: 0, 1 corresponding to RX_A or RX_B respectively
50 // Use MSB with no header
51 d_spi_format = SPI_FMT_MSB | SPI_FMT_HDR_0;
54 d_spi_enable = SPI_ENABLE_RX_A;
57 d_spi_enable = SPI_ENABLE_RX_B;
61 d_mimo = 1; // 0 = OFF, 1 = ON
62 d_int_div = 192; // 128 = min, 255 = max
63 d_frac_div = 0; // 0 = min, 65535 = max
64 d_highband = 0; // 0 = freq <= 5.4e9, 1 = freq > 5.4e9
65 d_five_gig = 0; // 0 = freq <= 3.e9, 1 = freq > 3e9
66 d_cp_current = 0; // 0 = 2mA, 1 = 4mA
67 d_ref_div = 4; // 1 to 7
68 d_rssi_hbw = 0; // 0 = 2 MHz, 1 = 6 MHz
69 d_txlpf_bw = 1; // 1 = 12 MHz, 2 = 18 MHz, 3 = 24 MHz
70 d_rxlpf_bw = 1; // 0 = 7.5 MHz, 1 = 9.5 MHz, 2 = 14 MHz, 3 = 18 MHz
71 d_rxlpf_fine = 2; // 0 = 90%, 1 = 95%, 2 = 100%, 3 = 105%, 4 = 110%
72 d_rxvga_ser = 1; // 0 = RXVGA controlled by B7:1, 1=controlled serially
73 d_rssi_range = 1; // 0 = low range (datasheet typo), 1=high range (0.5V - 2.0V)
74 d_rssi_mode = 1; // 0 = enable follows RXHP, 1 = enabled
75 d_rssi_mux = 0; // 0 = RSSI, 1 = TEMP
76 d_rx_hp_pin = 0; // 0 = Fc set by rx_hpf, 1 = 600 KHz
77 d_rx_hpf = 0; // 0 = 100Hz, 1 = 30KHz
78 d_rx_ant = 0; // 0 = Ant. #1, 1 = Ant. #2
79 d_tx_ant = 0; // 0 = Ant. #1, 1 = Ant. #2
80 d_txvga_ser = 1; // 0 = TXVGA controlled by B6:1, 1=controlled serially
81 d_tx_driver_lin = 2; // 0=50% (worst linearity), 1=63%, 2=78%, 3=100% (best lin)
82 d_tx_vga_lin = 2; // 0=50% (worst linearity), 1=63%, 2=78%, 3=100% (best lin)
83 d_tx_upconv_lin = 2; // 0=50% (worst linearity), 1=63%, 2=78%, 3=100% (best lin)
84 d_tx_bb_gain = 3; // 0=maxgain-5dB, 1=max-3dB, 2=max-1.5dB, 3=max
85 d_pabias_delay = 15; // 0 = 0, 15 = 7uS
86 d_pabias = 0; // 0 = 0 uA, 63 = 315uA
87 d_rx_rf_gain = 0; // 0 = 0dB, 1 = 0dB, 2 = 15dB, 3 = 30dB
88 d_rx_bb_gain = 16; // 0 = min, 31 = max (0 - 62 dB)
90 d_txgain = 63; // 0 = min, 63 = max
92 // Initialize GPIO and ATR
93 tx_write_io(TX_SAFE_IO, TX_OE_MASK);
94 tx_write_oe(TX_OE_MASK, ~0);
95 tx_set_atr_txval(TX_SAFE_IO);
96 tx_set_atr_rxval(TX_SAFE_IO);
97 tx_set_atr_mask(TX_OE_MASK);
98 rx_write_io(RX_SAFE_IO, RX_OE_MASK);
99 rx_write_oe(RX_OE_MASK, ~0);
100 rx_set_atr_rxval(RX_SAFE_IO);
101 rx_set_atr_txval(RX_SAFE_IO);
102 rx_set_atr_mask(RX_OE_MASK);
104 // Initialize chipset
105 // TODO: perform reset sequence to ensure power up defaults
107 set_reg_bandselpll();
110 set_reg_rxrssi_ctrl();
111 set_reg_txlin_gain();
115 //FIXME: set_freq(2.45e9);
118 xcvr2450::~xcvr2450()
120 //printf("xcvr2450::destructor\n");
121 tx_set_atr_txval(TX_SAFE_IO);
122 tx_set_atr_rxval(TX_SAFE_IO);
123 rx_set_atr_rxval(RX_SAFE_IO);
124 rx_set_atr_txval(RX_SAFE_IO);
128 xcvr2450::operator==(xcvr2450_key x)
130 if((x.serial_no == usrp()->serial_number()) && (x.which == d_which)) {
139 xcvr2450::set_reg_standby()
141 d_reg_standby = ((d_mimo<<17) |
146 send_reg(d_reg_standby);
150 xcvr2450::set_reg_int_divider()
152 d_reg_int_divider = (((d_frac_div & 0x03)<<16) |
154 send_reg(d_reg_int_divider);
158 xcvr2450::set_reg_frac_divider()
160 d_reg_frac_divider = ((d_frac_div & 0xfffc)<<2) | 4;
161 send_reg(d_reg_frac_divider);
165 xcvr2450::set_reg_bandselpll()
167 d_reg_bandselpll = ((d_mimo<<17) |
174 (d_five_gig<<4) | 5);
175 send_reg(d_reg_bandselpll);
179 xcvr2450::set_reg_cal()
181 // FIXME do calibration
182 d_reg_cal = (1<<14)|6;
187 xcvr2450::set_reg_lpf()
193 (d_rxlpf_fine<<4) | 7);
198 xcvr2450::set_reg_rxrssi_ctrl()
200 d_reg_rxrssi_ctrl = ((d_rxvga_ser<<16) |
207 send_reg(d_reg_rxrssi_ctrl);
211 xcvr2450::set_reg_txlin_gain()
213 d_reg_txlin_gain = ((d_txvga_ser<<14) |
214 (d_tx_driver_lin<<12) |
216 (d_tx_upconv_lin<<6) |
217 (d_tx_bb_gain<<4) | 9);
218 send_reg(d_reg_txlin_gain);
222 xcvr2450::set_reg_pabias()
225 (d_pabias_delay<<10) |
227 send_reg(d_reg_pabias);
231 xcvr2450::set_reg_rxgain()
235 (d_rx_bb_gain<<4) | 11);
236 send_reg(d_reg_rxgain);
240 xcvr2450::set_reg_txgain()
242 d_reg_txgain = (d_txgain<<4) | 12;
243 send_reg(d_reg_txgain);
247 xcvr2450::send_reg(int v)
249 // Send 24 bits, it keeps last 18 clocked in
251 c[0] = (char)((v >> 16) & 0xff);
252 c[1] = (char)((v >> 8) & 0xff);
253 c[2] = (char)((v & 0xff));
256 usrp()->_write_spi(0, d_spi_enable, d_spi_format, s);
257 //printf("xcvr2450: Setting reg %d to %06X\n", (v&15), v);
260 // --------------------------------------------------------------------
261 // These methods control the GPIO bus. Since the board has to access
262 // both the io_rx_* and io_tx_* pins, we define our own methods to do so.
263 // This bypasses any code in db_base.
265 // The board operates in ATR mode, always. Thus, when the board is first
266 // initialized, it is in receive mode, until bits show up in the TX FIFO.
269 // FIXME these should just call the similarly named common_* method on usrp_basic
272 xcvr2450::tx_write_oe(int value, int mask)
279 return usrp()->_write_fpga_reg(reg, (mask << 16) | value);
283 xcvr2450::tx_write_io(int value, int mask)
290 return usrp()->_write_fpga_reg(reg, (mask << 16) | value);
294 xcvr2450::tx_read_io()
298 val = FR_RB_IO_RX_A_IO_TX_A;
300 val = FR_RB_IO_RX_B_IO_TX_B;
301 int t = usrp()->_read_fpga_reg(val);
306 xcvr2450::rx_write_oe(int value, int mask)
313 return usrp()->_write_fpga_reg(reg, (mask << 16) | value);
317 xcvr2450::rx_write_io(int value, int mask)
324 return usrp()->_write_fpga_reg(reg, (mask << 16) | value);
328 xcvr2450::rx_read_io()
332 val = FR_RB_IO_RX_A_IO_TX_A;
334 val = FR_RB_IO_RX_B_IO_TX_B;
335 int t = usrp()->_read_fpga_reg(val);
336 return (t >> 16) & 0xffff;
340 xcvr2450::tx_set_atr_mask(int v)
347 return usrp()->_write_fpga_reg(reg, v);
351 xcvr2450::tx_set_atr_txval(int v)
355 reg = FR_ATR_TXVAL_0;
357 reg = FR_ATR_TXVAL_2;
358 return usrp()->_write_fpga_reg(reg, v);
362 xcvr2450::tx_set_atr_rxval(int v)
366 reg = FR_ATR_RXVAL_0;
368 reg = FR_ATR_RXVAL_2;
369 return usrp()->_write_fpga_reg(reg, v);
373 xcvr2450::rx_set_atr_mask(int v)
380 return usrp()->_write_fpga_reg(reg, v);
384 xcvr2450::rx_set_atr_txval(int v)
388 reg = FR_ATR_TXVAL_1;
390 reg = FR_ATR_TXVAL_3;
391 return usrp()->_write_fpga_reg(reg, v);
395 xcvr2450::rx_set_atr_rxval(int v)
399 reg = FR_ATR_RXVAL_1;
401 reg = FR_ATR_RXVAL_3;
402 return usrp()->_write_fpga_reg(reg, v);
405 // ----------------------------------------------------------------
410 // We calculate four values:
412 // io_rx_while_rx: what to drive onto io_rx_* when receiving
413 // io_rx_while_tx: what to drive onto io_rx_* when transmitting
414 // io_tx_while_rx: what to drive onto io_tx_* when receiving
415 // io_tx_while_tx: what to drive onto io_tx_* when transmitting
417 // B1-B7 is ignored as gain is set serially for now.
419 int rx_hp, tx_antsel, rx_antsel, tx_pa_sel;
426 tx_antsel = ANTSEL_TX1_RX2;
428 tx_antsel = ANTSEL_TX2_RX1;
431 rx_antsel = ANTSEL_TX1_RX2;
433 rx_antsel = ANTSEL_TX2_RX1;
436 tx_pa_sel = HB_PA_OFF;
438 tx_pa_sel = LB_PA_OFF;
440 int io_rx_while_rx = EN|rx_hp|RX_EN;
441 int io_rx_while_tx = EN|rx_hp;
442 int io_tx_while_rx = HB_PA_OFF|LB_PA_OFF|rx_antsel|AD9515DIV;
443 int io_tx_while_tx = tx_pa_sel|tx_antsel|TX_EN|AD9515DIV;
444 rx_set_atr_rxval(io_rx_while_rx);
445 rx_set_atr_txval(io_rx_while_tx);
446 tx_set_atr_rxval(io_tx_while_rx);
447 tx_set_atr_txval(io_tx_while_tx);
449 //printf("GPIO: RXRX=%04X RXTX=%04X TXRX=%04X TXTX=%04X",
450 // io_rx_while_rx, io_rx_while_tx, io_tx_while_rx, io_tx_while_tx);
455 xcvr2450::set_freq(double target_freq)
457 struct freq_result_t args = {false, 0};
461 if(target_freq > 3e9) {
474 if(target_freq > 5.27e9) {
481 double vco_freq = target_freq*scaler;
482 double sys_clk = usrp()->fpga_master_clock_freq(); // Usually 64e6
483 double ref_clk = sys_clk / d_ad9515_div;
485 double phdet_freq = ref_clk/d_ref_div;
486 double div = vco_freq/phdet_freq;
487 d_int_div = int(floor(div));
488 d_frac_div = int((div-d_int_div)*65536.0);
489 double actual_freq = phdet_freq*(d_int_div+(d_frac_div/65536.0))/scaler;
491 //printf("RF=%f VCO=%f R=%d PHD=%f DIV=%3.5f I=%3d F=%5d ACT=%f",
492 // target_freq, vco_freq, d_ref_div, phdet_freq,
493 // div, d_int_div, d_frac_div, actual_freq);
496 set_reg_int_divider();
497 set_reg_frac_divider();
498 set_reg_bandselpll();
500 args.ok = lock_detect();
501 args.baseband_freq = actual_freq;
504 if((target_freq > 5.275e9) && (target_freq <= 5.35e9)) {
506 set_reg_bandselpll();
507 args.ok = lock_detect();
508 printf("swap to 0 at %f, ok %d\n", target_freq, args.ok);
510 if((target_freq >= 5.25e9) && (target_freq <= 5.275e9)) {
512 set_reg_bandselpll();
513 args.ok = lock_detect();
514 printf("swap to 1 at %f, ok %d\n", target_freq, args.ok);
517 printf("Fail %f\n", target_freq);
524 xcvr2450::lock_detect()
527 @returns: the value of the VCO/PLL lock detect bit.
530 if(rx_read_io() & LOCKDET) {
533 else { // Give it a second chance
534 if(rx_read_io() & LOCKDET)
542 xcvr2450::set_rx_gain(float gain)
549 // Split the gain between RF and baseband
550 // This is experimental, not prescribed
552 d_rx_rf_gain = 0; // 0 dB RF gain
553 rx_bb_gain = int(gain/2.0);
556 if(gain >= 30.0 and gain < 60.5) {
557 d_rx_rf_gain = 2; // 15 dB RF gain
558 d_rx_bb_gain = int((gain-15.0)/2.0);
562 d_rx_rf_gain = 3; // 30.5 dB RF gain
563 d_rx_bb_gain = int((gain-30.5)/2.0);
572 xcvr2450::set_tx_gain(float gain)
581 d_txgain = int((gain/30.0)*63);
588 /*****************************************************************************/
591 //_xcvr2450_inst = weakref.WeakValueDictionary()
592 std::vector<xcvr2450_sptr> _xcvr2450_inst;
595 _get_or_make_xcvr2450(usrp_basic_sptr usrp, int which)
598 xcvr2450_key key = {usrp->serial_number(), which};
599 std::vector<xcvr2450_sptr>::iterator itr; // =
600 //std::find(_xcvr2450_inst.begin(), _xcvr2450_inst.end(), key);
602 for(itr = _xcvr2450_inst.begin(); itr != _xcvr2450_inst.end(); itr++) {
604 printf("Using existing xcvr2450 instance\n");
610 if(itr != _xcvr2450_inst.end()) {
611 printf("Creating new xcvr2450 instance\n");
612 inst = xcvr2450_sptr(new xcvr2450(usrp, which));
613 _xcvr2450_inst.push_back(inst);
620 /*****************************************************************************/
623 db_xcvr2450_base::db_xcvr2450_base(usrp_basic_sptr usrp, int which)
624 : db_base(usrp, which)
627 * Abstract base class for all xcvr2450 boards.
629 * Derive board specific subclasses from db_xcvr2450_base_{tx,rx}
631 * @param usrp: instance of usrp.source_c
632 * @param which: which side: 0 or 1 corresponding to side A or B respectively
636 d_xcvr = _get_or_make_xcvr2450(usrp, which);
639 db_xcvr2450_base::~db_xcvr2450_base()
644 db_xcvr2450_base::set_freq(double target_freq)
647 * @returns (ok, actual_baseband_freq) where:
648 * ok is True or False and indicates success or failure,
649 * actual_baseband_freq is the RF frequency that corresponds to DC in the IF.
651 return d_xcvr->set_freq(target_freq);
655 db_xcvr2450_base::is_quadrature()
658 * Return True if this board requires both I & Q analog channels.
660 * This bit of info is useful when setting up the USRP Rx mux register.
666 db_xcvr2450_base::freq_min()
672 db_xcvr2450_base::freq_max()
678 /******************************************************************************/
681 db_xcvr2450_tx::db_xcvr2450_tx(usrp_basic_sptr usrp, int which)
682 : db_xcvr2450_base(usrp, which)
684 printf("db_xcvr2450_tx::db_xcvr2450_tx\n");
687 db_xcvr2450_tx::~db_xcvr2450_tx()
692 db_xcvr2450_tx::gain_min()
698 db_xcvr2450_tx::gain_max()
704 db_xcvr2450_tx::gain_db_per_step()
710 db_xcvr2450_tx::set_gain(float gain)
712 return d_xcvr->set_tx_gain(gain);
716 db_xcvr2450_tx::i_and_q_swapped()
722 /******************************************************************************/
725 db_xcvr2450_rx::db_xcvr2450_rx(usrp_basic_sptr usrp, int which)
726 : db_xcvr2450_base(usrp, which)
729 * @param usrp: instance of usrp.source_c
730 * @param which: 0 or 1 corresponding to side RX_A or RX_B respectively.
733 printf("db_xcvr2450_rx:d_xcvr_2450_rx\n");
736 db_xcvr2450_rx::~db_xcvr2450_rx()
741 db_xcvr2450_rx::gain_min()
747 db_xcvr2450_rx::gain_max()
753 db_xcvr2450_rx::gain_db_per_step()
759 db_xcvr2450_rx::set_gain(float gain)
761 return d_xcvr->set_rx_gain(gain);