2 // Copyright 2008,2009 Free Software Foundation, Inc.
4 // This file is part of GNU Radio
6 // GNU Radio is free software; you can redistribute it and/or modify
7 // it under the terms of the GNU General Public License as published by
8 // the Free Software Foundation; either asversion 3, or (at your option)
11 // GNU Radio is distributed in the hope that it will be useful,
12 // but WITHOUT ANY WARRANTY; without even the implied warranty of
13 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 // GNU General Public License for more details.
16 // You should have received a copy of the GNU General Public License
17 // along with GNU Radio; see the file COPYING. If not, write to
18 // the Free Software Foundation, Inc., 51 Franklin Street,
19 // Boston, MA 02110-1301, USA.
21 #include <db_xcvr2450.h>
22 #include <db_base_impl.h>
24 #include <boost/thread.hpp>
25 #include <boost/weak_ptr.hpp>
29 #define LO_OFFSET 4.25e6
36 /* ------------------------------------------------------------------------
37 * A few comments about the XCVR2450:
39 * It is half-duplex. I.e., transmit and receive are mutually exclusive.
40 * There is a single LO for both the Tx and Rx sides.
41 * For our purposes the board is always either receiving or transmitting.
43 * Each board is uniquely identified by the *USRP hardware* instance and side
44 * This dictionary holds a weak reference to existing board controller so it
45 * can be created or retrieved as needed.
51 #define HB_PA_OFF (1 << 15) // 5GHz PA, 1 = off, 0 = on
52 #define LB_PA_OFF (1 << 14) // 2.4GHz PA, 1 = off, 0 = on
53 #define ANTSEL_TX1_RX2 (1 << 13) // 1 = Ant 1 to TX, Ant 2 to RX
54 #define ANTSEL_TX2_RX1 (1 << 12) // 1 = Ant 2 to TX, Ant 1 to RX
55 #define TX_EN (1 << 11) // 1 = TX on, 0 = TX off
56 #define AD9515DIV (1 << 4) // 1 = Div by 3, 0 = Div by 2
58 #define TX_OE_MASK HB_PA_OFF|LB_PA_OFF|ANTSEL_TX1_RX2|ANTSEL_TX2_RX1|TX_EN|AD9515DIV
59 #define TX_SAFE_IO HB_PA_OFF|LB_PA_OFF|ANTSEL_TX1_RX2|AD9515DIV
62 #define LOCKDET (1 << 15) // This is an INPUT!!!
64 #define RX_EN (1 << 13) // 1 = RX on, 0 = RX off
65 #define RX_HP (1 << 12)
66 #define RX_OE_MASK EN|RX_EN|RX_HP
70 std::string serial_no;
73 bool operator==(const xcvr2450_key &x){
74 return x.serial_no ==serial_no && x.which == which;
81 usrp_basic *d_raw_usrp;
85 int d_spi_format, d_spi_enable;
87 int d_mimo, d_int_div, d_frac_div, d_highband, d_five_gig;
88 int d_cp_current, d_ref_div, d_rssi_hbw;
89 int d_txlpf_bw, d_rxlpf_bw, d_rxlpf_fine, d_rxvga_ser;
90 int d_rssi_range, d_rssi_mode, d_rssi_mux;
91 int d_rx_hp_pin, d_rx_hpf, d_rx_ant;
92 int d_tx_ant, d_txvga_ser, d_tx_driver_lin;
93 int d_tx_vga_lin, d_tx_upconv_lin, d_tx_bb_gain;
94 int d_pabias_delay, d_pabias, rx_rf_gain, rx_bb_gain, d_txgain;
95 int d_rx_rf_gain, d_rx_bb_gain;
97 int d_reg_standby, d_reg_int_divider, d_reg_frac_divider, d_reg_bandselpll;
98 int d_reg_cal, dsend_reg, d_reg_lpf, d_reg_rxrssi_ctrl, d_reg_txlin_gain;
99 int d_reg_pabias, d_reg_rxgain, d_reg_txgain;
103 void _set_rfagc(float gain);
104 void _set_ifagc(float gain);
105 void _set_pga(float pga_gain);
112 xcvr2450(usrp_basic_sptr usrp, int which);
116 void set_reg_standby();
118 // Integer-Divider Ratio (3)
119 void set_reg_int_divider();
121 // Fractional-Divider Ratio (4)
122 void set_reg_frac_divider();
124 // Band Select and PLL (5)
125 void set_reg_bandselpll();
130 // Lowpass Filter (7)
133 // Rx Control/RSSI (8)
134 void set_reg_rxrssi_ctrl();
136 // Tx Linearity/Baseband Gain (9)
137 void set_reg_txlin_gain();
140 void set_reg_pabias();
143 void set_reg_rxgain();
146 void set_reg_txgain();
148 // Send register write to SPI
149 void send_reg(int v);
153 bool set_rx_gain(float gain);
154 bool set_tx_gain(float gain);
156 struct freq_result_t set_freq(double target_freq);
160 /*****************************************************************************/
163 xcvr2450::xcvr2450(usrp_basic_sptr _usrp, int which)
164 : d_raw_usrp(_usrp.get()), d_which(which), d_is_shutdown(false)
166 // Handler for Tv Rx daughterboards.
168 // @param usrp: instance of usrp.source_c
169 // @param which: which side: 0, 1 corresponding to RX_A or RX_B respectively
171 // Use MSB with no header
172 d_spi_format = SPI_FMT_MSB | SPI_FMT_HDR_0;
175 d_spi_enable = SPI_ENABLE_RX_A;
178 d_spi_enable = SPI_ENABLE_RX_B;
182 d_mimo = 1; // 0 = OFF, 1 = ON
183 d_int_div = 192; // 128 = min, 255 = max
184 d_frac_div = 0; // 0 = min, 65535 = max
185 d_highband = 0; // 0 = freq <= 5.4e9, 1 = freq > 5.4e9
186 d_five_gig = 0; // 0 = freq <= 3.e9, 1 = freq > 3e9
187 d_cp_current = 1; // 0 = 2mA, 1 = 4mA
188 d_ref_div = 1; // 1 to 7
189 d_rssi_hbw = 0; // 0 = 2 MHz, 1 = 6 MHz
190 d_txlpf_bw = 1; // 1 = 12 MHz, 2 = 18 MHz, 3 = 24 MHz
191 d_rxlpf_bw = 1; // 0 = 7.5 MHz, 1 = 9.5 MHz, 2 = 14 MHz, 3 = 18 MHz
192 d_rxlpf_fine = 2; // 0 = 90%, 1 = 95%, 2 = 100%, 3 = 105%, 4 = 110%
193 d_rxvga_ser = 1; // 0 = RXVGA controlled by B7:1, 1=controlled serially
194 d_rssi_range = 1; // 0 = low range (datasheet typo), 1=high range (0.5V - 2.0V)
195 d_rssi_mode = 1; // 0 = enable follows RXHP, 1 = enabled
196 d_rssi_mux = 0; // 0 = RSSI, 1 = TEMP
197 d_rx_hp_pin = 0; // 0 = Fc set by rx_hpf, 1 = 600 KHz
198 d_rx_hpf = 0; // 0 = 100Hz, 1 = 30KHz
199 d_rx_ant = 0; // 0 = Ant. #1, 1 = Ant. #2
200 d_tx_ant = 0; // 0 = Ant. #1, 1 = Ant. #2
201 d_txvga_ser = 1; // 0 = TXVGA controlled by B6:1, 1=controlled serially
202 d_tx_driver_lin = 2; // 0=50% (worst linearity), 1=63%, 2=78%, 3=100% (best lin)
203 d_tx_vga_lin = 2; // 0=50% (worst linearity), 1=63%, 2=78%, 3=100% (best lin)
204 d_tx_upconv_lin = 2; // 0=50% (worst linearity), 1=63%, 2=78%, 3=100% (best lin)
205 d_tx_bb_gain = 3; // 0=maxgain-5dB, 1=max-3dB, 2=max-1.5dB, 3=max
206 d_pabias_delay = 15; // 0 = 0, 15 = 7uS
207 d_pabias = 0; // 0 = 0 uA, 63 = 315uA
208 d_rx_rf_gain = 0; // 0 = 0dB, 1 = 0dB, 2 = 15dB, 3 = 30dB
209 d_rx_bb_gain = 16; // 0 = min, 31 = max (0 - 62 dB)
211 d_txgain = 63; // 0 = min, 63 = max
213 // Initialize GPIO and ATR
214 usrp()->common_write_io(C_TX, d_which, TX_SAFE_IO, TX_OE_MASK);
215 usrp()->_common_write_oe(C_TX, d_which, TX_OE_MASK, 0xffff);
216 usrp()->common_write_atr_txval(C_TX, d_which, TX_SAFE_IO);
217 usrp()->common_write_atr_rxval(C_TX, d_which, TX_SAFE_IO);
218 usrp()->common_write_atr_mask(C_TX, d_which, TX_OE_MASK);
220 usrp()->common_write_io(C_RX, d_which, RX_SAFE_IO, RX_OE_MASK);
221 usrp()->_common_write_oe(C_RX, d_which, RX_OE_MASK, 0xffff);
222 usrp()->common_write_atr_txval(C_RX, d_which, RX_SAFE_IO);
223 usrp()->common_write_atr_rxval(C_RX, d_which, RX_SAFE_IO);
224 usrp()->common_write_atr_mask(C_RX, d_which, RX_OE_MASK);
226 // Initialize chipset
227 // TODO: perform reset sequence to ensure power up defaults
229 set_reg_bandselpll();
232 set_reg_rxrssi_ctrl();
233 set_reg_txlin_gain();
237 //FIXME: set_freq(2.45e9);
240 xcvr2450::~xcvr2450()
242 //printf("xcvr2450::destructor\n");
250 d_is_shutdown = true;
251 usrp()->common_write_atr_txval(C_TX, d_which, TX_SAFE_IO);
252 usrp()->common_write_atr_rxval(C_TX, d_which, TX_SAFE_IO);
253 usrp()->common_write_atr_txval(C_RX, d_which, RX_SAFE_IO);
254 usrp()->common_write_atr_rxval(C_RX, d_which, RX_SAFE_IO);
260 xcvr2450::set_reg_standby()
262 d_reg_standby = ((d_mimo<<17) |
267 send_reg(d_reg_standby);
271 xcvr2450::set_reg_int_divider()
273 d_reg_int_divider = (((d_frac_div & 0x03)<<16) |
275 send_reg(d_reg_int_divider);
279 xcvr2450::set_reg_frac_divider()
281 d_reg_frac_divider = ((d_frac_div & 0xfffc)<<2) | 4;
282 send_reg(d_reg_frac_divider);
286 xcvr2450::set_reg_bandselpll()
288 d_reg_bandselpll = ((d_mimo<<17) |
295 (d_five_gig<<4) | 5);
296 send_reg(d_reg_bandselpll);
297 d_reg_bandselpll = ((d_mimo<<17) |
304 (d_five_gig<<4) | 5);
305 send_reg(d_reg_bandselpll);
309 xcvr2450::set_reg_cal()
311 // FIXME do calibration
312 d_reg_cal = (1<<14)|6;
317 xcvr2450::set_reg_lpf()
323 (d_rxlpf_fine<<4) | 7);
328 xcvr2450::set_reg_rxrssi_ctrl()
330 d_reg_rxrssi_ctrl = ((d_rxvga_ser<<16) |
337 send_reg(d_reg_rxrssi_ctrl);
341 xcvr2450::set_reg_txlin_gain()
343 d_reg_txlin_gain = ((d_txvga_ser<<14) |
344 (d_tx_driver_lin<<12) |
346 (d_tx_upconv_lin<<6) |
347 (d_tx_bb_gain<<4) | 9);
348 send_reg(d_reg_txlin_gain);
352 xcvr2450::set_reg_pabias()
355 (d_pabias_delay<<10) |
357 send_reg(d_reg_pabias);
361 xcvr2450::set_reg_rxgain()
365 (d_rx_bb_gain<<4) | 11);
366 send_reg(d_reg_rxgain);
370 xcvr2450::set_reg_txgain()
372 d_reg_txgain = (d_txgain<<4) | 12;
373 send_reg(d_reg_txgain);
377 xcvr2450::send_reg(int v)
379 // Send 24 bits, it keeps last 18 clocked in
381 c[0] = (char)((v >> 16) & 0xff);
382 c[1] = (char)((v >> 8) & 0xff);
383 c[2] = (char)((v & 0xff));
386 usrp()->_write_spi(0, d_spi_enable, d_spi_format, s);
387 //printf("xcvr2450: Setting reg %d to %X\n", (v&15), v);
390 // ----------------------------------------------------------------
395 // We calculate four values:
397 // io_rx_while_rx: what to drive onto io_rx_* when receiving
398 // io_rx_while_tx: what to drive onto io_rx_* when transmitting
399 // io_tx_while_rx: what to drive onto io_tx_* when receiving
400 // io_tx_while_tx: what to drive onto io_tx_* when transmitting
402 // B1-B7 is ignored as gain is set serially for now.
404 int rx_hp, tx_antsel, rx_antsel, tx_pa_sel;
411 tx_antsel = ANTSEL_TX2_RX1;
413 tx_antsel = ANTSEL_TX1_RX2;
416 rx_antsel = ANTSEL_TX2_RX1;
418 rx_antsel = ANTSEL_TX1_RX2;
421 tx_pa_sel = LB_PA_OFF;
423 tx_pa_sel = HB_PA_OFF;
425 // Reset GPIO and ATR
426 // FIXME: dont set io, oe, atr mask once basic code stops overriding our settings
427 usrp()->common_write_io(C_TX, d_which, TX_SAFE_IO, TX_OE_MASK);
428 usrp()->_common_write_oe(C_TX, d_which, TX_OE_MASK, 0xffff);
429 usrp()->common_write_atr_txval(C_TX, d_which, tx_pa_sel|tx_antsel|TX_EN|AD9515DIV);
430 usrp()->common_write_atr_rxval(C_TX, d_which, HB_PA_OFF|LB_PA_OFF|rx_antsel|AD9515DIV);
431 usrp()->common_write_atr_mask(C_TX, d_which, TX_OE_MASK);
433 usrp()->common_write_io(C_RX, d_which, RX_SAFE_IO, RX_OE_MASK);
434 usrp()->_common_write_oe(C_RX, d_which, RX_OE_MASK, 0xffff);
435 usrp()->common_write_atr_txval(C_RX, d_which, EN|rx_hp);
436 usrp()->common_write_atr_rxval(C_RX, d_which, EN|rx_hp|RX_EN);
437 usrp()->common_write_atr_mask(C_RX, d_which, RX_OE_MASK);
439 //printf("GPIO: RXRX=%04X RXTX=%04X TXRX=%04X TXTX=%04X\n",
440 // io_rx_while_rx, io_rx_while_tx, io_tx_while_rx, io_tx_while_tx);
445 xcvr2450::set_freq(double target_freq)
447 struct freq_result_t args = {false, 0};
451 if(target_freq > 3e9) {
462 if(target_freq > 5.408e9) {
469 double vco_freq = target_freq*scaler;
470 double sys_clk = usrp()->fpga_master_clock_freq(); // Usually 64e6
471 double ref_clk = sys_clk / d_ad9515_div;
473 double phdet_freq = ref_clk/d_ref_div;
474 double div = vco_freq/phdet_freq;
475 d_int_div = int(floor(div));
476 d_frac_div = int((div-d_int_div)*65536.0);
477 // double actual_freq = phdet_freq*(d_int_div+(d_frac_div/65536.0))/scaler;
479 //printf("RF=%f VCO=%f R=%d PHD=%f DIV=%3.5f I=%3d F=%5d ACT=%f\n",
480 // target_freq, vco_freq, d_ref_div, phdet_freq,
481 // div, d_int_div, d_frac_div, actual_freq);
484 set_reg_int_divider();
485 set_reg_frac_divider();
486 set_reg_bandselpll();
488 args.ok = lock_detect();
490 args.baseband_freq = target_freq;
492 args.baseband_freq = actual_freq;
496 printf("Fail %f\n", target_freq);
502 xcvr2450::lock_detect()
505 @returns: the value of the VCO/PLL lock detect bit.
508 if(usrp()->common_read_io(C_RX, d_which) & LOCKDET) {
511 else { // Give it a second chance
512 if(usrp()->common_read_io(C_RX, d_which) & LOCKDET)
520 xcvr2450::set_rx_gain(float gain)
527 // Split the gain between RF and baseband
528 // This is experimental, not prescribed
530 d_rx_rf_gain = 0; // 0 dB RF gain
531 rx_bb_gain = int(gain/2.0);
534 if(gain >= 30.0 and gain < 60.5) {
535 d_rx_rf_gain = 2; // 15 dB RF gain
536 d_rx_bb_gain = int((gain-15.0)/2.0);
540 d_rx_rf_gain = 3; // 30.5 dB RF gain
541 d_rx_bb_gain = int((gain-30.5)/2.0);
550 xcvr2450::set_tx_gain(float gain)
559 d_txgain = int((gain/30.0)*63);
566 /*****************************************************************************/
569 struct xcvr2450_table_entry {
571 boost::weak_ptr<xcvr2450> value;
573 xcvr2450_table_entry(const xcvr2450_key &_key, boost::weak_ptr<xcvr2450> _value)
574 : key(_key), value(_value) {}
577 typedef std::vector<xcvr2450_table_entry> xcvr2450_table;
579 static boost::mutex s_table_mutex;
580 static xcvr2450_table s_table;
583 _get_or_make_xcvr2450(usrp_basic_sptr usrp, int which)
585 xcvr2450_key key = {usrp->serial_number(), which};
587 boost::mutex::scoped_lock guard(s_table_mutex);
589 for (xcvr2450_table::iterator p = s_table.begin(); p != s_table.end();){
590 if (p->value.expired()) // weak pointer is now dead
591 p = s_table.erase(p); // erase it
593 if (key == p->key){ // found it
594 return xcvr2450_sptr(p->value);
601 // We don't have the xcvr2450 we're looking for
603 // create a new one and stick it in the table.
604 xcvr2450_sptr r(new xcvr2450(usrp, which));
605 xcvr2450_table_entry t(key, r);
606 s_table.push_back(t);
612 /*****************************************************************************/
615 db_xcvr2450_base::db_xcvr2450_base(usrp_basic_sptr usrp, int which)
616 : db_base(usrp, which)
619 * Abstract base class for all xcvr2450 boards.
621 * Derive board specific subclasses from db_xcvr2450_base_{tx,rx}
623 * @param usrp: instance of usrp.source_c
624 * @param which: which side: 0 or 1 corresponding to side A or B respectively
628 d_xcvr = _get_or_make_xcvr2450(usrp, which);
631 db_xcvr2450_base::~db_xcvr2450_base()
636 db_xcvr2450_base::shutdown_common()
638 // If the usrp_basic in the xcvr2450 is the same as the usrp_basic
639 // in the daughterboard, shutdown the xcvr now (when only one of Tx
640 // and Rx is open, this is always true).
642 if (d_xcvr->usrp() == usrp()){
643 //std::cerr << "db_xcvr2450_base::shutdown_common: same -> shutting down\n";
647 //std::cerr << "db_xcvr2450_base::shutdown_common: different -> ignoring\n";
652 db_xcvr2450_base::set_freq(double target_freq)
655 * @returns (ok, actual_baseband_freq) where:
656 * ok is True or False and indicates success or failure,
657 * actual_baseband_freq is the RF frequency that corresponds to DC in the IF.
659 return d_xcvr->set_freq(target_freq+d_lo_offset);
663 db_xcvr2450_base::is_quadrature()
666 * Return True if this board requires both I & Q analog channels.
668 * This bit of info is useful when setting up the USRP Rx mux register.
674 db_xcvr2450_base::freq_min()
680 db_xcvr2450_base::freq_max()
686 /******************************************************************************/
689 db_xcvr2450_tx::db_xcvr2450_tx(usrp_basic_sptr usrp, int which)
690 : db_xcvr2450_base(usrp, which)
692 set_lo_offset(LO_OFFSET);
693 //printf("db_xcvr2450_tx::db_xcvr2450_tx\n");
696 db_xcvr2450_tx::~db_xcvr2450_tx()
702 db_xcvr2450_tx::shutdown()
705 d_is_shutdown = true;
711 db_xcvr2450_tx::gain_min()
717 db_xcvr2450_tx::gain_max()
723 db_xcvr2450_tx::gain_db_per_step()
729 db_xcvr2450_tx::set_gain(float gain)
731 return d_xcvr->set_tx_gain(gain);
735 db_xcvr2450_tx::i_and_q_swapped()
741 /******************************************************************************/
744 db_xcvr2450_rx::db_xcvr2450_rx(usrp_basic_sptr usrp, int which)
745 : db_xcvr2450_base(usrp, which)
748 * @param usrp: instance of usrp.source_c
749 * @param which: 0 or 1 corresponding to side RX_A or RX_B respectively.
751 set_lo_offset(LO_OFFSET);
752 //printf("db_xcvr2450_rx:d_xcvr_2450_rx\n");
755 db_xcvr2450_rx::~db_xcvr2450_rx()
761 db_xcvr2450_rx::shutdown()
764 d_is_shutdown = true;
770 db_xcvr2450_rx::gain_min()
776 db_xcvr2450_rx::gain_max()
782 db_xcvr2450_rx::gain_db_per_step()
788 db_xcvr2450_rx::set_gain(float gain)
790 return d_xcvr->set_rx_gain(gain);