2 // Copyright 2008 Free Software Foundation, Inc.
4 // This file is part of GNU Radio
6 // GNU Radio is free software; you can redistribute it and/or modify
7 // it under the terms of the GNU General Public License as published by
8 // the Free Software Foundation; either asversion 3, or (at your option)
11 // GNU Radio is distributed in the hope that it will be useful,
12 // but WITHOUT ANY WARRANTY; without even the implied warranty of
13 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 // GNU General Public License for more details.
16 // You should have received a copy of the GNU General Public License
17 // along with GNU Radio; see the file COPYING. If not, write to
18 // the Free Software Foundation, Inc., 51 Franklin Street,
19 // Boston, MA 02110-1301, USA.
21 #include <db_flexrf.h>
22 #include <db_base_impl.h>
24 // d'board i/o pin defs
25 // Tx and Rx have shared defs, but different i/o regs
26 #define AUX_RXAGC (1 << 8)
27 #define POWER_UP (1 << 7) // enables power supply
28 #define RX_TXN (1 << 6) // Tx only: T/R antenna switch for TX/RX port
29 #define RX2_RX1N (1 << 6) // Rx only: antenna switch between RX2 and TX/RX port
30 #define ENABLE (1 << 5) // enables mixer
31 #define AUX_SEN (1 << 4)
32 #define AUX_SCLK (1 << 3)
33 #define PLL_LOCK_DETECT (1 << 2)
34 #define AUX_SDO (1 << 1)
35 #define CLOCK_OUT (1 << 0)
37 flexrf_base::flexrf_base(usrp_basic_sptr _usrp, int which, int _power_on)
38 : db_base(_usrp, which), d_power_on(_power_on)
41 @param usrp: instance of usrp.source_c
42 @param which: which side: 0 or 1 corresponding to side A or B respectively
47 d_spi_format = SPI_FMT_MSB | SPI_FMT_HDR_0;
49 usrp()->_write_oe(d_which, 0, 0xffff); // turn off all outputs
50 _enable_refclk(false); // disable refclk
55 flexrf_base::~flexrf_base()
61 flexrf_base::_write_all(int R, int control, int N)
64 Write R counter latch, control latch and N counter latch to VCO.
66 Adds 10ms delay between writing control and N if this is first call.
67 This is the required power-up sequence.
69 @param R: 24-bit R counter latch
71 @param control: 24-bit control latch
73 @param N: 24-bit N counter latch
81 _write_control(control);
91 flexrf_base::_write_control(int control)
93 _write_it((control & ~0x3) | 0);
97 flexrf_base::_write_R(int R)
99 _write_it((R & ~0x3) | 1);
103 flexrf_base::_write_N(int N)
105 _write_it((N & ~0x3) | 2);
109 flexrf_base::_write_it(int v)
112 s[0] = (char)((v >> 16) & 0xff);
113 s[1] = (char)((v >> 8) & 0xff);
114 s[2] = (char)(v & 0xff);
115 std::string str(s, 3);
116 usrp()->_write_spi(0, d_spi_enable, d_spi_format, str);
120 flexrf_base::_lock_detect()
123 @returns: the value of the VCO/PLL lock detect bit.
126 if(usrp()->read_io(d_which) & PLL_LOCK_DETECT) {
129 else { // Give it a second chance
130 // FIXME: make portable sleep
133 t.tv_nsec = 100000000;
136 if(usrp()->read_io(d_which) & PLL_LOCK_DETECT) {
146 flexrf_base::_compute_regs(double freq, int &retR, int &retcontrol,
147 int &retN, double &retfreq)
150 Determine values of R, control, and N registers, along with actual freq.
152 @param freq: target frequency in Hz
154 @returns: (R, control, N, actual_freq)
155 @rtype: tuple(int, int, int, float)
157 Override this in derived classes.
160 //raise NotImplementedError;
161 throw std::runtime_error("_compute_regs called from flexrf_base\n");
165 flexrf_base::_compute_control_reg()
167 return d_common->_compute_control_reg();
171 flexrf_base::_refclk_divisor()
173 return d_common->_refclk_divisor();
177 flexrf_base::_refclk_freq()
179 return 64e6/_refclk_divisor();
183 flexrf_base::set_freq(double freq)
186 @returns (ok, actual_baseband_freq) where:
187 ok is True or False and indicates success or failure,
188 actual_baseband_freq is the RF frequency that corresponds to DC in the IF.
191 struct freq_result_t args = {false, 0};
193 // Offsetting the LO helps get the Tx carrier leakage out of the way.
194 // This also ensures that on Rx, we're not getting hosed by the
195 // FPGA's DC removal loop's time constant. We were seeing a
196 // problem when running with discontinuous transmission.
197 // Offsetting the LO made the problem go away.
202 _compute_regs(freq, R, control, N, actual_freq);
208 _write_all(R, control, N);
209 args.ok = _lock_detect();
210 args.baseband_freq = actual_freq;
215 flexrf_base::_set_pga(float pga_gain)
218 usrp()->set_pga(0, pga_gain);
219 usrp()->set_pga(1, pga_gain);
222 usrp()->set_pga(2, pga_gain);
223 usrp()->set_pga(3, pga_gain);
229 flexrf_base::is_quadrature()
232 Return True if this board requires both I & Q analog channels.
234 This bit of info is useful when setting up the USRP Rx mux register.
240 flexrf_base::freq_min()
242 return d_common->freq_min();
246 flexrf_base::freq_max()
248 return d_common->freq_max();
251 // ----------------------------------------------------------------
253 flexrf_base_tx::flexrf_base_tx(usrp_basic_sptr _usrp, int which, int _power_on)
254 : flexrf_base(_usrp, which, _power_on)
257 @param usrp: instance of usrp.sink_c
258 @param which: 0 or 1 corresponding to side TX_A or TX_B respectively.
262 d_spi_enable = SPI_ENABLE_TX_A;
265 d_spi_enable = SPI_ENABLE_TX_B;
268 // power up the transmit side, but don't enable the mixer
269 usrp()->_write_oe(d_which,(POWER_UP|RX_TXN|ENABLE), 0xffff);
270 usrp()->write_io(d_which, (power_on()|RX_TXN), (POWER_UP|RX_TXN|ENABLE));
273 set_gain((gain_min() + gain_max()) / 2.0); // initialize gain
276 flexrf_base_tx::~flexrf_base_tx()
283 flexrf_base_tx::shutdown()
285 // fprintf(stderr, "flexrf_base_tx::shutdown d_is_shutdown = %d\n", d_is_shutdown);
288 d_is_shutdown = true;
289 // do whatever there is to do to shutdown
291 // Power down and leave the T/R switch in the R position
292 usrp()->write_io(d_which, (power_off()|RX_TXN), (POWER_UP|RX_TXN|ENABLE));
294 // Power down VCO/PLL
297 _write_control(_compute_control_reg());
298 _enable_refclk(false); // turn off refclk
304 flexrf_base_tx::set_auto_tr(bool on)
308 ok &= set_atr_mask (RX_TXN | ENABLE);
309 ok &= set_atr_txval(0 | ENABLE);
310 ok &= set_atr_rxval(RX_TXN | 0);
313 ok &= set_atr_mask (0);
314 ok &= set_atr_txval(0);
315 ok &= set_atr_rxval(0);
321 flexrf_base_tx::set_enable(bool on)
324 Enable transmitter if on is true
328 int mask = RX_TXN | ENABLE;
335 return usrp()->write_io(d_which, v, mask);
339 flexrf_base_tx::gain_min()
341 return usrp()->pga_max();
345 flexrf_base_tx::gain_max()
347 return usrp()->pga_max();
351 flexrf_base_tx::gain_db_per_step()
357 flexrf_base_tx::set_gain(float gain)
362 @param gain: gain in decibels
365 return _set_pga(usrp()->pga_max());
369 /**************************************************************************/
372 flexrf_base_rx::flexrf_base_rx(usrp_basic_sptr _usrp, int which, int _power_on)
373 : flexrf_base(_usrp, which, _power_on)
376 @param usrp: instance of usrp.source_c
377 @param which: 0 or 1 corresponding to side RX_A or RX_B respectively.
381 d_spi_enable = SPI_ENABLE_RX_A;
384 d_spi_enable = SPI_ENABLE_RX_B;
387 usrp()->_write_oe(d_which, (POWER_UP|RX2_RX1N|ENABLE), 0xffff);
388 usrp()->write_io(d_which, (power_on()|RX2_RX1N|ENABLE),
389 (POWER_UP|RX2_RX1N|ENABLE));
391 // set up for RX on TX/RX port
392 select_rx_antenna("TX/RX");
394 bypass_adc_buffers(true);
399 flexrf_base_rx::~flexrf_base_rx()
405 flexrf_base_rx::shutdown()
407 // fprintf(stderr, "flexrf_base_rx::shutdown d_is_shutdown = %d\n", d_is_shutdown);
410 d_is_shutdown = true;
411 // do whatever there is to do to shutdown
414 usrp()->common_write_io(C_RX, d_which, power_off(), (POWER_UP|ENABLE));
416 // Power down VCO/PLL
420 // fprintf(stderr, "flexrf_base_rx::shutdown before _write_control\n");
421 _write_control(_compute_control_reg());
423 // fprintf(stderr, "flexrf_base_rx::shutdown before _enable_refclk\n");
424 _enable_refclk(false); // turn off refclk
426 // fprintf(stderr, "flexrf_base_rx::shutdown before set_auto_tr\n");
429 // fprintf(stderr, "flexrf_base_rx::shutdown after set_auto_tr\n");
434 flexrf_base_rx::set_auto_tr(bool on)
438 ok &= set_atr_mask (ENABLE);
439 ok &= set_atr_txval( 0);
440 ok &= set_atr_rxval(ENABLE);
443 ok &= set_atr_mask (0);
444 ok &= set_atr_txval(0);
445 ok &= set_atr_rxval(0);
451 flexrf_base_rx::select_rx_antenna(int which_antenna)
454 Specify which antenna port to use for reception.
455 @param which_antenna: either 'TX/RX' or 'RX2'
458 if(which_antenna == 0) {
459 usrp()->write_io(d_which, 0,RX2_RX1N);
461 else if(which_antenna == 1) {
462 usrp()->write_io(d_which, RX2_RX1N, RX2_RX1N);
466 // throw std::invalid_argument("which_antenna must be either 'TX/RX' or 'RX2'\n");
472 flexrf_base_rx::select_rx_antenna(const std::string &which_antenna)
475 Specify which antenna port to use for reception.
476 @param which_antenna: either 'TX/RX' or 'RX2'
479 if(which_antenna == "TX/RX") {
480 usrp()->write_io(d_which, 0, RX2_RX1N);
482 else if(which_antenna == "RX2") {
483 usrp()->write_io(d_which, RX2_RX1N, RX2_RX1N);
486 // throw std::invalid_argument("which_antenna must be either 'TX/RX' or 'RX2'\n");
493 flexrf_base_rx::set_gain(float gain)
498 @param gain: gain in decibels
503 gain = std::max(gain_min(), std::min(gain, gain_max()));
505 float pga_gain, agc_gain;
506 float V_maxgain, V_mingain, V_fullscale, dac_value;
508 float maxgain = gain_max() - usrp()->pga_max();
509 float mingain = gain_min();
511 pga_gain = gain-maxgain;
512 assert(pga_gain <= usrp()->pga_max());
523 dac_value = (agc_gain*(V_maxgain-V_mingain)/(maxgain-mingain) + V_mingain)*4096/V_fullscale;
525 assert(dac_value>=0 && dac_value<4096);
527 return (usrp()->write_aux_dac(d_which, 0, int(dac_value))
528 && _set_pga(int(pga_gain)));
531 // ----------------------------------------------------------------
534 _AD4360_common::_AD4360_common()
536 // R-Register Common Values
537 d_R_RSV = 0; // bits 23,22
538 d_BSC = 3; // bits 21,20 Div by 8 to be safe
539 d_TEST = 0; // bit 19
541 d_ABP = 0; // bit 17,16 3ns
543 // N-Register Common Values
544 d_N_RSV = 0; // bit 7
546 // Control Register Common Values
547 d_PD = 0; // bits 21,20 Normal operation
548 d_PL = 0; // bits 13,12 11mA
549 d_MTLD = 1; // bit 11 enabled
550 d_CPG = 0; // bit 10 CP setting 1
551 d_CP3S = 0; // bit 9 Normal
552 d_PDP = 1; // bit 8 Positive
553 d_MUXOUT = 1; // bits 7:5 Digital Lock Detect
554 d_CR = 0; // bit 4 Normal
555 d_PC = 1; // bits 3,2 Core power 10mA
558 _AD4360_common::~_AD4360_common()
563 _AD4360_common::_compute_regs(double refclk_freq, double freq, int &retR,
564 int &retcontrol, int &retN, double &retfreq)
567 Determine values of R, control, and N registers, along with actual freq.
569 @param freq: target frequency in Hz
571 @returns: (R, control, N, actual_freq)
572 @rtype: tuple(int, int, int, float)
575 // Band-specific N-Register Values
576 //float phdet_freq = _refclk_freq()/d_R_DIV;
577 double phdet_freq = refclk_freq/d_R_DIV;
578 double desired_n = round(freq*d_freq_mult/phdet_freq);
579 double actual_freq = desired_n * phdet_freq;
580 int B = floor(desired_n/_prescaler());
581 int A = desired_n - _prescaler()*B;
582 d_B_DIV = int(B); // bits 20:8
583 d_A_DIV = int(A); // bit 6:2
585 //assert db_B_DIV >= db_A_DIV
586 if(d_B_DIV < d_A_DIV) {
594 int R = (d_R_RSV<<22) | (d_BSC<<20) | (d_TEST<<19) |
595 (d_LDP<<18) | (d_ABP<<16) | (d_R_DIV<<2);
597 int control = _compute_control_reg();
599 int N = (d_DIVSEL<<23) | (d_DIV2<<22) | (d_CPGAIN<<21) |
600 (d_B_DIV<<8) | (d_N_RSV<<7) | (d_A_DIV<<2);
603 retcontrol = control;
605 retfreq = actual_freq/d_freq_mult;
610 _AD4360_common::_compute_control_reg()
612 int control = (d_P<<22) | (d_PD<<20) | (d_CP2<<17) | (d_CP1<<14)
613 | (d_PL<<12) | (d_MTLD<<11) | (d_CPG<<10) | (d_CP3S<<9) | (d_PDP<<8)
614 | (d_MUXOUT<<5) | (d_CR<<4) | (d_PC<<2);
620 _AD4360_common::_refclk_divisor()
623 Return value to stick in REFCLK_DIVISOR register
629 _AD4360_common::_prescaler()
642 //----------------------------------------------------------------------
644 _2400_common::_2400_common()
647 // Band-specific R-Register Values
648 d_R_DIV = 16; // bits 15:2
650 // Band-specific C-Register values
651 d_P = 1; // bits 23,22 Div by 16/17
652 d_CP2 = 7; // bits 19:17
653 d_CP1 = 7; // bits 16:14
655 // Band specifc N-Register Values
656 d_DIVSEL = 0; // bit 23
657 d_DIV2 = 0; // bit 22
658 d_CPGAIN = 0; // bit 21
663 _2400_common::freq_min()
669 _2400_common::freq_max()
674 //----------------------------------------------------------------------
676 _1200_common::_1200_common()
679 // Band-specific R-Register Values
680 d_R_DIV = 16; // bits 15:2 DIV by 16 for a 1 MHz phase detector freq
682 // Band-specific C-Register values
683 d_P = 1; // bits 23,22 Div by 16/17
684 d_CP2 = 7; // bits 19:17 1.25 mA
685 d_CP1 = 7; // bits 16:14 1.25 mA
687 // Band specifc N-Register Values
688 d_DIVSEL = 0; // bit 23
689 d_DIV2 = 1; // bit 22
690 d_CPGAIN = 0; // bit 21
695 _1200_common::freq_min()
701 _1200_common::freq_max()
706 //-------------------------------------------------------------------------
708 _1800_common::_1800_common()
711 // Band-specific R-Register Values
712 d_R_DIV = 16; // bits 15:2 DIV by 16 for a 1 MHz phase detector freq
714 // Band-specific C-Register values
715 d_P = 1; // bits 23,22 Div by 16/17
716 d_CP2 = 7; // bits 19:17 1.25 mA
717 d_CP1 = 7; // bits 16:14 1.25 mA
719 // Band specifc N-Register Values
720 d_DIVSEL = 0; // bit 23
721 d_DIV2 = 0; // bit 22
723 d_CPGAIN = 0; // bit 21
727 _1800_common::freq_min()
733 _1800_common::freq_max()
738 //-------------------------------------------------------------------------
740 _900_common::_900_common()
743 // Band-specific R-Register Values
744 d_R_DIV = 16; // bits 15:2 DIV by 16 for a 1 MHz phase detector freq
746 // Band-specific C-Register values
747 d_P = 1; // bits 23,22 Div by 16/17
748 d_CP2 = 7; // bits 19:17 1.25 mA
749 d_CP1 = 7; // bits 16:14 1.25 mA
751 // Band specifc N-Register Values
752 d_DIVSEL = 0; // bit 23
753 d_DIV2 = 1; // bit 22
755 d_CPGAIN = 0; // bit 21
759 _900_common::freq_min()
765 _900_common::freq_max()
770 //-------------------------------------------------------------------------
772 _400_common::_400_common()
775 // Band-specific R-Register Values
776 d_R_DIV = 16; // bits 15:2
778 // Band-specific C-Register values
779 d_P = 0; // bits 23,22 Div by 8/9
780 d_CP2 = 7; // bits 19:17 1.25 mA
781 d_CP1 = 7; // bits 16:14 1.25 mA
783 // Band specifc N-Register Values These are different for TX/RX
784 d_DIVSEL = 0; // bit 23
787 d_CPGAIN = 0; // bit 21
791 _400_common::freq_min()
797 _400_common::freq_max()
805 d_DIV2 = 1; // bit 22
811 d_DIV2 = 0; // bit 22 // RX side has built-in DIV2 in AD8348
814 //------------------------------------------------------------
816 db_flexrf_2400_tx::db_flexrf_2400_tx(usrp_basic_sptr usrp, int which)
817 : flexrf_base_tx(usrp, which)
819 d_common = new _2400_common();
822 db_flexrf_2400_tx::~db_flexrf_2400_tx()
827 db_flexrf_2400_tx::_compute_regs(double freq, int &retR, int &retcontrol,
828 int &retN, double &retfreq)
830 return d_common->_compute_regs(_refclk_freq(), freq, retR,
831 retcontrol, retN, retfreq);
836 db_flexrf_2400_rx::db_flexrf_2400_rx(usrp_basic_sptr usrp, int which)
837 : flexrf_base_rx(usrp, which)
839 d_common = new _2400_common();
840 set_gain((gain_min() + gain_max()) / 2.0); // initialize gain
843 db_flexrf_2400_rx::~db_flexrf_2400_rx()
848 db_flexrf_2400_rx::gain_min()
850 return usrp()->pga_min();
854 db_flexrf_2400_rx::gain_max()
856 return usrp()->pga_max()+70;
860 db_flexrf_2400_rx::gain_db_per_step()
867 db_flexrf_2400_rx::i_and_q_swapped()
873 db_flexrf_2400_rx::_compute_regs(double freq, int &retR, int &retcontrol,
874 int &retN, double &retfreq)
876 return d_common->_compute_regs(_refclk_freq(), freq, retR,
877 retcontrol, retN, retfreq);
880 //------------------------------------------------------------
883 db_flexrf_1200_tx::db_flexrf_1200_tx(usrp_basic_sptr usrp, int which)
884 : flexrf_base_tx(usrp, which)
886 d_common = new _1200_common();
889 db_flexrf_1200_tx::~db_flexrf_1200_tx()
894 db_flexrf_1200_tx::_compute_regs(double freq, int &retR, int &retcontrol,
895 int &retN, double &retfreq)
897 return d_common->_compute_regs(_refclk_freq(), freq, retR,
898 retcontrol, retN, retfreq);
904 db_flexrf_1200_rx::db_flexrf_1200_rx(usrp_basic_sptr usrp, int which)
905 : flexrf_base_rx(usrp, which)
907 d_common = new _1200_common();
908 set_gain((gain_min() + gain_max()) / 2.0); // initialize gain
911 db_flexrf_1200_rx::~db_flexrf_1200_rx()
916 db_flexrf_1200_rx::gain_min()
918 return usrp()->pga_min();
922 db_flexrf_1200_rx::gain_max()
924 return usrp()->pga_max()+70;
928 db_flexrf_1200_rx::gain_db_per_step()
934 db_flexrf_1200_rx::i_and_q_swapped()
940 db_flexrf_1200_rx::_compute_regs(double freq, int &retR, int &retcontrol,
941 int &retN, double &retfreq)
943 return d_common->_compute_regs(_refclk_freq(), freq, retR,
944 retcontrol, retN, retfreq);
948 //------------------------------------------------------------
951 db_flexrf_1800_tx::db_flexrf_1800_tx(usrp_basic_sptr usrp, int which)
952 : flexrf_base_tx(usrp, which)
954 d_common = new _1800_common();
957 db_flexrf_1800_tx::~db_flexrf_1800_tx()
962 db_flexrf_1800_tx::_compute_regs(double freq, int &retR, int &retcontrol,
963 int &retN, double &retfreq)
965 return d_common->_compute_regs(_refclk_freq(), freq, retR,
966 retcontrol, retN, retfreq);
971 db_flexrf_1800_rx::db_flexrf_1800_rx(usrp_basic_sptr usrp, int which)
972 : flexrf_base_rx(usrp, which)
974 d_common = new _1800_common();
975 set_gain((gain_min() + gain_max()) / 2.0); // initialize gain
978 db_flexrf_1800_rx::~db_flexrf_1800_rx()
984 db_flexrf_1800_rx::gain_min()
986 return usrp()->pga_min();
990 db_flexrf_1800_rx::gain_max()
992 return usrp()->pga_max()+70;
996 db_flexrf_1800_rx::gain_db_per_step()
1002 db_flexrf_1800_rx::i_and_q_swapped()
1008 db_flexrf_1800_rx::_compute_regs(double freq, int &retR, int &retcontrol,
1009 int &retN, double &retfreq)
1011 return d_common->_compute_regs(_refclk_freq(), freq, retR,
1012 retcontrol, retN, retfreq);
1016 //------------------------------------------------------------
1019 db_flexrf_900_tx::db_flexrf_900_tx(usrp_basic_sptr usrp, int which)
1020 : flexrf_base_tx(usrp, which)
1022 d_common = new _900_common();
1025 db_flexrf_900_tx::~db_flexrf_900_tx()
1030 db_flexrf_900_tx::_compute_regs(double freq, int &retR, int &retcontrol,
1031 int &retN, double &retfreq)
1033 return d_common->_compute_regs(_refclk_freq(), freq, retR,
1034 retcontrol, retN, retfreq);
1038 db_flexrf_900_rx::db_flexrf_900_rx(usrp_basic_sptr usrp, int which)
1039 : flexrf_base_rx(usrp, which)
1041 d_common = new _900_common();
1042 set_gain((gain_min() + gain_max()) / 2.0); // initialize gain
1045 db_flexrf_900_rx::~db_flexrf_900_rx()
1050 db_flexrf_900_rx::gain_min()
1052 return usrp()->pga_min();
1056 db_flexrf_900_rx::gain_max()
1058 return usrp()->pga_max()+70;
1062 db_flexrf_900_rx::gain_db_per_step()
1068 db_flexrf_900_rx::i_and_q_swapped()
1074 db_flexrf_900_rx::_compute_regs(double freq, int &retR, int &retcontrol,
1075 int &retN, double &retfreq)
1077 return d_common->_compute_regs(_refclk_freq(), freq, retR,
1078 retcontrol, retN, retfreq);
1081 //------------------------------------------------------------
1084 db_flexrf_400_tx::db_flexrf_400_tx(usrp_basic_sptr usrp, int which)
1085 : flexrf_base_tx(usrp, which, POWER_UP)
1087 d_common = new _400_tx();
1090 db_flexrf_400_tx::~db_flexrf_400_tx()
1095 db_flexrf_400_tx::_compute_regs(double freq, int &retR, int &retcontrol,
1096 int &retN, double &retfreq)
1098 return d_common->_compute_regs(_refclk_freq(), freq, retR,
1099 retcontrol, retN, retfreq);
1104 db_flexrf_400_rx::db_flexrf_400_rx(usrp_basic_sptr usrp, int which)
1105 : flexrf_base_rx(usrp, which, POWER_UP)
1107 d_common = new _400_rx();
1108 set_gain((gain_min() + gain_max()) / 2.0); // initialize gain
1111 db_flexrf_400_rx::~db_flexrf_400_rx()
1116 db_flexrf_400_rx::gain_min()
1118 return usrp()->pga_min();
1122 db_flexrf_400_rx::gain_max()
1124 return usrp()->pga_max()+45;
1129 db_flexrf_400_rx::gain_db_per_step()
1136 db_flexrf_400_rx::i_and_q_swapped()
1142 db_flexrf_400_rx::_compute_regs(double freq, int &retR, int &retcontrol,
1143 int &retN, double &retfreq)
1145 return d_common->_compute_regs(_refclk_freq(), freq, retR,
1146 retcontrol, retN, retfreq);