2 // Copyright 2008,2009 Free Software Foundation, Inc.
4 // This file is part of GNU Radio
6 // GNU Radio is free software; you can redistribute it and/or modify
7 // it under the terms of the GNU General Public License as published by
8 // the Free Software Foundation; either asversion 3, or (at your option)
11 // GNU Radio is distributed in the hope that it will be useful,
12 // but WITHOUT ANY WARRANTY; without even the implied warranty of
13 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 // GNU General Public License for more details.
16 // You should have received a copy of the GNU General Public License
17 // along with GNU Radio; see the file COPYING. If not, write to
18 // the Free Software Foundation, Inc., 51 Franklin Street,
19 // Boston, MA 02110-1301, USA.
25 #include <usrp/db_xcvr2450.h>
26 #include <db_base_impl.h>
28 #include <boost/thread.hpp>
29 #include <boost/weak_ptr.hpp>
33 #define LO_OFFSET 4.25e6
40 /* ------------------------------------------------------------------------
41 * A few comments about the XCVR2450:
43 * It is half-duplex. I.e., transmit and receive are mutually exclusive.
44 * There is a single LO for both the Tx and Rx sides.
45 * For our purposes the board is always either receiving or transmitting.
47 * Each board is uniquely identified by the *USRP hardware* instance and side
48 * This dictionary holds a weak reference to existing board controller so it
49 * can be created or retrieved as needed.
55 #define HB_PA_OFF (1 << 15) // 5GHz PA, 1 = off, 0 = on
56 #define LB_PA_OFF (1 << 14) // 2.4GHz PA, 1 = off, 0 = on
57 #define ANTSEL_TX1_RX2 (1 << 13) // 1 = Ant 1 to TX, Ant 2 to RX
58 #define ANTSEL_TX2_RX1 (1 << 12) // 1 = Ant 2 to TX, Ant 1 to RX
59 #define TX_EN (1 << 11) // 1 = TX on, 0 = TX off
60 #define AD9515DIV (1 << 4) // 1 = Div by 3, 0 = Div by 2
62 #define TX_OE_MASK HB_PA_OFF|LB_PA_OFF|ANTSEL_TX1_RX2|ANTSEL_TX2_RX1|TX_EN|AD9515DIV
63 #define TX_SAFE_IO HB_PA_OFF|LB_PA_OFF|ANTSEL_TX1_RX2|AD9515DIV
66 #define LOCKDET (1 << 15) // This is an INPUT!!!
68 #define RX_EN (1 << 13) // 1 = RX on, 0 = RX off
69 #define RX_HP (1 << 12)
70 #define RX_OE_MASK EN|RX_EN|RX_HP
74 std::string serial_no;
77 bool operator==(const xcvr2450_key &x){
78 return x.serial_no ==serial_no && x.which == which;
85 usrp_basic *d_raw_usrp;
89 int d_spi_format, d_spi_enable;
91 int d_mimo, d_int_div, d_frac_div, d_highband, d_five_gig;
92 int d_cp_current, d_ref_div, d_rssi_hbw;
93 int d_txlpf_bw, d_rxlpf_bw, d_rxlpf_fine, d_rxvga_ser;
94 int d_rssi_range, d_rssi_mode, d_rssi_mux;
95 int d_rx_hp_pin, d_rx_hpf, d_rx_ant;
96 int d_tx_ant, d_txvga_ser, d_tx_driver_lin;
97 int d_tx_vga_lin, d_tx_upconv_lin, d_tx_bb_gain;
98 int d_pabias_delay, d_pabias, rx_rf_gain, rx_bb_gain, d_txgain;
99 int d_rx_rf_gain, d_rx_bb_gain;
101 int d_reg_standby, d_reg_int_divider, d_reg_frac_divider, d_reg_bandselpll;
102 int d_reg_cal, dsend_reg, d_reg_lpf, d_reg_rxrssi_ctrl, d_reg_txlin_gain;
103 int d_reg_pabias, d_reg_rxgain, d_reg_txgain;
107 void _set_rfagc(float gain);
108 void _set_ifagc(float gain);
109 void _set_pga(float pga_gain);
116 xcvr2450(usrp_basic_sptr usrp, int which);
120 void set_reg_standby();
122 // Integer-Divider Ratio (3)
123 void set_reg_int_divider();
125 // Fractional-Divider Ratio (4)
126 void set_reg_frac_divider();
128 // Band Select and PLL (5)
129 void set_reg_bandselpll();
134 // Lowpass Filter (7)
137 // Rx Control/RSSI (8)
138 void set_reg_rxrssi_ctrl();
140 // Tx Linearity/Baseband Gain (9)
141 void set_reg_txlin_gain();
144 void set_reg_pabias();
147 void set_reg_rxgain();
150 void set_reg_txgain();
152 // Send register write to SPI
153 void send_reg(int v);
157 bool set_rx_gain(float gain);
158 bool set_tx_gain(float gain);
160 struct freq_result_t set_freq(double target_freq);
164 /*****************************************************************************/
167 xcvr2450::xcvr2450(usrp_basic_sptr _usrp, int which)
168 : d_raw_usrp(_usrp.get()), d_which(which), d_is_shutdown(false)
170 // Handler for Tv Rx daughterboards.
172 // @param usrp: instance of usrp.source_c
173 // @param which: which side: 0, 1 corresponding to RX_A or RX_B respectively
175 // Use MSB with no header
176 d_spi_format = SPI_FMT_MSB | SPI_FMT_HDR_0;
179 d_spi_enable = SPI_ENABLE_RX_A;
182 d_spi_enable = SPI_ENABLE_RX_B;
186 d_mimo = 1; // 0 = OFF, 1 = ON
187 d_int_div = 192; // 128 = min, 255 = max
188 d_frac_div = 0; // 0 = min, 65535 = max
189 d_highband = 0; // 0 = freq <= 5.4e9, 1 = freq > 5.4e9
190 d_five_gig = 0; // 0 = freq <= 3.e9, 1 = freq > 3e9
191 d_cp_current = 1; // 0 = 2mA, 1 = 4mA
192 d_ref_div = 1; // 1 to 7
193 d_rssi_hbw = 0; // 0 = 2 MHz, 1 = 6 MHz
194 d_txlpf_bw = 1; // 1 = 12 MHz, 2 = 18 MHz, 3 = 24 MHz
195 d_rxlpf_bw = 1; // 0 = 7.5 MHz, 1 = 9.5 MHz, 2 = 14 MHz, 3 = 18 MHz
196 d_rxlpf_fine = 2; // 0 = 90%, 1 = 95%, 2 = 100%, 3 = 105%, 4 = 110%
197 d_rxvga_ser = 1; // 0 = RXVGA controlled by B7:1, 1=controlled serially
198 d_rssi_range = 1; // 0 = low range (datasheet typo), 1=high range (0.5V - 2.0V)
199 d_rssi_mode = 1; // 0 = enable follows RXHP, 1 = enabled
200 d_rssi_mux = 0; // 0 = RSSI, 1 = TEMP
201 d_rx_hp_pin = 0; // 0 = Fc set by rx_hpf, 1 = 600 KHz
202 d_rx_hpf = 0; // 0 = 100Hz, 1 = 30KHz
203 d_rx_ant = 0; // 0 = Ant. #1, 1 = Ant. #2
204 d_tx_ant = 0; // 0 = Ant. #1, 1 = Ant. #2
205 d_txvga_ser = 1; // 0 = TXVGA controlled by B6:1, 1=controlled serially
206 d_tx_driver_lin = 2; // 0=50% (worst linearity), 1=63%, 2=78%, 3=100% (best lin)
207 d_tx_vga_lin = 2; // 0=50% (worst linearity), 1=63%, 2=78%, 3=100% (best lin)
208 d_tx_upconv_lin = 2; // 0=50% (worst linearity), 1=63%, 2=78%, 3=100% (best lin)
209 d_tx_bb_gain = 3; // 0=maxgain-5dB, 1=max-3dB, 2=max-1.5dB, 3=max
210 d_pabias_delay = 15; // 0 = 0, 15 = 7uS
211 d_pabias = 0; // 0 = 0 uA, 63 = 315uA
212 d_rx_rf_gain = 0; // 0 = 0dB, 1 = 0dB, 2 = 15dB, 3 = 30dB
213 d_rx_bb_gain = 16; // 0 = min, 31 = max (0 - 62 dB)
215 d_txgain = 63; // 0 = min, 63 = max
217 // Initialize GPIO and ATR
218 usrp()->common_write_io(C_TX, d_which, TX_SAFE_IO, TX_OE_MASK);
219 usrp()->_common_write_oe(C_TX, d_which, TX_OE_MASK, 0xffff);
220 usrp()->common_write_atr_txval(C_TX, d_which, TX_SAFE_IO);
221 usrp()->common_write_atr_rxval(C_TX, d_which, TX_SAFE_IO);
222 usrp()->common_write_atr_mask(C_TX, d_which, TX_OE_MASK);
224 usrp()->common_write_io(C_RX, d_which, RX_SAFE_IO, RX_OE_MASK);
225 usrp()->_common_write_oe(C_RX, d_which, RX_OE_MASK, 0xffff);
226 usrp()->common_write_atr_txval(C_RX, d_which, RX_SAFE_IO);
227 usrp()->common_write_atr_rxval(C_RX, d_which, RX_SAFE_IO);
228 usrp()->common_write_atr_mask(C_RX, d_which, RX_OE_MASK);
230 // Initialize chipset
231 // TODO: perform reset sequence to ensure power up defaults
233 set_reg_bandselpll();
236 set_reg_rxrssi_ctrl();
237 set_reg_txlin_gain();
241 //FIXME: set_freq(2.45e9);
244 xcvr2450::~xcvr2450()
246 //printf("xcvr2450::destructor\n");
254 d_is_shutdown = true;
255 usrp()->common_write_atr_txval(C_TX, d_which, TX_SAFE_IO);
256 usrp()->common_write_atr_rxval(C_TX, d_which, TX_SAFE_IO);
257 usrp()->common_write_atr_txval(C_RX, d_which, RX_SAFE_IO);
258 usrp()->common_write_atr_rxval(C_RX, d_which, RX_SAFE_IO);
264 xcvr2450::set_reg_standby()
266 d_reg_standby = ((d_mimo<<17) |
271 send_reg(d_reg_standby);
275 xcvr2450::set_reg_int_divider()
277 d_reg_int_divider = (((d_frac_div & 0x03)<<16) |
279 send_reg(d_reg_int_divider);
283 xcvr2450::set_reg_frac_divider()
285 d_reg_frac_divider = ((d_frac_div & 0xfffc)<<2) | 4;
286 send_reg(d_reg_frac_divider);
290 xcvr2450::set_reg_bandselpll()
292 d_reg_bandselpll = ((d_mimo<<17) |
299 (d_five_gig<<4) | 5);
300 send_reg(d_reg_bandselpll);
301 d_reg_bandselpll = ((d_mimo<<17) |
308 (d_five_gig<<4) | 5);
309 send_reg(d_reg_bandselpll);
313 xcvr2450::set_reg_cal()
315 // FIXME do calibration
316 d_reg_cal = (1<<14)|6;
321 xcvr2450::set_reg_lpf()
327 (d_rxlpf_fine<<4) | 7);
332 xcvr2450::set_reg_rxrssi_ctrl()
334 d_reg_rxrssi_ctrl = ((d_rxvga_ser<<16) |
341 send_reg(d_reg_rxrssi_ctrl);
345 xcvr2450::set_reg_txlin_gain()
347 d_reg_txlin_gain = ((d_txvga_ser<<14) |
348 (d_tx_driver_lin<<12) |
350 (d_tx_upconv_lin<<6) |
351 (d_tx_bb_gain<<4) | 9);
352 send_reg(d_reg_txlin_gain);
356 xcvr2450::set_reg_pabias()
359 (d_pabias_delay<<10) |
361 send_reg(d_reg_pabias);
365 xcvr2450::set_reg_rxgain()
369 (d_rx_bb_gain<<4) | 11);
370 send_reg(d_reg_rxgain);
374 xcvr2450::set_reg_txgain()
376 d_reg_txgain = (d_txgain<<4) | 12;
377 send_reg(d_reg_txgain);
381 xcvr2450::send_reg(int v)
383 // Send 24 bits, it keeps last 18 clocked in
385 c[0] = (char)((v >> 16) & 0xff);
386 c[1] = (char)((v >> 8) & 0xff);
387 c[2] = (char)((v & 0xff));
390 usrp()->_write_spi(0, d_spi_enable, d_spi_format, s);
391 //printf("xcvr2450: Setting reg %d to %X\n", (v&15), v);
394 // ----------------------------------------------------------------
399 // We calculate four values:
401 // io_rx_while_rx: what to drive onto io_rx_* when receiving
402 // io_rx_while_tx: what to drive onto io_rx_* when transmitting
403 // io_tx_while_rx: what to drive onto io_tx_* when receiving
404 // io_tx_while_tx: what to drive onto io_tx_* when transmitting
406 // B1-B7 is ignored as gain is set serially for now.
408 int rx_hp, tx_antsel, rx_antsel, tx_pa_sel;
415 tx_antsel = ANTSEL_TX2_RX1;
417 tx_antsel = ANTSEL_TX1_RX2;
420 rx_antsel = ANTSEL_TX2_RX1;
422 rx_antsel = ANTSEL_TX1_RX2;
425 tx_pa_sel = LB_PA_OFF;
427 tx_pa_sel = HB_PA_OFF;
429 // Reset GPIO and ATR
430 // FIXME: dont set io, oe, atr mask once basic code stops overriding our settings
431 usrp()->common_write_io(C_TX, d_which, TX_SAFE_IO, TX_OE_MASK);
432 usrp()->_common_write_oe(C_TX, d_which, TX_OE_MASK, 0xffff);
433 usrp()->common_write_atr_txval(C_TX, d_which, tx_pa_sel|tx_antsel|TX_EN|AD9515DIV);
434 usrp()->common_write_atr_rxval(C_TX, d_which, HB_PA_OFF|LB_PA_OFF|rx_antsel|AD9515DIV);
435 usrp()->common_write_atr_mask(C_TX, d_which, TX_OE_MASK);
437 usrp()->common_write_io(C_RX, d_which, RX_SAFE_IO, RX_OE_MASK);
438 usrp()->_common_write_oe(C_RX, d_which, RX_OE_MASK, 0xffff);
439 usrp()->common_write_atr_txval(C_RX, d_which, EN|rx_hp);
440 usrp()->common_write_atr_rxval(C_RX, d_which, EN|rx_hp|RX_EN);
441 usrp()->common_write_atr_mask(C_RX, d_which, RX_OE_MASK);
443 //printf("GPIO: RXRX=%04X RXTX=%04X TXRX=%04X TXTX=%04X\n",
444 // io_rx_while_rx, io_rx_while_tx, io_tx_while_rx, io_tx_while_tx);
449 xcvr2450::set_freq(double target_freq)
451 struct freq_result_t args = {false, 0};
455 if(target_freq > 3e9) {
466 if(target_freq > 5.408e9) {
473 double vco_freq = target_freq*scaler;
474 double sys_clk = usrp()->fpga_master_clock_freq(); // Usually 64e6
475 double ref_clk = sys_clk / d_ad9515_div;
477 double phdet_freq = ref_clk/d_ref_div;
478 double div = vco_freq/phdet_freq;
479 d_int_div = int(floor(div));
480 d_frac_div = int((div-d_int_div)*65536.0);
481 // double actual_freq = phdet_freq*(d_int_div+(d_frac_div/65536.0))/scaler;
483 //printf("RF=%f VCO=%f R=%d PHD=%f DIV=%3.5f I=%3d F=%5d ACT=%f\n",
484 // target_freq, vco_freq, d_ref_div, phdet_freq,
485 // div, d_int_div, d_frac_div, actual_freq);
488 set_reg_int_divider();
489 set_reg_frac_divider();
490 set_reg_bandselpll();
492 args.ok = lock_detect();
494 args.baseband_freq = target_freq;
496 args.baseband_freq = actual_freq;
500 printf("Fail %f\n", target_freq);
506 xcvr2450::lock_detect()
509 @returns: the value of the VCO/PLL lock detect bit.
512 if(usrp()->common_read_io(C_RX, d_which) & LOCKDET) {
515 else { // Give it a second chance
516 if(usrp()->common_read_io(C_RX, d_which) & LOCKDET)
524 xcvr2450::set_rx_gain(float gain)
531 // Split the gain between RF and baseband
532 // This is experimental, not prescribed
534 d_rx_rf_gain = 0; // 0 dB RF gain
535 rx_bb_gain = int(gain/2.0);
538 if(gain >= 30.0 and gain < 60.5) {
539 d_rx_rf_gain = 2; // 15 dB RF gain
540 d_rx_bb_gain = int((gain-15.0)/2.0);
544 d_rx_rf_gain = 3; // 30.5 dB RF gain
545 d_rx_bb_gain = int((gain-30.5)/2.0);
554 xcvr2450::set_tx_gain(float gain)
563 d_txgain = int((gain/30.0)*63);
570 /*****************************************************************************/
573 struct xcvr2450_table_entry {
575 boost::weak_ptr<xcvr2450> value;
577 xcvr2450_table_entry(const xcvr2450_key &_key, boost::weak_ptr<xcvr2450> _value)
578 : key(_key), value(_value) {}
581 typedef std::vector<xcvr2450_table_entry> xcvr2450_table;
583 static boost::mutex s_table_mutex;
584 static xcvr2450_table s_table;
587 _get_or_make_xcvr2450(usrp_basic_sptr usrp, int which)
589 xcvr2450_key key = {usrp->serial_number(), which};
591 boost::mutex::scoped_lock guard(s_table_mutex);
593 for (xcvr2450_table::iterator p = s_table.begin(); p != s_table.end();){
594 if (p->value.expired()) // weak pointer is now dead
595 p = s_table.erase(p); // erase it
597 if (key == p->key){ // found it
598 return xcvr2450_sptr(p->value);
605 // We don't have the xcvr2450 we're looking for
607 // create a new one and stick it in the table.
608 xcvr2450_sptr r(new xcvr2450(usrp, which));
609 xcvr2450_table_entry t(key, r);
610 s_table.push_back(t);
616 /*****************************************************************************/
619 db_xcvr2450_base::db_xcvr2450_base(usrp_basic_sptr usrp, int which)
620 : db_base(usrp, which)
623 * Abstract base class for all xcvr2450 boards.
625 * Derive board specific subclasses from db_xcvr2450_base_{tx,rx}
627 * @param usrp: instance of usrp.source_c
628 * @param which: which side: 0 or 1 corresponding to side A or B respectively
632 d_xcvr = _get_or_make_xcvr2450(usrp, which);
635 db_xcvr2450_base::~db_xcvr2450_base()
640 db_xcvr2450_base::shutdown_common()
642 // If the usrp_basic in the xcvr2450 is the same as the usrp_basic
643 // in the daughterboard, shutdown the xcvr now (when only one of Tx
644 // and Rx is open, this is always true).
646 if (d_xcvr->usrp() == usrp()){
647 //std::cerr << "db_xcvr2450_base::shutdown_common: same -> shutting down\n";
651 //std::cerr << "db_xcvr2450_base::shutdown_common: different -> ignoring\n";
656 db_xcvr2450_base::set_freq(double target_freq)
659 * @returns (ok, actual_baseband_freq) where:
660 * ok is True or False and indicates success or failure,
661 * actual_baseband_freq is the RF frequency that corresponds to DC in the IF.
663 return d_xcvr->set_freq(target_freq+d_lo_offset);
667 db_xcvr2450_base::is_quadrature()
670 * Return True if this board requires both I & Q analog channels.
672 * This bit of info is useful when setting up the USRP Rx mux register.
678 db_xcvr2450_base::freq_min()
684 db_xcvr2450_base::freq_max()
690 /******************************************************************************/
693 db_xcvr2450_tx::db_xcvr2450_tx(usrp_basic_sptr usrp, int which)
694 : db_xcvr2450_base(usrp, which)
696 set_lo_offset(LO_OFFSET);
697 //printf("db_xcvr2450_tx::db_xcvr2450_tx\n");
700 db_xcvr2450_tx::~db_xcvr2450_tx()
706 db_xcvr2450_tx::shutdown()
709 d_is_shutdown = true;
715 db_xcvr2450_tx::gain_min()
721 db_xcvr2450_tx::gain_max()
727 db_xcvr2450_tx::gain_db_per_step()
733 db_xcvr2450_tx::set_gain(float gain)
735 return d_xcvr->set_tx_gain(gain);
739 db_xcvr2450_tx::i_and_q_swapped()
745 /******************************************************************************/
748 db_xcvr2450_rx::db_xcvr2450_rx(usrp_basic_sptr usrp, int which)
749 : db_xcvr2450_base(usrp, which)
752 * @param usrp: instance of usrp.source_c
753 * @param which: 0 or 1 corresponding to side RX_A or RX_B respectively.
755 set_lo_offset(LO_OFFSET);
756 //printf("db_xcvr2450_rx:d_xcvr_2450_rx\n");
759 db_xcvr2450_rx::~db_xcvr2450_rx()
765 db_xcvr2450_rx::shutdown()
768 d_is_shutdown = true;
774 db_xcvr2450_rx::gain_min()
780 db_xcvr2450_rx::gain_max()
786 db_xcvr2450_rx::gain_db_per_step()
792 db_xcvr2450_rx::set_gain(float gain)
794 return d_xcvr->set_rx_gain(gain);