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   1 /*
   2  * Copyright 2009 Ettus Research LLC
   3  */
   4
   5 #include "db_wbxng_adf4350_regs.h"
   6 #include "db_wbxng_adf4350.h"
   7
   8 //#include "cal_div.h"
   9
  10 /* reg 0 */
  11 /* reg 1 */
  12 const uint16_t adf4350_regs::s_phase = 0;
  13 /* reg 2 */
  14 const uint8_t adf4350_regs::s_low_noise_and_low_spur_modes = 3;
  15 const uint8_t adf4350_regs::s_muxout = 6;
  16 const uint8_t adf4350_regs::s_reference_doubler = 0;
  17 const uint8_t adf4350_regs::s_rdiv2 = 0;
  18 const uint8_t adf4350_regs::s_double_buff = 0;
  19 const uint8_t adf4350_regs::s_charge_pump_setting = 5;
  20 const uint8_t adf4350_regs::s_ldf = 0;
  21 const uint8_t adf4350_regs::s_ldp = 0;
  22 const uint8_t adf4350_regs::s_pd_polarity = 1;
  23 const uint8_t adf4350_regs::s_power_down = 0;
  24 const uint8_t adf4350_regs::s_cp_three_state = 0;
  25 const uint8_t adf4350_regs::s_counter_reset = 0;
  26 /* reg 3 */
  27 const uint8_t adf4350_regs::s_csr = 0;
  28 const uint8_t adf4350_regs::s_clk_div_mode = 0;
  29 const uint16_t adf4350_regs::s_12_bit_clock_divider_value = 0;
  30 /* reg 4 */
  31 const uint8_t adf4350_regs::s_feedback_select = 1;
  32 const uint8_t adf4350_regs::s_vco_power_down = 0;
  33 const uint8_t adf4350_regs::s_mtld = 0;
  34 const uint8_t adf4350_regs::s_aux_output_select = 1;
  35 const uint8_t adf4350_regs::s_aux_output_enable = 0;
  36 const uint8_t adf4350_regs::s_aux_output_power = 0;
  37 const uint8_t adf4350_regs::s_rf_output_enable = 1;
  38 const uint8_t adf4350_regs::s_output_power = 3;
  39 /* reg 5 */
  40 const uint8_t adf4350_regs::s_ld_pin_mode = 1;
  41
  42 adf4350_regs::adf4350_regs(adf4350* _adf4350){
  43     d_adf4350 = _adf4350;
  44
  45     /* reg 0 */
  46     d_int = uint16_t(100);
  47     d_frac = 0;
  48     /* reg 1 */
  49     d_prescaler = uint8_t(0);
  50     d_mod = uint16_t(0xfff);                      /* max fractional accuracy */
  51     /* reg 2 */
  52     d_10_bit_r_counter = uint16_t(2);
  53     /* reg 3 */
  54     /* reg 4 */
  55     d_divider_select = 0;
  56     d_8_bit_band_select_clock_divider_value = 0;
  57     /* reg 5 */
  58 }
  59
  60 adf4350_regs::~adf4350_regs(void){
  61 }
  62
  63 uint32_t
  64 adf4350_regs::_reg_shift(uint32_t data, uint32_t shift){
  65         return data << shift;
  66     }
  67
  68 void
  69 adf4350_regs::_load_register(uint8_t addr){
  70         uint32_t data;
  71         switch (addr){
  72                 case 0: data = (
  73                         _reg_shift(d_int, 15)                           |
  74                         _reg_shift(d_frac, 3)); break;
  75                 case 1: data = (
  76                         _reg_shift(d_prescaler, 27)                     |
  77                         _reg_shift(s_phase, 15)                         |
  78                         _reg_shift(d_mod, 3)); break;
  79                 case 2: data = (
  80                         _reg_shift(s_low_noise_and_low_spur_modes, 29)  |
  81                         _reg_shift(s_muxout, 26)                        |
  82                         _reg_shift(s_reference_doubler, 25)             |
  83                         _reg_shift(s_rdiv2, 24)                         |
  84                         _reg_shift(d_10_bit_r_counter, 14)              |
  85                         _reg_shift(s_double_buff, 13)                   |
  86                         _reg_shift(s_charge_pump_setting, 9)            |
  87                         _reg_shift(s_ldf, 8)                            |
  88                         _reg_shift(s_ldp, 7)                            |
  89                         _reg_shift(s_pd_polarity, 6)                    |
  90                         _reg_shift(s_power_down, 5)                     |
  91                         _reg_shift(s_cp_three_state, 4)                 |
  92                         _reg_shift(s_counter_reset, 3)); break;
  93                 case 3: data = (
  94                         _reg_shift(s_csr, 18)                           |
  95                         _reg_shift(s_clk_div_mode, 15)                  |
  96                         _reg_shift(s_12_bit_clock_divider_value, 3)); break;
  97                 case 4: data = (
  98                         _reg_shift(s_feedback_select, 23)               |
  99                         _reg_shift(d_divider_select, 20)                |
 100                         _reg_shift(d_8_bit_band_select_clock_divider_value, 12) |
 101                         _reg_shift(s_vco_power_down, 11)                |
 102                         _reg_shift(s_mtld, 10)                          |
 103                         _reg_shift(s_aux_output_select, 9)              |
 104                         _reg_shift(s_aux_output_enable, 8)              |
 105                         _reg_shift(s_aux_output_power, 6)               |
 106                         _reg_shift(s_rf_output_enable, 5)               |
 107                         _reg_shift(s_output_power, 3)); break;
 108                 case 5: data = (
 109                         _reg_shift(s_ld_pin_mode, 22)); break;
 110                 default: return;
 111         }
 112         /* write the data out to spi */
 113         d_adf4350->_write(addr, data);
 114 }