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   1 /*
   2  * Copyright 2009 Ettus Research LLC
   3  */
   4
   5 #include <usrp/db_wbxng_adf4350_regs.h>
   6 #include <usrp/db_wbxng_adf4350.h>
   7 //#include "cal_div.h"
   8
   9 adf4350_regs::adf4350_regs(adf4350* _adf4350){
  10     d_adf4350 = _adf4350;
  11
  12     /* reg 0 */
  13     _int = uint16_t(100);
  14     _frac = 0;
  15     /* reg 1 */
  16     _prescaler = 1;                        /* 8/9 */
  17     _phase = 0;                           /* 0 */
  18     _mod = uint16_t(0xfff);                      /* max fractional accuracy */
  19     /* reg 2 */
  20     _low_noise_and_low_spur_modes = 0;     /* low noise mode */
  21     _muxout = 6;                           /* digital lock detect */
  22     _reference_doubler = 1;                /* enabled */
  23     _rdiv2 = 0;                            /* disabled */
  24     _10_bit_r_counter = uint16_t(1);
  25     _double_buff = 0;                      /* disabled */
  26     _charge_pump_setting = 7;              /* 2.50 mA */
  27     _ldf = 0;                              /* frac-n */
  28     _ldp = 0;                              /* 10 ns */
  29     _pd_polarity = 1;                      /* positive */
  30     _power_down = 0;                       /* disabled */
  31     _cp_three_state = 0;                   /* disabled */
  32     _counter_reset = 0;                    /* disabled */
  33     /* reg 3 */
  34     _csr = 0;                              /* disabled */
  35     _clk_div_mode = 0;                     /* clock divider off */
  36     _12_bit_clock_divider_value = 0;      /* 0 */
  37     /* reg 4 */
  38     _feedback_select = 1;                  /* fundamental */
  39     _divider_select = 0;
  40     _8_bit_band_select_clock_divider_value = 0;
  41     _vco_power_down = 0;                   /* vco powered up */
  42     _mtld = 0;                             /* mute disabled */
  43     _aux_output_select = 0;                /* divided output */
  44     _aux_output_enable = 0;                /* disabled */
  45     _aux_output_power = 0;                 /* -4 */
  46     _rf_output_enable = 1;                 /* enabled */
  47     _output_power = 1;                     /* -1 */
  48     /* reg 5 */
  49     _ld_pin_mode = 1;                      /* digital lock detect */
  50 }
  51
  52 adf4350_regs::~adf4350_regs(void){
  53 }
  54
  55 uint32_t
  56 adf4350_regs::_reg_shift(uint32_t data, uint32_t shift){
  57         return data << shift;
  58     }
  59
  60 void
  61 adf4350_regs::_load_register(uint8_t addr){
  62         uint32_t data;
  63         switch (addr){
  64                 case 0: data = (
  65                         _reg_shift(_int, 15)                           |
  66                         _reg_shift(_frac, 3)); break;
  67                 case 1: data = (
  68                         _reg_shift(_prescaler, 27)                     |
  69                         _reg_shift(_phase, 15)                         |
  70                         _reg_shift(_mod, 3)); break;
  71                 case 2: data = (
  72                         _reg_shift(_low_noise_and_low_spur_modes, 29)  |
  73                         _reg_shift(_muxout, 26)                        |
  74                         _reg_shift(_reference_doubler, 25)             |
  75                         _reg_shift(_rdiv2, 24)                         |
  76                         _reg_shift(_10_bit_r_counter, 14)              |
  77                         _reg_shift(_double_buff, 13)                   |
  78                         _reg_shift(_charge_pump_setting, 9)            |
  79                         _reg_shift(_ldf, 8)                            |
  80                         _reg_shift(_ldp, 7)                            |
  81                         _reg_shift(_pd_polarity, 6)                    |
  82                         _reg_shift(_power_down, 5)                     |
  83                         _reg_shift(_cp_three_state, 4)                 |
  84                         _reg_shift(_counter_reset, 3)); break;
  85                 case 3: data = (
  86                         _reg_shift(_csr, 18)                           |
  87                         _reg_shift(_clk_div_mode, 15)                  |
  88                         _reg_shift(_12_bit_clock_divider_value, 3)); break;
  89                 case 4: data = (
  90                         _reg_shift(_feedback_select, 23)               |
  91                         _reg_shift(_divider_select, 20)                |
  92                         _reg_shift(_8_bit_band_select_clock_divider_value, 12) |
  93                         _reg_shift(_vco_power_down, 11)                |
  94                         _reg_shift(_mtld, 10)                          |
  95                         _reg_shift(_aux_output_select, 9)              |
  96                         _reg_shift(_aux_output_enable, 8)              |
  97                         _reg_shift(_aux_output_power, 6)               |
  98                         _reg_shift(_rf_output_enable, 5)               |
  99                         _reg_shift(_output_power, 3)); break;
 100                 case 5: data = (
 101                         _reg_shift(_ld_pin_mode, 22)); break;
 102                 default: return;
 103         }
 104         /* write the data out to spi */
 105         d_adf4350->_write(addr, data);
 106 }