2 * Copyright 2009 Ettus Research LLC
5 #include <usrp/db_wbxng_adf4350_regs.h>
6 #include <usrp/db_wbxng_adf4350.h>
11 const uint8_t adf4350_regs::s_prescaler = 0;
12 const uint16_t adf4350_regs::s_phase = 0;
14 const uint8_t adf4350_regs::s_low_noise_and_low_spur_modes = 0;
15 const uint8_t adf4350_regs::s_muxout = 6;
16 const uint8_t adf4350_regs::s_reference_doubler = 0;
17 const uint8_t adf4350_regs::s_rdiv2 = 0;
18 const uint8_t adf4350_regs::s_double_buff = 0;
19 const uint8_t adf4350_regs::s_charge_pump_setting = 5;
20 const uint8_t adf4350_regs::s_ldf = 0;
21 const uint8_t adf4350_regs::s_ldp = 0;
22 const uint8_t adf4350_regs::s_pd_polarity = 1;
23 const uint8_t adf4350_regs::s_power_down = 0;
24 const uint8_t adf4350_regs::s_cp_three_state = 0;
25 const uint8_t adf4350_regs::s_counter_reset = 0;
27 const uint8_t adf4350_regs::s_csr = 0;
28 const uint8_t adf4350_regs::s_clk_div_mode = 0;
29 const uint16_t adf4350_regs::s_12_bit_clock_divider_value = 0;
31 const uint8_t adf4350_regs::s_feedback_select = 1;
32 const uint8_t adf4350_regs::s_vco_power_down = 0;
33 const uint8_t adf4350_regs::s_mtld = 0;
34 const uint8_t adf4350_regs::s_aux_output_select = 0;
35 const uint8_t adf4350_regs::s_aux_output_enable = 1;
36 const uint8_t adf4350_regs::s_aux_output_power = 3;
37 const uint8_t adf4350_regs::s_rf_output_enable = 1;
38 const uint8_t adf4350_regs::s_output_power = 3;
40 const uint8_t adf4350_regs::s_ld_pin_mode = 1;
42 adf4350_regs::adf4350_regs(adf4350* _adf4350){
46 d_int = uint16_t(100);
49 d_mod = uint16_t(0xfff); /* max fractional accuracy */
51 d_10_bit_r_counter = uint16_t(2);
55 d_8_bit_band_select_clock_divider_value = 0;
59 adf4350_regs::~adf4350_regs(void){
63 adf4350_regs::_reg_shift(uint32_t data, uint32_t shift){
68 adf4350_regs::_load_register(uint8_t addr){
72 _reg_shift(d_int, 15) |
73 _reg_shift(d_frac, 3)); break;
75 _reg_shift(s_prescaler, 27) |
76 _reg_shift(s_phase, 15) |
77 _reg_shift(d_mod, 3)); break;
79 _reg_shift(s_low_noise_and_low_spur_modes, 29) |
80 _reg_shift(s_muxout, 26) |
81 _reg_shift(s_reference_doubler, 25) |
82 _reg_shift(s_rdiv2, 24) |
83 _reg_shift(d_10_bit_r_counter, 14) |
84 _reg_shift(s_double_buff, 13) |
85 _reg_shift(s_charge_pump_setting, 9) |
86 _reg_shift(s_ldf, 8) |
87 _reg_shift(s_ldp, 7) |
88 _reg_shift(s_pd_polarity, 6) |
89 _reg_shift(s_power_down, 5) |
90 _reg_shift(s_cp_three_state, 4) |
91 _reg_shift(s_counter_reset, 3)); break;
93 _reg_shift(s_csr, 18) |
94 _reg_shift(s_clk_div_mode, 15) |
95 _reg_shift(s_12_bit_clock_divider_value, 3)); break;
97 _reg_shift(s_feedback_select, 23) |
98 _reg_shift(d_divider_select, 20) |
99 _reg_shift(d_8_bit_band_select_clock_divider_value, 12) |
100 _reg_shift(s_vco_power_down, 11) |
101 _reg_shift(s_mtld, 10) |
102 _reg_shift(s_aux_output_select, 9) |
103 _reg_shift(s_aux_output_enable, 8) |
104 _reg_shift(s_aux_output_power, 6) |
105 _reg_shift(s_rf_output_enable, 5) |
106 _reg_shift(s_output_power, 3)); break;
108 _reg_shift(s_ld_pin_mode, 22)); break;
111 /* write the data out to spi */
112 d_adf4350->_write(addr, data);