2 // Copyright 2009 Free Software Foundation, Inc.
4 // This file is part of GNU Radio
6 // GNU Radio is free software; you can redistribute it and/or modify
7 // it under the terms of the GNU General Public License as published by
8 // the Free Software Foundation; either asversion 3, or (at your option)
11 // GNU Radio is distributed in the hope that it will be useful,
12 // but WITHOUT ANY WARRANTY; without even the implied warranty of
13 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 // GNU General Public License for more details.
16 // You should have received a copy of the GNU General Public License
17 // along with GNU Radio; see the file COPYING. If not, write to
18 // the Free Software Foundation, Inc., 51 Franklin Street,
19 // Boston, MA 02110-1301, USA.
25 #include "db_wbxng_adf4350.h"
26 #include <db_base_impl.h>
29 #define FREQ_C(freq) uint64_t(freq)
30 #define DIV_ROUND(num, denom) (((num) + ((denom)/2))/(denom))
31 #define MIN_INT_DIV uint16_t(23) /* minimum int divider, prescaler 4/5 only */
32 #define MAX_RF_DIV uint8_t(16) /* max rf divider, divides rf output */
33 #define MIN_VCO_FREQ FREQ_C(2.2e9) /* minimum vco freq */
34 #define MAX_VCO_FREQ FREQ_C(4.4e9) /* minimum vco freq */
35 #define MAX_FREQ DIV_ROUND(MAX_VCO_FREQ, 1) /* upper bound freq (rf div = 1) */
36 #define MIN_FREQ DIV_ROUND(MIN_VCO_FREQ, MAX_RF_DIV) /* calculated lower bound freq */
38 #define CE_PIN (1 << 3)
39 #define PDB_RF_PIN (1 << 2)
40 #define MUX_PIN (1 << 1)
41 #define LD_PIN (1 << 0)
43 adf4350::adf4350(usrp_basic_sptr _usrp, int _which, int _spi_enable)
45 /* Initialize the pin directions. */
49 d_spi_enable = _spi_enable;
50 d_spi_format = SPI_FMT_MSB | SPI_FMT_HDR_0;
52 d_regs = new adf4350_regs(this);
55 d_usrp->_write_oe(d_which, (CE_PIN | PDB_RF_PIN), (CE_PIN | PDB_RF_PIN));
56 d_usrp->write_io(d_which, (CE_PIN), (CE_PIN | PDB_RF_PIN));
58 /* Initialize the pin levels. */
60 /* Initialize the registers. */
61 d_regs->_load_register(5);
62 d_regs->_load_register(4);
63 d_regs->_load_register(3);
64 d_regs->_load_register(2);
65 d_regs->_load_register(1);
66 d_regs->_load_register(0);
71 d_usrp->write_io(d_which, (0), (CE_PIN | PDB_RF_PIN));
76 adf4350::_get_max_freq(void)
82 adf4350::_get_min_freq(void)
88 adf4350::_get_locked(void)
90 return d_usrp->read_io(d_which) & LD_PIN;
94 adf4350::_enable(bool enable)
96 if (enable){ /* chip enable */
97 d_usrp->write_io(d_which, (PDB_RF_PIN), (PDB_RF_PIN));
99 d_usrp->write_io(d_which, 0, (PDB_RF_PIN));
104 adf4350::_write(uint8_t addr, uint32_t data)
108 // create str from data here
110 s[0] = (char)((data >> 24) & 0xff);
111 s[1] = (char)((data >> 16) & 0xff);
112 s[2] = (char)((data >> 8) & 0xff);
113 s[3] = (char)(data & 0xff);
114 std::string str(s, 4);
121 d_usrp->_write_spi(0, d_spi_enable, d_spi_format, str);
124 //fprintf(stderr, "Wrote to WBXNG SPI address %d with data %8x\n", addr, data);
126 //d_usrp->write_io(d_which, 1, LE_PIN);
127 //d_usrp->write_io(d_which, 0, LE_PIN);
131 adf4350::_set_freq(freq_t freq, freq_t refclock_freq)
133 /* Set the frequency by setting int, frac, mod, r, div */
134 if (freq > MAX_FREQ || freq < MIN_FREQ) return false;
135 int min_int_div = 23;
136 d_regs->d_prescaler = 0;
137 if (freq > FREQ_C(3e9)) {
139 d_regs->d_prescaler = 1;
141 /* Ramp up the RF divider until the VCO is within range. */
142 d_regs->d_divider_select = 0;
143 while (freq < MIN_VCO_FREQ){
144 freq <<= 1; //double the freq
145 d_regs->d_divider_select++; //double the divider
147 /* Ramp up the R divider until the N divider is at least the minimum. */
148 //d_regs->d_10_bit_r_counter = refclock_freq*MIN_INT_DIV/freq;
149 d_regs->d_10_bit_r_counter = 2;
152 d_regs->d_10_bit_r_counter++;
154 n_mod *= d_regs->d_10_bit_r_counter;
155 n_mod *= d_regs->d_mod;
156 n_mod /= refclock_freq;
157 /* calculate int and frac */
158 d_regs->d_int = n_mod/d_regs->d_mod;
159 d_regs->d_frac = (n_mod - (freq_t)d_regs->d_int*d_regs->d_mod) & uint16_t(0xfff);
162 "VCO %lu KHz, Int %u, Frac %u, Mod %u, R %u, Div %u\n",
163 freq, d_regs->d_int, d_regs->d_frac,
164 d_regs->d_mod, d_regs->d_10_bit_r_counter, (1 << d_regs->d_divider_select)
167 }while(d_regs->d_int < min_int_div);
168 /* calculate the band select so PFD is under 125 KHz */
169 d_regs->d_8_bit_band_select_clock_divider_value = \
170 refclock_freq/(FREQ_C(30e3)*d_regs->d_10_bit_r_counter) + 1;
172 fprintf(stderr, "Band Selection: Div %u, Freq %lu\n",
173 d_regs->d_8_bit_band_select_clock_divider_value,
174 refclock_freq/(d_regs->d_8_bit_band_select_clock_divider_value * d_regs->d_10_bit_r_counter) + 1
177 d_regs->_load_register(5);
178 d_regs->_load_register(3);
179 d_regs->_load_register(1);
180 /* load involved registers */
181 d_regs->_load_register(2);
182 d_regs->_load_register(4);
183 d_regs->_load_register(0); /* register 0 must be last */
188 adf4350::_get_freq(freq_t refclock_freq)
190 /* Calculate the freq from int, frac, mod, ref, r, div:
191 * freq = (int + frac/mod) * (ref/r)
192 * Keep precision by doing multiplies first:
193 * freq = (((((((int)*mod) + frac)*ref)/mod)/r)/div)
196 temp = d_regs->d_int;
197 temp *= d_regs->d_mod;
198 temp += d_regs->d_frac;
199 temp *= refclock_freq;
200 temp /= d_regs->d_mod;
201 temp /= d_regs->d_10_bit_r_counter;
202 temp /= (1 << d_regs->d_divider_select);