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   1 /*
   2  * Copyright 2009 Ettus Research LLC
   3  */
   4
   5 #ifdef HAVE_CONFIG_H
   6 #include <config.h>
   7 #endif
   8
   9 #include <usrp/db_wbxng_adf4350.h>
  10 #include <usrp/db_wbxng_adf4350_regs.h>
  11 #include <db_base_impl.h>
  12 #include <stdio.h>
  13 //#include "io.h"
  14 //#include "spi.h"
  15
  16 #define INPUT_REF_FREQ FREQ_C(10e6)
  17 #define DIV_ROUND(num, denom) (((num) + ((denom)/2))/(denom))
  18 #define FREQ_C(freq) ((uint32_t)DIV_ROUND(freq, (uint32_t)1000))
  19 #define INPUT_REF_FREQ_2X (2*INPUT_REF_FREQ)                            /* input ref freq with doubler turned on */
  20 #define MIN_INT_DIV uint16_t(23)                                        /* minimum int divider, prescaler 4/5 only */
  21 #define MAX_RF_DIV uint8_t(16)                                          /* max rf divider, divides rf output */
  22 #define MIN_VCO_FREQ FREQ_C(2.2e9)                                      /* minimum vco freq */
  23 #define MAX_VCO_FREQ FREQ_C(4.4e9)                                      /* minimum vco freq */
  24 #define MAX_FREQ MAX_VCO_FREQ                                           /* upper bound freq (rf div = 1) */
  25 #define MIN_FREQ DIV_ROUND(MIN_VCO_FREQ, MAX_RF_DIV)                    /* calculated lower bound freq */
  26
  27 #define CE_PIN        (1 << 3)
  28 #define PDB_RF_PIN    (1 << 2)
  29 #define MUX_PIN       (1 << 1)
  30 #define LD_PIN        (1 << 0)
  31
  32 adf4350::adf4350(usrp_basic_sptr _usrp, int _which, int _spi_enable){
  33         /* Initialize the pin directions. */
  34
  35     d_usrp = _usrp;
  36     d_which = _which;
  37     d_spi_enable = _spi_enable;
  38     d_spi_format = SPI_FMT_MSB | SPI_FMT_HDR_0;
  39
  40     d_regs = new adf4350_regs(this);
  41
  42     /* Outputs */
  43     d_usrp->_write_oe(d_which, (CE_PIN | PDB_RF_PIN), 0xffff);
  44
  45         /* Initialize the pin levels. */
  46         _enable(true);
  47         /* Initialize the registers. */
  48         d_regs->_load_register(5);
  49         d_regs->_load_register(4);
  50         d_regs->_load_register(3);
  51         d_regs->_load_register(2);
  52         d_regs->_load_register(1);
  53         d_regs->_load_register(0);
  54 }
  55
  56 adf4350::~adf4350(){
  57     delete d_regs;
  58 }
  59
  60 freq_t
  61 adf4350::_get_max_freq(void){
  62         return MAX_FREQ;
  63 }
  64
  65 freq_t
  66 adf4350::_get_min_freq(void){
  67         return MIN_FREQ;
  68 }
  69
  70 bool
  71 adf4350::_get_locked(void){
  72     return d_usrp->read_io(d_which) & LD_PIN;
  73 }
  74
  75 void
  76 adf4350::_enable(bool enable){
  77         if (enable){ /* chip enable */
  78         d_usrp->write_io(d_which, 1, CE_PIN);
  79         }else{
  80         d_usrp->write_io(d_which, 0, CE_PIN);
  81         }
  82 }
  83
  84 void
  85 adf4350::_write(uint8_t addr, uint32_t data){
  86         data |= addr;
  87
  88     // create str from data here
  89     char s[4];
  90     s[0] = (char)((data >> 24) & 0xff);
  91     s[1] = (char)((data >> 16) & 0xff);
  92     s[2] = (char)((data >>  8) & 0xff);
  93     s[3] = (char)(data & 0xff);
  94     std::string str(s, 3);
  95
  96     d_usrp->_write_spi(0, d_spi_enable, d_spi_format, str);
  97         /* pulse latch */
  98     //d_usrp->write_io(d_which, 1, LE_PIN);
  99     //d_usrp->write_io(d_which, 0, LE_PIN);
 100 }
 101
 102 bool
 103 adf4350::_set_freq(freq_t freq){
 104         /* Set the frequency by setting int, frac, mod, r, div */
 105         if (freq > MAX_FREQ || freq < MIN_FREQ) return false;
 106         /* Ramp up the RF divider until the VCO is within range. */
 107         d_regs->_divider_select = 0;
 108         while (freq < MIN_VCO_FREQ){
 109                 freq <<= 1; //double the freq
 110                 d_regs->_divider_select++; //double the divider
 111         }
 112         /* Ramp up the R divider until the N divider is at least the minimum. */
 113         d_regs->_10_bit_r_counter = INPUT_REF_FREQ_2X*MIN_INT_DIV/freq;
 114         uint64_t n_mod;
 115         do{
 116                 d_regs->_10_bit_r_counter++;
 117                 n_mod = freq;
 118                 n_mod *= d_regs->_10_bit_r_counter;
 119                 n_mod *= d_regs->_mod;
 120                 n_mod /= INPUT_REF_FREQ_2X;
 121                 /* calculate int and frac */
 122                 d_regs->_int = n_mod/d_regs->_mod;
 123                 d_regs->_frac = (n_mod - (freq_t)d_regs->_int*d_regs->_mod) & uint16_t(0xfff);
 124                 /*printf(
 125                         "VCO %lu KHz, Int %u, Frac %u, Mod %u, R %u, Div %u\n",
 126                         freq, d_regs->_int, d_regs->_frac,
 127                         d_regs->_mod, d_regs->_10_bit_r_counter, (1 << d_regs->_divider_select)
 128                 );*/
 129         }while(d_regs->_int < MIN_INT_DIV);
 130         /* calculate the band select so PFD is under 125 KHz */
 131         d_regs->_8_bit_band_select_clock_divider_value = \
 132                 INPUT_REF_FREQ_2X/(FREQ_C(125e3)*d_regs->_10_bit_r_counter) + 1;
 133         /* load involved registers */
 134         d_regs->_load_register(2);
 135         d_regs->_load_register(4);
 136         d_regs->_load_register(0); /* register 0 must be last */
 137         return true;
 138 }
 139
 140 freq_t
 141 adf4350::_get_freq(void){
 142         /* Calculate the freq from int, frac, mod, ref, r, div:
 143          *  freq = (int + frac/mod) * (ref/r)
 144          * Keep precision by doing multiplies first:
 145          *  freq = (((((((int)*mod) + frac)*ref)/mod)/r)/div)
 146          */
 147         uint64_t temp;
 148         temp = d_regs->_int;
 149         temp *= d_regs->_mod;
 150         temp += d_regs->_frac;
 151         temp *= INPUT_REF_FREQ_2X;
 152         temp /= d_regs->_mod;
 153         temp /= d_regs->_10_bit_r_counter;
 154         temp /= (1 << d_regs->_divider_select);
 155         return temp;
 156 }