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   1 /*
   2  * Copyright 2009 Ettus Research LLC
   3  */
   4
   5 #ifdef HAVE_CONFIG_H
   6 #include <config.h>
   7 #endif
   8
   9 #include <usrp/db_wbxng_adf4350.h>
  10 #include <usrp/db_wbxng_adf4350_regs.h>
  11 #include <db_base_impl.h>
  12 #include <stdio.h>
  13 //#include "io.h"
  14 //#include "spi.h"
  15
  16 #define INPUT_REF_FREQ FREQ_C(64e6)
  17 #define DIV_ROUND(num, denom) (((num) + ((denom)/2))/(denom))
  18 //#define FREQ_C(freq) ((uint64_t)DIV_ROUND(freq, (uint64_t)1000))
  19 #define FREQ_C(freq) uint64_t(freq)
  20 #define INPUT_REF_FREQ_2X (2*INPUT_REF_FREQ)                            /* input ref freq with doubler turned on */
  21 #define MIN_INT_DIV uint16_t(23)                                        /* minimum int divider, prescaler 4/5 only */
  22 #define MAX_RF_DIV uint8_t(16)                                          /* max rf divider, divides rf output */
  23 #define MIN_VCO_FREQ FREQ_C(2.2e9)                                      /* minimum vco freq */
  24 #define MAX_VCO_FREQ FREQ_C(4.4e9)                                      /* minimum vco freq */
  25 #define MAX_FREQ MAX_VCO_FREQ                                           /* upper bound freq (rf div = 1) */
  26 #define MIN_FREQ DIV_ROUND(MIN_VCO_FREQ, MAX_RF_DIV)                    /* calculated lower bound freq */
  27
  28 #define CE_PIN        (1 << 3)
  29 #define PDB_RF_PIN    (1 << 2)
  30 #define MUX_PIN       (1 << 1)
  31 #define LD_PIN        (1 << 0)
  32
  33 adf4350::adf4350(usrp_basic_sptr _usrp, int _which, int _spi_enable){
  34         /* Initialize the pin directions. */
  35
  36     d_usrp = _usrp;
  37     d_which = _which;
  38     d_spi_enable = _spi_enable;
  39     d_spi_format = SPI_FMT_MSB | SPI_FMT_HDR_0;
  40
  41     d_regs = new adf4350_regs(this);
  42
  43     /* Outputs */
  44     d_usrp->_write_oe(d_which, (CE_PIN | PDB_RF_PIN), (CE_PIN | PDB_RF_PIN));
  45     d_usrp->write_io(d_which, (CE_PIN | PDB_RF_PIN), (CE_PIN | PDB_RF_PIN));
  46
  47         /* Initialize the pin levels. */
  48         _enable(true);
  49         /* Initialize the registers. */
  50     /*
  51     timespec t;
  52     t.tv_sec = 1;
  53     t.tv_nsec = 0;
  54     while (1) {
  55     */
  56     d_regs->_load_register(5);
  57     /*
  58         nanosleep(&t, NULL);
  59     }
  60     */
  61         d_regs->_load_register(4);
  62         d_regs->_load_register(3);
  63         d_regs->_load_register(2);
  64         d_regs->_load_register(1);
  65         d_regs->_load_register(0);
  66 }
  67
  68 adf4350::~adf4350(){
  69     delete d_regs;
  70 }
  71
  72 freq_t
  73 adf4350::_get_max_freq(void){
  74         return MAX_FREQ;
  75 }
  76
  77 freq_t
  78 adf4350::_get_min_freq(void){
  79         return MIN_FREQ;
  80 }
  81
  82 bool
  83 adf4350::_get_locked(void){
  84     return d_usrp->read_io(d_which) & LD_PIN;
  85 }
  86
  87 void
  88 adf4350::_enable(bool enable){
  89         if (enable){ /* chip enable */
  90         d_usrp->write_io(d_which, (CE_PIN | PDB_RF_PIN), (CE_PIN | PDB_RF_PIN));
  91         }else{
  92         d_usrp->write_io(d_which, 0, (CE_PIN | PDB_RF_PIN));
  93         }
  94 }
  95
  96 void
  97 adf4350::_write(uint8_t addr, uint32_t data){
  98         data |= addr;
  99
 100     // create str from data here
 101     char s[4];
 102     s[0] = (char)((data >> 24) & 0xff);
 103     s[1] = (char)((data >> 16) & 0xff);
 104     s[2] = (char)((data >>  8) & 0xff);
 105     s[3] = (char)(data & 0xff);
 106     std::string str(s, 4);
 107
 108     timespec t;
 109     t.tv_sec = 0;
 110     t.tv_nsec = 5e6;
 111
 112     nanosleep(&t, NULL);
 113     d_usrp->_write_spi(0, d_spi_enable, d_spi_format, str);
 114     nanosleep(&t, NULL);
 115
 116     fprintf(stderr, "Wrote to WBXNG SPI address %d with data %8x\n", addr, data);
 117         /* pulse latch */
 118     //d_usrp->write_io(d_which, 1, LE_PIN);
 119     //d_usrp->write_io(d_which, 0, LE_PIN);
 120 }
 121
 122 bool
 123 adf4350::_set_freq(freq_t freq){
 124         /* Set the frequency by setting int, frac, mod, r, div */
 125         if (freq > MAX_FREQ || freq < MIN_FREQ) return false;
 126         /* Ramp up the RF divider until the VCO is within range. */
 127         d_regs->d_divider_select = 0;
 128         while (freq < MIN_VCO_FREQ){
 129                 freq <<= 1; //double the freq
 130                 d_regs->d_divider_select++; //double the divider
 131         }
 132         /* Ramp up the R divider until the N divider is at least the minimum. */
 133         //d_regs->d_10_bit_r_counter = INPUT_REF_FREQ*MIN_INT_DIV/freq;
 134         d_regs->d_10_bit_r_counter = 2;
 135         uint64_t n_mod;
 136         do{
 137                 d_regs->d_10_bit_r_counter++;
 138                 n_mod = freq;
 139                 n_mod *= d_regs->d_10_bit_r_counter;
 140                 n_mod *= d_regs->d_mod;
 141                 n_mod /= INPUT_REF_FREQ;
 142                 /* calculate int and frac */
 143                 d_regs->d_int = n_mod/d_regs->d_mod;
 144                 d_regs->d_frac = (n_mod - (freq_t)d_regs->d_int*d_regs->d_mod) & uint16_t(0xfff);
 145                 fprintf(stderr,
 146                         "VCO %lu KHz, Int %u, Frac %u, Mod %u, R %u, Div %u\n",
 147                         freq, d_regs->d_int, d_regs->d_frac,
 148                         d_regs->d_mod, d_regs->d_10_bit_r_counter, (1 << d_regs->d_divider_select)
 149                 );
 150         }while(d_regs->d_int < MIN_INT_DIV);
 151         /* calculate the band select so PFD is under 125 KHz */
 152         d_regs->d_8_bit_band_select_clock_divider_value = \
 153                 INPUT_REF_FREQ/(FREQ_C(30e3)*d_regs->d_10_bit_r_counter) + 1;
 154     fprintf(stderr, "Band Selection: Div %u, Freq %lu\n",
 155         d_regs->d_8_bit_band_select_clock_divider_value,
 156                 INPUT_REF_FREQ/(d_regs->d_8_bit_band_select_clock_divider_value * d_regs->d_10_bit_r_counter) + 1
 157     );
 158         d_regs->_load_register(5);
 159         d_regs->_load_register(3);
 160         d_regs->_load_register(1);
 161         /* load involved registers */
 162         d_regs->_load_register(2);
 163         d_regs->_load_register(4);
 164         d_regs->_load_register(0); /* register 0 must be last */
 165         return true;
 166 }
 167
 168 freq_t
 169 adf4350::_get_freq(void){
 170         /* Calculate the freq from int, frac, mod, ref, r, div:
 171          *  freq = (int + frac/mod) * (ref/r)
 172          * Keep precision by doing multiplies first:
 173          *  freq = (((((((int)*mod) + frac)*ref)/mod)/r)/div)
 174          */
 175         uint64_t temp;
 176         temp = d_regs->d_int;
 177         temp *= d_regs->d_mod;
 178         temp += d_regs->d_frac;
 179         temp *= INPUT_REF_FREQ;
 180         temp /= d_regs->d_mod;
 181         temp /= d_regs->d_10_bit_r_counter;
 182         temp /= (1 << d_regs->d_divider_select);
 183         return temp;
 184 }