2 // Copyright 2008,2009 Free Software Foundation, Inc.
4 // This file is part of GNU Radio
6 // GNU Radio is free software; you can redistribute it and/or modify
7 // it under the terms of the GNU General Public License as published by
8 // the Free Software Foundation; either asversion 3, or (at your option)
11 // GNU Radio is distributed in the hope that it will be useful,
12 // but WITHOUT ANY WARRANTY; without even the implied warranty of
13 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 // GNU General Public License for more details.
16 // You should have received a copy of the GNU General Public License
17 // along with GNU Radio; see the file COPYING. If not, write to
18 // the Free Software Foundation, Inc., 51 Franklin Street,
19 // Boston, MA 02110-1301, USA.
25 #include <usrp/db_flexrf.h>
26 #include <db_base_impl.h>
28 // d'board i/o pin defs
29 // Tx and Rx have shared defs, but different i/o regs
30 #define AUX_RXAGC (1 << 8)
31 #define POWER_UP (1 << 7) // enables power supply
32 #define RX_TXN (1 << 6) // Tx only: T/R antenna switch for TX/RX port
33 #define RX2_RX1N (1 << 6) // Rx only: antenna switch between RX2 and TX/RX port
34 #define ENABLE (1 << 5) // enables mixer
35 #define AUX_SEN (1 << 4)
36 #define AUX_SCLK (1 << 3)
37 #define PLL_LOCK_DETECT (1 << 2)
38 #define AUX_SDO (1 << 1)
39 #define CLOCK_OUT (1 << 0)
41 flexrf_base::flexrf_base(usrp_basic_sptr _usrp, int which, int _power_on)
42 : db_base(_usrp, which), d_power_on(_power_on)
45 @param usrp: instance of usrp.source_c
46 @param which: which side: 0 or 1 corresponding to side A or B respectively
51 d_spi_format = SPI_FMT_MSB | SPI_FMT_HDR_0;
53 usrp()->_write_oe(d_which, 0, 0xffff); // turn off all outputs
54 _enable_refclk(false); // disable refclk
59 flexrf_base::~flexrf_base()
65 flexrf_base::_write_all(int R, int control, int N)
68 Write R counter latch, control latch and N counter latch to VCO.
70 Adds 10ms delay between writing control and N if this is first call.
71 This is the required power-up sequence.
73 @param R: 24-bit R counter latch
75 @param control: 24-bit control latch
77 @param N: 24-bit N counter latch
85 _write_control(control);
95 flexrf_base::_write_control(int control)
97 _write_it((control & ~0x3) | 0);
101 flexrf_base::_write_R(int R)
103 _write_it((R & ~0x3) | 1);
107 flexrf_base::_write_N(int N)
109 _write_it((N & ~0x3) | 2);
113 flexrf_base::_write_it(int v)
116 s[0] = (char)((v >> 16) & 0xff);
117 s[1] = (char)((v >> 8) & 0xff);
118 s[2] = (char)(v & 0xff);
119 std::string str(s, 3);
120 usrp()->_write_spi(0, d_spi_enable, d_spi_format, str);
124 flexrf_base::_lock_detect()
127 @returns: the value of the VCO/PLL lock detect bit.
130 if(usrp()->read_io(d_which) & PLL_LOCK_DETECT) {
133 else { // Give it a second chance
134 // FIXME: make portable sleep
137 t.tv_nsec = 100000000;
140 if(usrp()->read_io(d_which) & PLL_LOCK_DETECT) {
150 flexrf_base::_compute_regs(double freq, int &retR, int &retcontrol,
151 int &retN, double &retfreq)
154 Determine values of R, control, and N registers, along with actual freq.
156 @param freq: target frequency in Hz
158 @returns: (R, control, N, actual_freq)
159 @rtype: tuple(int, int, int, float)
161 Override this in derived classes.
164 //raise NotImplementedError;
165 throw std::runtime_error("_compute_regs called from flexrf_base\n");
169 flexrf_base::_compute_control_reg()
171 return d_common->_compute_control_reg();
175 flexrf_base::_refclk_divisor()
177 return d_common->_refclk_divisor();
181 flexrf_base::_refclk_freq()
183 return 64e6/_refclk_divisor();
187 flexrf_base::set_freq(double freq)
190 @returns (ok, actual_baseband_freq) where:
191 ok is True or False and indicates success or failure,
192 actual_baseband_freq is the RF frequency that corresponds to DC in the IF.
195 struct freq_result_t args = {false, 0};
197 // Offsetting the LO helps get the Tx carrier leakage out of the way.
198 // This also ensures that on Rx, we're not getting hosed by the
199 // FPGA's DC removal loop's time constant. We were seeing a
200 // problem when running with discontinuous transmission.
201 // Offsetting the LO made the problem go away.
206 _compute_regs(freq, R, control, N, actual_freq);
212 _write_all(R, control, N);
213 args.ok = _lock_detect();
214 args.baseband_freq = actual_freq;
219 flexrf_base::_set_pga(float pga_gain)
222 usrp()->set_pga(0, pga_gain);
223 usrp()->set_pga(1, pga_gain);
226 usrp()->set_pga(2, pga_gain);
227 usrp()->set_pga(3, pga_gain);
233 flexrf_base::is_quadrature()
236 Return True if this board requires both I & Q analog channels.
238 This bit of info is useful when setting up the USRP Rx mux register.
244 flexrf_base::freq_min()
246 return d_common->freq_min();
250 flexrf_base::freq_max()
252 return d_common->freq_max();
255 // ----------------------------------------------------------------
257 flexrf_base_tx::flexrf_base_tx(usrp_basic_sptr _usrp, int which, int _power_on)
258 : flexrf_base(_usrp, which, _power_on)
261 @param usrp: instance of usrp.sink_c
262 @param which: 0 or 1 corresponding to side TX_A or TX_B respectively.
266 d_spi_enable = SPI_ENABLE_TX_A;
269 d_spi_enable = SPI_ENABLE_TX_B;
272 // power up the transmit side, but don't enable the mixer
273 usrp()->_write_oe(d_which,(POWER_UP|RX_TXN|ENABLE), 0xffff);
274 usrp()->write_io(d_which, (power_on()|RX_TXN), (POWER_UP|RX_TXN|ENABLE));
277 set_gain((gain_min() + gain_max()) / 2.0); // initialize gain
280 flexrf_base_tx::~flexrf_base_tx()
287 flexrf_base_tx::shutdown()
289 // fprintf(stderr, "flexrf_base_tx::shutdown d_is_shutdown = %d\n", d_is_shutdown);
292 d_is_shutdown = true;
293 // do whatever there is to do to shutdown
295 // Power down and leave the T/R switch in the R position
296 usrp()->write_io(d_which, (power_off()|RX_TXN), (POWER_UP|RX_TXN|ENABLE));
298 // Power down VCO/PLL
301 _write_control(_compute_control_reg());
302 _enable_refclk(false); // turn off refclk
308 flexrf_base_tx::set_auto_tr(bool on)
312 ok &= set_atr_mask (RX_TXN | ENABLE);
313 ok &= set_atr_txval(0 | ENABLE);
314 ok &= set_atr_rxval(RX_TXN | 0);
317 ok &= set_atr_mask (0);
318 ok &= set_atr_txval(0);
319 ok &= set_atr_rxval(0);
325 flexrf_base_tx::set_enable(bool on)
328 Enable transmitter if on is true
332 int mask = RX_TXN | ENABLE;
339 return usrp()->write_io(d_which, v, mask);
343 flexrf_base_tx::gain_min()
345 return usrp()->pga_max();
349 flexrf_base_tx::gain_max()
351 return usrp()->pga_max();
355 flexrf_base_tx::gain_db_per_step()
361 flexrf_base_tx::set_gain(float gain)
366 @param gain: gain in decibels
369 return _set_pga(usrp()->pga_max());
373 /**************************************************************************/
376 flexrf_base_rx::flexrf_base_rx(usrp_basic_sptr _usrp, int which, int _power_on)
377 : flexrf_base(_usrp, which, _power_on)
380 @param usrp: instance of usrp.source_c
381 @param which: 0 or 1 corresponding to side RX_A or RX_B respectively.
385 d_spi_enable = SPI_ENABLE_RX_A;
388 d_spi_enable = SPI_ENABLE_RX_B;
391 usrp()->_write_oe(d_which, (POWER_UP|RX2_RX1N|ENABLE), 0xffff);
392 usrp()->write_io(d_which, (power_on()|RX2_RX1N|ENABLE),
393 (POWER_UP|RX2_RX1N|ENABLE));
395 // set up for RX on TX/RX port
396 select_rx_antenna("TX/RX");
398 bypass_adc_buffers(true);
403 flexrf_base_rx::~flexrf_base_rx()
409 flexrf_base_rx::shutdown()
411 // fprintf(stderr, "flexrf_base_rx::shutdown d_is_shutdown = %d\n", d_is_shutdown);
414 d_is_shutdown = true;
415 // do whatever there is to do to shutdown
418 usrp()->common_write_io(C_RX, d_which, power_off(), (POWER_UP|ENABLE));
420 // Power down VCO/PLL
424 // fprintf(stderr, "flexrf_base_rx::shutdown before _write_control\n");
425 _write_control(_compute_control_reg());
427 // fprintf(stderr, "flexrf_base_rx::shutdown before _enable_refclk\n");
428 _enable_refclk(false); // turn off refclk
430 // fprintf(stderr, "flexrf_base_rx::shutdown before set_auto_tr\n");
433 // fprintf(stderr, "flexrf_base_rx::shutdown after set_auto_tr\n");
438 flexrf_base_rx::set_auto_tr(bool on)
442 ok &= set_atr_mask (ENABLE);
443 ok &= set_atr_txval( 0);
444 ok &= set_atr_rxval(ENABLE);
447 ok &= set_atr_mask (0);
448 ok &= set_atr_txval(0);
449 ok &= set_atr_rxval(0);
455 flexrf_base_rx::select_rx_antenna(int which_antenna)
458 Specify which antenna port to use for reception.
459 @param which_antenna: either 'TX/RX' or 'RX2'
462 if(which_antenna == 0) {
463 usrp()->write_io(d_which, 0,RX2_RX1N);
465 else if(which_antenna == 1) {
466 usrp()->write_io(d_which, RX2_RX1N, RX2_RX1N);
470 // throw std::invalid_argument("which_antenna must be either 'TX/RX' or 'RX2'\n");
476 flexrf_base_rx::select_rx_antenna(const std::string &which_antenna)
479 Specify which antenna port to use for reception.
480 @param which_antenna: either 'TX/RX' or 'RX2'
483 if(which_antenna == "TX/RX") {
484 usrp()->write_io(d_which, 0, RX2_RX1N);
486 else if(which_antenna == "RX2") {
487 usrp()->write_io(d_which, RX2_RX1N, RX2_RX1N);
490 // throw std::invalid_argument("which_antenna must be either 'TX/RX' or 'RX2'\n");
497 flexrf_base_rx::set_gain(float gain)
502 @param gain: gain in decibels
507 gain = std::max(gain_min(), std::min(gain, gain_max()));
509 float pga_gain, agc_gain;
510 float V_maxgain, V_mingain, V_fullscale, dac_value;
512 float maxgain = gain_max() - usrp()->pga_max();
513 float mingain = gain_min();
515 pga_gain = gain-maxgain;
516 assert(pga_gain <= usrp()->pga_max());
527 dac_value = (agc_gain*(V_maxgain-V_mingain)/(maxgain-mingain) + V_mingain)*4096/V_fullscale;
529 assert(dac_value>=0 && dac_value<4096);
531 return (usrp()->write_aux_dac(d_which, 0, int(dac_value))
532 && _set_pga(int(pga_gain)));
535 // ----------------------------------------------------------------
538 _AD4360_common::_AD4360_common()
540 // R-Register Common Values
541 d_R_RSV = 0; // bits 23,22
542 d_BSC = 3; // bits 21,20 Div by 8 to be safe
543 d_TEST = 0; // bit 19
545 d_ABP = 0; // bit 17,16 3ns
547 // N-Register Common Values
548 d_N_RSV = 0; // bit 7
550 // Control Register Common Values
551 d_PD = 0; // bits 21,20 Normal operation
552 d_PL = 0; // bits 13,12 11mA
553 d_MTLD = 1; // bit 11 enabled
554 d_CPG = 0; // bit 10 CP setting 1
555 d_CP3S = 0; // bit 9 Normal
556 d_PDP = 1; // bit 8 Positive
557 d_MUXOUT = 1; // bits 7:5 Digital Lock Detect
558 d_CR = 0; // bit 4 Normal
559 d_PC = 1; // bits 3,2 Core power 10mA
562 _AD4360_common::~_AD4360_common()
567 _AD4360_common::_compute_regs(double refclk_freq, double freq, int &retR,
568 int &retcontrol, int &retN, double &retfreq)
571 Determine values of R, control, and N registers, along with actual freq.
573 @param freq: target frequency in Hz
575 @returns: (R, control, N, actual_freq)
576 @rtype: tuple(int, int, int, float)
579 // Band-specific N-Register Values
580 //float phdet_freq = _refclk_freq()/d_R_DIV;
581 double phdet_freq = refclk_freq/d_R_DIV;
582 double desired_n = round(freq*d_freq_mult/phdet_freq);
583 double actual_freq = desired_n * phdet_freq;
584 int B = floor(desired_n/_prescaler());
585 int A = desired_n - _prescaler()*B;
586 d_B_DIV = int(B); // bits 20:8
587 d_A_DIV = int(A); // bit 6:2
589 //assert db_B_DIV >= db_A_DIV
590 if(d_B_DIV < d_A_DIV) {
598 int R = (d_R_RSV<<22) | (d_BSC<<20) | (d_TEST<<19) |
599 (d_LDP<<18) | (d_ABP<<16) | (d_R_DIV<<2);
601 int control = _compute_control_reg();
603 int N = (d_DIVSEL<<23) | (d_DIV2<<22) | (d_CPGAIN<<21) |
604 (d_B_DIV<<8) | (d_N_RSV<<7) | (d_A_DIV<<2);
607 retcontrol = control;
609 retfreq = actual_freq/d_freq_mult;
614 _AD4360_common::_compute_control_reg()
616 int control = (d_P<<22) | (d_PD<<20) | (d_CP2<<17) | (d_CP1<<14)
617 | (d_PL<<12) | (d_MTLD<<11) | (d_CPG<<10) | (d_CP3S<<9) | (d_PDP<<8)
618 | (d_MUXOUT<<5) | (d_CR<<4) | (d_PC<<2);
624 _AD4360_common::_refclk_divisor()
627 Return value to stick in REFCLK_DIVISOR register
633 _AD4360_common::_prescaler()
646 //----------------------------------------------------------------------
648 _2400_common::_2400_common()
651 // Band-specific R-Register Values
652 d_R_DIV = 16; // bits 15:2
654 // Band-specific C-Register values
655 d_P = 1; // bits 23,22 Div by 16/17
656 d_CP2 = 7; // bits 19:17
657 d_CP1 = 7; // bits 16:14
659 // Band specifc N-Register Values
660 d_DIVSEL = 0; // bit 23
661 d_DIV2 = 0; // bit 22
662 d_CPGAIN = 0; // bit 21
667 _2400_common::freq_min()
673 _2400_common::freq_max()
678 //----------------------------------------------------------------------
680 _1200_common::_1200_common()
683 // Band-specific R-Register Values
684 d_R_DIV = 16; // bits 15:2 DIV by 16 for a 1 MHz phase detector freq
686 // Band-specific C-Register values
687 d_P = 1; // bits 23,22 Div by 16/17
688 d_CP2 = 7; // bits 19:17 1.25 mA
689 d_CP1 = 7; // bits 16:14 1.25 mA
691 // Band specifc N-Register Values
692 d_DIVSEL = 0; // bit 23
693 d_DIV2 = 1; // bit 22
694 d_CPGAIN = 0; // bit 21
699 _1200_common::freq_min()
705 _1200_common::freq_max()
710 //-------------------------------------------------------------------------
712 _1800_common::_1800_common()
715 // Band-specific R-Register Values
716 d_R_DIV = 16; // bits 15:2 DIV by 16 for a 1 MHz phase detector freq
718 // Band-specific C-Register values
719 d_P = 1; // bits 23,22 Div by 16/17
720 d_CP2 = 7; // bits 19:17 1.25 mA
721 d_CP1 = 7; // bits 16:14 1.25 mA
723 // Band specifc N-Register Values
724 d_DIVSEL = 0; // bit 23
725 d_DIV2 = 0; // bit 22
727 d_CPGAIN = 0; // bit 21
731 _1800_common::freq_min()
737 _1800_common::freq_max()
742 //-------------------------------------------------------------------------
744 _900_common::_900_common()
747 // Band-specific R-Register Values
748 d_R_DIV = 16; // bits 15:2 DIV by 16 for a 1 MHz phase detector freq
750 // Band-specific C-Register values
751 d_P = 1; // bits 23,22 Div by 16/17
752 d_CP2 = 7; // bits 19:17 1.25 mA
753 d_CP1 = 7; // bits 16:14 1.25 mA
755 // Band specifc N-Register Values
756 d_DIVSEL = 0; // bit 23
757 d_DIV2 = 1; // bit 22
759 d_CPGAIN = 0; // bit 21
763 _900_common::freq_min()
769 _900_common::freq_max()
774 //-------------------------------------------------------------------------
776 _400_common::_400_common()
779 // Band-specific R-Register Values
780 d_R_DIV = 16; // bits 15:2
782 // Band-specific C-Register values
783 d_P = 0; // bits 23,22 Div by 8/9
784 d_CP2 = 7; // bits 19:17 1.25 mA
785 d_CP1 = 7; // bits 16:14 1.25 mA
787 // Band specifc N-Register Values These are different for TX/RX
788 d_DIVSEL = 0; // bit 23
791 d_CPGAIN = 0; // bit 21
795 _400_common::freq_min()
801 _400_common::freq_max()
809 d_DIV2 = 1; // bit 22
815 d_DIV2 = 0; // bit 22 // RX side has built-in DIV2 in AD8348
818 //------------------------------------------------------------
820 db_flexrf_2400_tx::db_flexrf_2400_tx(usrp_basic_sptr usrp, int which)
821 : flexrf_base_tx(usrp, which)
823 d_common = new _2400_common();
826 db_flexrf_2400_tx::~db_flexrf_2400_tx()
831 db_flexrf_2400_tx::_compute_regs(double freq, int &retR, int &retcontrol,
832 int &retN, double &retfreq)
834 return d_common->_compute_regs(_refclk_freq(), freq, retR,
835 retcontrol, retN, retfreq);
840 db_flexrf_2400_rx::db_flexrf_2400_rx(usrp_basic_sptr usrp, int which)
841 : flexrf_base_rx(usrp, which)
843 d_common = new _2400_common();
844 set_gain((gain_min() + gain_max()) / 2.0); // initialize gain
847 db_flexrf_2400_rx::~db_flexrf_2400_rx()
852 db_flexrf_2400_rx::gain_min()
854 return usrp()->pga_min();
858 db_flexrf_2400_rx::gain_max()
860 return usrp()->pga_max()+70;
864 db_flexrf_2400_rx::gain_db_per_step()
871 db_flexrf_2400_rx::i_and_q_swapped()
877 db_flexrf_2400_rx::_compute_regs(double freq, int &retR, int &retcontrol,
878 int &retN, double &retfreq)
880 return d_common->_compute_regs(_refclk_freq(), freq, retR,
881 retcontrol, retN, retfreq);
884 //------------------------------------------------------------
887 db_flexrf_1200_tx::db_flexrf_1200_tx(usrp_basic_sptr usrp, int which)
888 : flexrf_base_tx(usrp, which)
890 d_common = new _1200_common();
893 db_flexrf_1200_tx::~db_flexrf_1200_tx()
898 db_flexrf_1200_tx::_compute_regs(double freq, int &retR, int &retcontrol,
899 int &retN, double &retfreq)
901 return d_common->_compute_regs(_refclk_freq(), freq, retR,
902 retcontrol, retN, retfreq);
908 db_flexrf_1200_rx::db_flexrf_1200_rx(usrp_basic_sptr usrp, int which)
909 : flexrf_base_rx(usrp, which)
911 d_common = new _1200_common();
912 set_gain((gain_min() + gain_max()) / 2.0); // initialize gain
915 db_flexrf_1200_rx::~db_flexrf_1200_rx()
920 db_flexrf_1200_rx::gain_min()
922 return usrp()->pga_min();
926 db_flexrf_1200_rx::gain_max()
928 return usrp()->pga_max()+70;
932 db_flexrf_1200_rx::gain_db_per_step()
938 db_flexrf_1200_rx::i_and_q_swapped()
944 db_flexrf_1200_rx::_compute_regs(double freq, int &retR, int &retcontrol,
945 int &retN, double &retfreq)
947 return d_common->_compute_regs(_refclk_freq(), freq, retR,
948 retcontrol, retN, retfreq);
952 //------------------------------------------------------------
955 db_flexrf_1800_tx::db_flexrf_1800_tx(usrp_basic_sptr usrp, int which)
956 : flexrf_base_tx(usrp, which)
958 d_common = new _1800_common();
961 db_flexrf_1800_tx::~db_flexrf_1800_tx()
966 db_flexrf_1800_tx::_compute_regs(double freq, int &retR, int &retcontrol,
967 int &retN, double &retfreq)
969 return d_common->_compute_regs(_refclk_freq(), freq, retR,
970 retcontrol, retN, retfreq);
975 db_flexrf_1800_rx::db_flexrf_1800_rx(usrp_basic_sptr usrp, int which)
976 : flexrf_base_rx(usrp, which)
978 d_common = new _1800_common();
979 set_gain((gain_min() + gain_max()) / 2.0); // initialize gain
982 db_flexrf_1800_rx::~db_flexrf_1800_rx()
988 db_flexrf_1800_rx::gain_min()
990 return usrp()->pga_min();
994 db_flexrf_1800_rx::gain_max()
996 return usrp()->pga_max()+70;
1000 db_flexrf_1800_rx::gain_db_per_step()
1006 db_flexrf_1800_rx::i_and_q_swapped()
1012 db_flexrf_1800_rx::_compute_regs(double freq, int &retR, int &retcontrol,
1013 int &retN, double &retfreq)
1015 return d_common->_compute_regs(_refclk_freq(), freq, retR,
1016 retcontrol, retN, retfreq);
1020 //------------------------------------------------------------
1023 db_flexrf_900_tx::db_flexrf_900_tx(usrp_basic_sptr usrp, int which)
1024 : flexrf_base_tx(usrp, which)
1026 d_common = new _900_common();
1029 db_flexrf_900_tx::~db_flexrf_900_tx()
1034 db_flexrf_900_tx::_compute_regs(double freq, int &retR, int &retcontrol,
1035 int &retN, double &retfreq)
1037 return d_common->_compute_regs(_refclk_freq(), freq, retR,
1038 retcontrol, retN, retfreq);
1042 db_flexrf_900_rx::db_flexrf_900_rx(usrp_basic_sptr usrp, int which)
1043 : flexrf_base_rx(usrp, which)
1045 d_common = new _900_common();
1046 set_gain((gain_min() + gain_max()) / 2.0); // initialize gain
1049 db_flexrf_900_rx::~db_flexrf_900_rx()
1054 db_flexrf_900_rx::gain_min()
1056 return usrp()->pga_min();
1060 db_flexrf_900_rx::gain_max()
1062 return usrp()->pga_max()+70;
1066 db_flexrf_900_rx::gain_db_per_step()
1072 db_flexrf_900_rx::i_and_q_swapped()
1078 db_flexrf_900_rx::_compute_regs(double freq, int &retR, int &retcontrol,
1079 int &retN, double &retfreq)
1081 return d_common->_compute_regs(_refclk_freq(), freq, retR,
1082 retcontrol, retN, retfreq);
1085 //------------------------------------------------------------
1088 db_flexrf_400_tx::db_flexrf_400_tx(usrp_basic_sptr usrp, int which)
1089 : flexrf_base_tx(usrp, which, POWER_UP)
1091 d_common = new _400_tx();
1094 db_flexrf_400_tx::~db_flexrf_400_tx()
1099 db_flexrf_400_tx::_compute_regs(double freq, int &retR, int &retcontrol,
1100 int &retN, double &retfreq)
1102 return d_common->_compute_regs(_refclk_freq(), freq, retR,
1103 retcontrol, retN, retfreq);
1108 db_flexrf_400_rx::db_flexrf_400_rx(usrp_basic_sptr usrp, int which)
1109 : flexrf_base_rx(usrp, which, POWER_UP)
1111 d_common = new _400_rx();
1112 set_gain((gain_min() + gain_max()) / 2.0); // initialize gain
1115 db_flexrf_400_rx::~db_flexrf_400_rx()
1120 db_flexrf_400_rx::gain_min()
1122 return usrp()->pga_min();
1126 db_flexrf_400_rx::gain_max()
1128 return usrp()->pga_max()+45;
1133 db_flexrf_400_rx::gain_db_per_step()
1140 db_flexrf_400_rx::i_and_q_swapped()
1146 db_flexrf_400_rx::_compute_regs(double freq, int &retR, int &retcontrol,
1147 int &retN, double &retfreq)
1149 return d_common->_compute_regs(_refclk_freq(), freq, retR,
1150 retcontrol, retN, retfreq);