2 // Copyright 2008,2009 Free Software Foundation, Inc.
4 // This file is part of GNU Radio
6 // GNU Radio is free software; you can redistribute it and/or modify
7 // it under the terms of the GNU General Public License as published by
8 // the Free Software Foundation; either asversion 3, or (at your option)
11 // GNU Radio is distributed in the hope that it will be useful,
12 // but WITHOUT ANY WARRANTY; without even the implied warranty of
13 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 // GNU General Public License for more details.
16 // You should have received a copy of the GNU General Public License
17 // along with GNU Radio; see the file COPYING. If not, write to
18 // the Free Software Foundation, Inc., 51 Franklin Street,
19 // Boston, MA 02110-1301, USA.
25 #include <usrp/db_flexrf.h>
26 #include <db_base_impl.h>
28 // d'board i/o pin defs
29 // Tx and Rx have shared defs, but different i/o regs
30 #define AUX_RXAGC (1 << 8)
31 #define POWER_UP (1 << 7) // enables power supply
32 #define RX_TXN (1 << 6) // Tx only: T/R antenna switch for TX/RX port
33 #define RX2_RX1N (1 << 6) // Rx only: antenna switch between RX2 and TX/RX port
34 #define ENABLE (1 << 5) // enables mixer
35 #define AUX_SEN (1 << 4)
36 #define AUX_SCLK (1 << 3)
37 #define PLL_LOCK_DETECT (1 << 2)
38 #define AUX_SDO (1 << 1)
39 #define CLOCK_OUT (1 << 0)
41 flexrf_base::flexrf_base(usrp_basic_sptr _usrp, int which, int _power_on)
42 : db_base(_usrp, which), d_power_on(_power_on)
45 @param usrp: instance of usrp.source_c
46 @param which: which side: 0 or 1 corresponding to side A or B respectively
51 d_spi_format = SPI_FMT_MSB | SPI_FMT_HDR_0;
53 usrp()->_write_oe(d_which, 0, 0xffff); // turn off all outputs
54 _enable_refclk(false); // disable refclk
59 flexrf_base::~flexrf_base()
65 flexrf_base::_write_all(int R, int control, int N)
68 Write R counter latch, control latch and N counter latch to VCO.
70 Adds 10ms delay between writing control and N if this is first call.
71 This is the required power-up sequence.
73 @param R: 24-bit R counter latch
75 @param control: 24-bit control latch
77 @param N: 24-bit N counter latch
85 _write_control(control);
95 flexrf_base::_write_control(int control)
97 _write_it((control & ~0x3) | 0);
101 flexrf_base::_write_R(int R)
103 _write_it((R & ~0x3) | 1);
107 flexrf_base::_write_N(int N)
109 _write_it((N & ~0x3) | 2);
113 flexrf_base::_write_it(int v)
116 s[0] = (char)((v >> 16) & 0xff);
117 s[1] = (char)((v >> 8) & 0xff);
118 s[2] = (char)(v & 0xff);
119 std::string str(s, 3);
120 usrp()->_write_spi(0, d_spi_enable, d_spi_format, str);
124 flexrf_base::_lock_detect()
127 @returns: the value of the VCO/PLL lock detect bit.
130 if(usrp()->read_io(d_which) & PLL_LOCK_DETECT) {
133 else { // Give it a second chance
134 // FIXME: make portable sleep
137 t.tv_nsec = 100000000;
140 if(usrp()->read_io(d_which) & PLL_LOCK_DETECT) {
150 flexrf_base::_compute_regs(double freq, int &retR, int &retcontrol,
151 int &retN, double &retfreq)
154 Determine values of R, control, and N registers, along with actual freq.
156 @param freq: target frequency in Hz
158 @returns: (R, control, N, actual_freq)
159 @rtype: tuple(int, int, int, float)
161 Override this in derived classes.
164 //raise NotImplementedError;
165 throw std::runtime_error("_compute_regs called from flexrf_base\n");
169 flexrf_base::_compute_control_reg()
171 return d_common->_compute_control_reg();
175 flexrf_base::_refclk_divisor()
177 return d_common->_refclk_divisor();
181 flexrf_base::set_freq(double freq)
184 @returns (ok, actual_baseband_freq) where:
185 ok is True or False and indicates success or failure,
186 actual_baseband_freq is the RF frequency that corresponds to DC in the IF.
189 struct freq_result_t args = {false, 0};
191 // Offsetting the LO helps get the Tx carrier leakage out of the way.
192 // This also ensures that on Rx, we're not getting hosed by the
193 // FPGA's DC removal loop's time constant. We were seeing a
194 // problem when running with discontinuous transmission.
195 // Offsetting the LO made the problem go away.
200 _compute_regs(freq, R, control, N, actual_freq);
206 _write_all(R, control, N);
207 args.ok = _lock_detect();
208 args.baseband_freq = actual_freq;
213 flexrf_base::_set_pga(float pga_gain)
216 usrp()->set_pga(0, pga_gain);
217 usrp()->set_pga(1, pga_gain);
220 usrp()->set_pga(2, pga_gain);
221 usrp()->set_pga(3, pga_gain);
227 flexrf_base::is_quadrature()
230 Return True if this board requires both I & Q analog channels.
232 This bit of info is useful when setting up the USRP Rx mux register.
238 flexrf_base::freq_min()
240 return d_common->freq_min();
244 flexrf_base::freq_max()
246 return d_common->freq_max();
249 // ----------------------------------------------------------------
251 flexrf_base_tx::flexrf_base_tx(usrp_basic_sptr _usrp, int which, int _power_on)
252 : flexrf_base(_usrp, which, _power_on)
255 @param usrp: instance of usrp.sink_c
256 @param which: 0 or 1 corresponding to side TX_A or TX_B respectively.
260 d_spi_enable = SPI_ENABLE_TX_A;
263 d_spi_enable = SPI_ENABLE_TX_B;
266 // power up the transmit side, but don't enable the mixer
267 usrp()->_write_oe(d_which,(POWER_UP|RX_TXN|ENABLE), 0xffff);
268 usrp()->write_io(d_which, (power_on()|RX_TXN), (POWER_UP|RX_TXN|ENABLE));
271 set_gain((gain_min() + gain_max()) / 2.0); // initialize gain
274 flexrf_base_tx::~flexrf_base_tx()
281 flexrf_base_tx::shutdown()
283 // fprintf(stderr, "flexrf_base_tx::shutdown d_is_shutdown = %d\n", d_is_shutdown);
286 d_is_shutdown = true;
287 // do whatever there is to do to shutdown
289 // Power down and leave the T/R switch in the R position
290 usrp()->write_io(d_which, (power_off()|RX_TXN), (POWER_UP|RX_TXN|ENABLE));
292 // Power down VCO/PLL
295 _write_control(_compute_control_reg());
296 _enable_refclk(false); // turn off refclk
302 flexrf_base_tx::set_auto_tr(bool on)
306 ok &= set_atr_mask (RX_TXN | ENABLE);
307 ok &= set_atr_txval(0 | ENABLE);
308 ok &= set_atr_rxval(RX_TXN | 0);
311 ok &= set_atr_mask (0);
312 ok &= set_atr_txval(0);
313 ok &= set_atr_rxval(0);
319 flexrf_base_tx::set_enable(bool on)
322 Enable transmitter if on is true
326 int mask = RX_TXN | ENABLE;
333 return usrp()->write_io(d_which, v, mask);
337 flexrf_base_tx::gain_min()
339 return usrp()->pga_max();
343 flexrf_base_tx::gain_max()
345 return usrp()->pga_max();
349 flexrf_base_tx::gain_db_per_step()
355 flexrf_base_tx::set_gain(float gain)
360 @param gain: gain in decibels
363 return _set_pga(usrp()->pga_max());
367 /**************************************************************************/
370 flexrf_base_rx::flexrf_base_rx(usrp_basic_sptr _usrp, int which, int _power_on)
371 : flexrf_base(_usrp, which, _power_on)
374 @param usrp: instance of usrp.source_c
375 @param which: 0 or 1 corresponding to side RX_A or RX_B respectively.
379 d_spi_enable = SPI_ENABLE_RX_A;
382 d_spi_enable = SPI_ENABLE_RX_B;
385 usrp()->_write_oe(d_which, (POWER_UP|RX2_RX1N|ENABLE), 0xffff);
386 usrp()->write_io(d_which, (power_on()|RX2_RX1N|ENABLE),
387 (POWER_UP|RX2_RX1N|ENABLE));
389 // set up for RX on TX/RX port
390 select_rx_antenna("TX/RX");
392 bypass_adc_buffers(true);
397 flexrf_base_rx::~flexrf_base_rx()
403 flexrf_base_rx::shutdown()
405 // fprintf(stderr, "flexrf_base_rx::shutdown d_is_shutdown = %d\n", d_is_shutdown);
408 d_is_shutdown = true;
409 // do whatever there is to do to shutdown
412 usrp()->common_write_io(C_RX, d_which, power_off(), (POWER_UP|ENABLE));
414 // Power down VCO/PLL
418 // fprintf(stderr, "flexrf_base_rx::shutdown before _write_control\n");
419 _write_control(_compute_control_reg());
421 // fprintf(stderr, "flexrf_base_rx::shutdown before _enable_refclk\n");
422 _enable_refclk(false); // turn off refclk
424 // fprintf(stderr, "flexrf_base_rx::shutdown before set_auto_tr\n");
427 // fprintf(stderr, "flexrf_base_rx::shutdown after set_auto_tr\n");
432 flexrf_base_rx::set_auto_tr(bool on)
436 ok &= set_atr_mask (ENABLE);
437 ok &= set_atr_txval( 0);
438 ok &= set_atr_rxval(ENABLE);
441 ok &= set_atr_mask (0);
442 ok &= set_atr_txval(0);
443 ok &= set_atr_rxval(0);
449 flexrf_base_rx::select_rx_antenna(int which_antenna)
452 Specify which antenna port to use for reception.
453 @param which_antenna: either 'TX/RX' or 'RX2'
456 if(which_antenna == 0) {
457 usrp()->write_io(d_which, 0,RX2_RX1N);
459 else if(which_antenna == 1) {
460 usrp()->write_io(d_which, RX2_RX1N, RX2_RX1N);
464 // throw std::invalid_argument("which_antenna must be either 'TX/RX' or 'RX2'\n");
470 flexrf_base_rx::select_rx_antenna(const std::string &which_antenna)
473 Specify which antenna port to use for reception.
474 @param which_antenna: either 'TX/RX' or 'RX2'
477 if(which_antenna == "TX/RX") {
478 usrp()->write_io(d_which, 0, RX2_RX1N);
480 else if(which_antenna == "RX2") {
481 usrp()->write_io(d_which, RX2_RX1N, RX2_RX1N);
484 // throw std::invalid_argument("which_antenna must be either 'TX/RX' or 'RX2'\n");
491 flexrf_base_rx::set_gain(float gain)
496 @param gain: gain in decibels
501 gain = std::max(gain_min(), std::min(gain, gain_max()));
503 float pga_gain, agc_gain;
504 float V_maxgain, V_mingain, V_fullscale, dac_value;
506 float maxgain = gain_max() - usrp()->pga_max();
507 float mingain = gain_min();
509 pga_gain = gain-maxgain;
510 assert(pga_gain <= usrp()->pga_max());
521 dac_value = (agc_gain*(V_maxgain-V_mingain)/(maxgain-mingain) + V_mingain)*4096/V_fullscale;
523 assert(dac_value>=0 && dac_value<4096);
525 return (usrp()->write_aux_dac(d_which, 0, int(dac_value))
526 && _set_pga(int(pga_gain)));
529 // ----------------------------------------------------------------
532 _AD4360_common::_AD4360_common()
534 // R-Register Common Values
535 d_R_RSV = 0; // bits 23,22
536 d_BSC = 3; // bits 21,20 Div by 8 to be safe
537 d_TEST = 0; // bit 19
539 d_ABP = 0; // bit 17,16 3ns
541 // N-Register Common Values
542 d_N_RSV = 0; // bit 7
544 // Control Register Common Values
545 d_PD = 0; // bits 21,20 Normal operation
546 d_PL = 0; // bits 13,12 11mA
547 d_MTLD = 1; // bit 11 enabled
548 d_CPG = 0; // bit 10 CP setting 1
549 d_CP3S = 0; // bit 9 Normal
550 d_PDP = 1; // bit 8 Positive
551 d_MUXOUT = 1; // bits 7:5 Digital Lock Detect
552 d_CR = 0; // bit 4 Normal
553 d_PC = 1; // bits 3,2 Core power 10mA
556 _AD4360_common::~_AD4360_common()
561 _AD4360_common::_compute_regs(double refclk_freq, double freq, int &retR,
562 int &retcontrol, int &retN, double &retfreq)
565 Determine values of R, control, and N registers, along with actual freq.
567 @param freq: target frequency in Hz
569 @returns: (R, control, N, actual_freq)
570 @rtype: tuple(int, int, int, float)
573 // Band-specific N-Register Values
574 //float phdet_freq = _refclk_freq()/d_R_DIV;
575 double phdet_freq = refclk_freq/d_R_DIV;
576 double desired_n = round(freq*d_freq_mult/phdet_freq);
577 double actual_freq = desired_n * phdet_freq;
578 int B = floor(desired_n/_prescaler());
579 int A = desired_n - _prescaler()*B;
580 d_B_DIV = int(B); // bits 20:8
581 d_A_DIV = int(A); // bit 6:2
583 //assert db_B_DIV >= db_A_DIV
584 if(d_B_DIV < d_A_DIV) {
592 int R = (d_R_RSV<<22) | (d_BSC<<20) | (d_TEST<<19) |
593 (d_LDP<<18) | (d_ABP<<16) | (d_R_DIV<<2);
595 int control = _compute_control_reg();
597 int N = (d_DIVSEL<<23) | (d_DIV2<<22) | (d_CPGAIN<<21) |
598 (d_B_DIV<<8) | (d_N_RSV<<7) | (d_A_DIV<<2);
601 retcontrol = control;
603 retfreq = actual_freq/d_freq_mult;
608 _AD4360_common::_compute_control_reg()
610 int control = (d_P<<22) | (d_PD<<20) | (d_CP2<<17) | (d_CP1<<14)
611 | (d_PL<<12) | (d_MTLD<<11) | (d_CPG<<10) | (d_CP3S<<9) | (d_PDP<<8)
612 | (d_MUXOUT<<5) | (d_CR<<4) | (d_PC<<2);
618 _AD4360_common::_refclk_divisor()
621 Return value to stick in REFCLK_DIVISOR register
627 _AD4360_common::_prescaler()
640 //----------------------------------------------------------------------
642 _2200_common::_2200_common()
645 // Band-specific R-Register Values
646 d_R_DIV = 16; // bits 15:2
648 // Band-specific C-Register values
649 d_P = 1; // bits 23,22 Div by 16/17
650 d_CP2 = 7; // bits 19:17
651 d_CP1 = 7; // bits 16:14
653 // Band specifc N-Register Values
654 d_DIVSEL = 0; // bit 23
655 d_DIV2 = 0; // bit 22
656 d_CPGAIN = 0; // bit 21
661 _2200_common::freq_min()
667 _2200_common::freq_max()
672 //----------------------------------------------------------------------
674 _2400_common::_2400_common()
677 // Band-specific R-Register Values
678 d_R_DIV = 16; // bits 15:2
680 // Band-specific C-Register values
681 d_P = 1; // bits 23,22 Div by 16/17
682 d_CP2 = 7; // bits 19:17
683 d_CP1 = 7; // bits 16:14
685 // Band specifc N-Register Values
686 d_DIVSEL = 0; // bit 23
687 d_DIV2 = 0; // bit 22
688 d_CPGAIN = 0; // bit 21
693 _2400_common::freq_min()
699 _2400_common::freq_max()
704 //----------------------------------------------------------------------
706 _1200_common::_1200_common()
709 // Band-specific R-Register Values
710 d_R_DIV = 16; // bits 15:2 DIV by 16 for a 1 MHz phase detector freq
712 // Band-specific C-Register values
713 d_P = 1; // bits 23,22 Div by 16/17
714 d_CP2 = 7; // bits 19:17 1.25 mA
715 d_CP1 = 7; // bits 16:14 1.25 mA
717 // Band specifc N-Register Values
718 d_DIVSEL = 0; // bit 23
719 d_DIV2 = 1; // bit 22
720 d_CPGAIN = 0; // bit 21
725 _1200_common::freq_min()
731 _1200_common::freq_max()
736 //-------------------------------------------------------------------------
738 _1800_common::_1800_common()
741 // Band-specific R-Register Values
742 d_R_DIV = 16; // bits 15:2 DIV by 16 for a 1 MHz phase detector freq
744 // Band-specific C-Register values
745 d_P = 1; // bits 23,22 Div by 16/17
746 d_CP2 = 7; // bits 19:17 1.25 mA
747 d_CP1 = 7; // bits 16:14 1.25 mA
749 // Band specifc N-Register Values
750 d_DIVSEL = 0; // bit 23
751 d_DIV2 = 0; // bit 22
753 d_CPGAIN = 0; // bit 21
757 _1800_common::freq_min()
763 _1800_common::freq_max()
768 //-------------------------------------------------------------------------
770 _900_common::_900_common()
773 // Band-specific R-Register Values
774 d_R_DIV = 16; // bits 15:2 DIV by 16 for a 1 MHz phase detector freq
776 // Band-specific C-Register values
777 d_P = 1; // bits 23,22 Div by 16/17
778 d_CP2 = 7; // bits 19:17 1.25 mA
779 d_CP1 = 7; // bits 16:14 1.25 mA
781 // Band specifc N-Register Values
782 d_DIVSEL = 0; // bit 23
783 d_DIV2 = 1; // bit 22
785 d_CPGAIN = 0; // bit 21
789 _900_common::freq_min()
795 _900_common::freq_max()
800 //-------------------------------------------------------------------------
802 _400_common::_400_common()
805 // Band-specific R-Register Values
806 d_R_DIV = 16; // bits 15:2
808 // Band-specific C-Register values
809 d_P = 0; // bits 23,22 Div by 8/9
810 d_CP2 = 7; // bits 19:17 1.25 mA
811 d_CP1 = 7; // bits 16:14 1.25 mA
813 // Band specifc N-Register Values These are different for TX/RX
814 d_DIVSEL = 0; // bit 23
817 d_CPGAIN = 0; // bit 21
821 _400_common::freq_min()
827 _400_common::freq_max()
835 d_DIV2 = 1; // bit 22
841 d_DIV2 = 0; // bit 22 // RX side has built-in DIV2 in AD8348
844 //------------------------------------------------------------
846 db_flexrf_2200_tx::db_flexrf_2200_tx(usrp_basic_sptr usrp, int which)
847 : flexrf_base_tx(usrp, which)
849 d_common = new _2200_common();
852 db_flexrf_2200_tx::~db_flexrf_2200_tx()
857 db_flexrf_2200_tx::_compute_regs(double freq, int &retR, int &retcontrol,
858 int &retN, double &retfreq)
860 return d_common->_compute_regs(_refclk_freq(), freq, retR,
861 retcontrol, retN, retfreq);
866 db_flexrf_2200_rx::db_flexrf_2200_rx(usrp_basic_sptr usrp, int which)
867 : flexrf_base_rx(usrp, which)
869 d_common = new _2200_common();
870 set_gain((gain_min() + gain_max()) / 2.0); // initialize gain
873 db_flexrf_2200_rx::~db_flexrf_2200_rx()
878 db_flexrf_2200_rx::gain_min()
880 return usrp()->pga_min();
884 db_flexrf_2200_rx::gain_max()
886 return usrp()->pga_max()+70;
890 db_flexrf_2200_rx::gain_db_per_step()
897 db_flexrf_2200_rx::i_and_q_swapped()
903 db_flexrf_2200_rx::_compute_regs(double freq, int &retR, int &retcontrol,
904 int &retN, double &retfreq)
906 return d_common->_compute_regs(_refclk_freq(), freq, retR,
907 retcontrol, retN, retfreq);
910 //------------------------------------------------------------
912 db_flexrf_2400_tx::db_flexrf_2400_tx(usrp_basic_sptr usrp, int which)
913 : flexrf_base_tx(usrp, which)
915 d_common = new _2400_common();
918 db_flexrf_2400_tx::~db_flexrf_2400_tx()
923 db_flexrf_2400_tx::_compute_regs(double freq, int &retR, int &retcontrol,
924 int &retN, double &retfreq)
926 return d_common->_compute_regs(_refclk_freq(), freq, retR,
927 retcontrol, retN, retfreq);
932 db_flexrf_2400_rx::db_flexrf_2400_rx(usrp_basic_sptr usrp, int which)
933 : flexrf_base_rx(usrp, which)
935 d_common = new _2400_common();
936 set_gain((gain_min() + gain_max()) / 2.0); // initialize gain
939 db_flexrf_2400_rx::~db_flexrf_2400_rx()
944 db_flexrf_2400_rx::gain_min()
946 return usrp()->pga_min();
950 db_flexrf_2400_rx::gain_max()
952 return usrp()->pga_max()+70;
956 db_flexrf_2400_rx::gain_db_per_step()
963 db_flexrf_2400_rx::i_and_q_swapped()
969 db_flexrf_2400_rx::_compute_regs(double freq, int &retR, int &retcontrol,
970 int &retN, double &retfreq)
972 return d_common->_compute_regs(_refclk_freq(), freq, retR,
973 retcontrol, retN, retfreq);
976 //------------------------------------------------------------
979 db_flexrf_1200_tx::db_flexrf_1200_tx(usrp_basic_sptr usrp, int which)
980 : flexrf_base_tx(usrp, which)
982 d_common = new _1200_common();
985 db_flexrf_1200_tx::~db_flexrf_1200_tx()
990 db_flexrf_1200_tx::_compute_regs(double freq, int &retR, int &retcontrol,
991 int &retN, double &retfreq)
993 return d_common->_compute_regs(_refclk_freq(), freq, retR,
994 retcontrol, retN, retfreq);
1000 db_flexrf_1200_rx::db_flexrf_1200_rx(usrp_basic_sptr usrp, int which)
1001 : flexrf_base_rx(usrp, which)
1003 d_common = new _1200_common();
1004 set_gain((gain_min() + gain_max()) / 2.0); // initialize gain
1007 db_flexrf_1200_rx::~db_flexrf_1200_rx()
1012 db_flexrf_1200_rx::gain_min()
1014 return usrp()->pga_min();
1018 db_flexrf_1200_rx::gain_max()
1020 return usrp()->pga_max()+70;
1024 db_flexrf_1200_rx::gain_db_per_step()
1030 db_flexrf_1200_rx::i_and_q_swapped()
1036 db_flexrf_1200_rx::_compute_regs(double freq, int &retR, int &retcontrol,
1037 int &retN, double &retfreq)
1039 return d_common->_compute_regs(_refclk_freq(), freq, retR,
1040 retcontrol, retN, retfreq);
1044 //------------------------------------------------------------
1047 db_flexrf_1800_tx::db_flexrf_1800_tx(usrp_basic_sptr usrp, int which)
1048 : flexrf_base_tx(usrp, which)
1050 d_common = new _1800_common();
1053 db_flexrf_1800_tx::~db_flexrf_1800_tx()
1058 db_flexrf_1800_tx::_compute_regs(double freq, int &retR, int &retcontrol,
1059 int &retN, double &retfreq)
1061 return d_common->_compute_regs(_refclk_freq(), freq, retR,
1062 retcontrol, retN, retfreq);
1067 db_flexrf_1800_rx::db_flexrf_1800_rx(usrp_basic_sptr usrp, int which)
1068 : flexrf_base_rx(usrp, which)
1070 d_common = new _1800_common();
1071 set_gain((gain_min() + gain_max()) / 2.0); // initialize gain
1074 db_flexrf_1800_rx::~db_flexrf_1800_rx()
1080 db_flexrf_1800_rx::gain_min()
1082 return usrp()->pga_min();
1086 db_flexrf_1800_rx::gain_max()
1088 return usrp()->pga_max()+70;
1092 db_flexrf_1800_rx::gain_db_per_step()
1098 db_flexrf_1800_rx::i_and_q_swapped()
1104 db_flexrf_1800_rx::_compute_regs(double freq, int &retR, int &retcontrol,
1105 int &retN, double &retfreq)
1107 return d_common->_compute_regs(_refclk_freq(), freq, retR,
1108 retcontrol, retN, retfreq);
1112 //------------------------------------------------------------
1115 db_flexrf_900_tx::db_flexrf_900_tx(usrp_basic_sptr usrp, int which)
1116 : flexrf_base_tx(usrp, which)
1118 d_common = new _900_common();
1121 db_flexrf_900_tx::~db_flexrf_900_tx()
1126 db_flexrf_900_tx::_compute_regs(double freq, int &retR, int &retcontrol,
1127 int &retN, double &retfreq)
1129 return d_common->_compute_regs(_refclk_freq(), freq, retR,
1130 retcontrol, retN, retfreq);
1134 db_flexrf_900_rx::db_flexrf_900_rx(usrp_basic_sptr usrp, int which)
1135 : flexrf_base_rx(usrp, which)
1137 d_common = new _900_common();
1138 set_gain((gain_min() + gain_max()) / 2.0); // initialize gain
1141 db_flexrf_900_rx::~db_flexrf_900_rx()
1146 db_flexrf_900_rx::gain_min()
1148 return usrp()->pga_min();
1152 db_flexrf_900_rx::gain_max()
1154 return usrp()->pga_max()+70;
1158 db_flexrf_900_rx::gain_db_per_step()
1164 db_flexrf_900_rx::i_and_q_swapped()
1170 db_flexrf_900_rx::_compute_regs(double freq, int &retR, int &retcontrol,
1171 int &retN, double &retfreq)
1173 return d_common->_compute_regs(_refclk_freq(), freq, retR,
1174 retcontrol, retN, retfreq);
1177 //------------------------------------------------------------
1180 db_flexrf_400_tx::db_flexrf_400_tx(usrp_basic_sptr usrp, int which)
1181 : flexrf_base_tx(usrp, which, POWER_UP)
1183 d_common = new _400_tx();
1186 db_flexrf_400_tx::~db_flexrf_400_tx()
1191 db_flexrf_400_tx::_compute_regs(double freq, int &retR, int &retcontrol,
1192 int &retN, double &retfreq)
1194 return d_common->_compute_regs(_refclk_freq(), freq, retR,
1195 retcontrol, retN, retfreq);
1200 db_flexrf_400_rx::db_flexrf_400_rx(usrp_basic_sptr usrp, int which)
1201 : flexrf_base_rx(usrp, which, POWER_UP)
1203 d_common = new _400_rx();
1204 set_gain((gain_min() + gain_max()) / 2.0); // initialize gain
1207 db_flexrf_400_rx::~db_flexrf_400_rx()
1212 db_flexrf_400_rx::gain_min()
1214 return usrp()->pga_min();
1218 db_flexrf_400_rx::gain_max()
1220 return usrp()->pga_max()+45;
1225 db_flexrf_400_rx::gain_db_per_step()
1232 db_flexrf_400_rx::i_and_q_swapped()
1238 db_flexrf_400_rx::_compute_regs(double freq, int &retR, int &retcontrol,
1239 int &retN, double &retfreq)
1241 return d_common->_compute_regs(_refclk_freq(), freq, retR,
1242 retcontrol, retN, retfreq);