10 * ----------------------------------------------------------------------
11 * Mid level interface to the Universal Software Radio Peripheral (Rev 1)
13 * These classes implement the basic functionality for talking to the
14 * USRP. They try to be as independent of the signal processing code
15 * in FPGA as possible. They implement access to the low level
16 * peripherals on the board, provide a common way for reading and
17 * writing registers in the FPGA, and provide the high speed interface
18 * to streaming data across the USB.
20 * It is expected that subclasses will be derived that provide
21 * access to the functionality to a particular FPGA configuration.
22 * ----------------------------------------------------------------------
27 * \brief abstract base class for usrp operations
30 class usrp_basic : boost::noncopyable
33 void shutdown_daughterboards();
36 libusb_device_handle *d_udh;
37 struct libusb_context *d_ctx;
38 int d_usb_data_rate; // bytes/sec
39 int d_bytes_per_poll; // how often to poll for overruns
41 long d_fpga_master_clock_freq;
43 static const int MAX_REGS = 128;
44 unsigned int d_fpga_shadows[MAX_REGS];
46 int d_dbid[2]; // daughterboard ID's (side A, side B)
49 * Shared pointers to subclasses of db_base.
51 * The outer vector is of length 2 (0 = side A, 1 = side B). The
52 * inner vectors are of length 1, 2 or 3 depending on the number of
53 * subdevices implemented by the daugherboard. At this time, only
54 * the Basic Rx and LF Rx implement more than 1 subdevice.
56 std::vector< std::vector<db_base_sptr> > d_db;
58 //! One time call, made only only from usrp_standard_*::make after shared_ptr is created.
59 void init_db(usrp_basic_sptr u);
62 usrp_basic (int which_board,
63 libusb_device_handle *open_interface (libusb_device *dev),
64 const std::string fpga_filename = "",
65 const std::string firmware_filename = "");
68 * \brief advise usrp_basic of usb data rate (bytes/sec)
70 * N.B., this doesn't tweak any hardware. Derived classes
71 * should call this to inform us of the data rate whenever it's
72 * first set or if it changes.
74 * \param usb_data_rate bytes/sec
76 void set_usb_data_rate (int usb_data_rate);
79 * \brief Write auxiliary digital to analog converter.
81 * \param slot Which Tx or Rx slot to write.
82 * N.B., SLOT_TX_A and SLOT_RX_A share the same AUX DAC's.
83 * SLOT_TX_B and SLOT_RX_B share the same AUX DAC's.
84 * \param which_dac [0,3] RX slots must use only 0 and 1. TX slots must use only 2 and 3.
85 * \param value [0,4095]
86 * \returns true iff successful
88 bool _write_aux_dac (int slot, int which_dac, int value);
91 * \brief Read auxiliary analog to digital converter.
93 * \param slot 2-bit slot number. E.g., SLOT_TX_A
94 * \param which_adc [0,1]
95 * \param value return 12-bit value [0,4095]
96 * \returns true iff successful
98 bool _read_aux_adc (int slot, int which_adc, int *value);
101 * \brief Read auxiliary analog to digital converter.
103 * \param slot 2-bit slot number. E.g., SLOT_TX_A
104 * \param which_adc [0,1]
105 * \returns value in the range [0,4095] if successful, else READ_FAILED.
107 int _read_aux_adc (int slot, int which_adc);
111 virtual ~usrp_basic ();
115 * Return a vector of vectors that contain shared pointers
116 * to the daughterboard instance(s) associated with the specified side.
118 * It is an error to use the returned objects after the usrp_basic
119 * object has been destroyed.
121 std::vector<std::vector<db_base_sptr> > db() const { return d_db; }
124 * Return a vector of size >= 1 that contains shared pointers
125 * to the daughterboard instance(s) associated with the specified side.
127 * \param which_side [0,1] which daughterboard
129 * It is an error to use the returned objects after the usrp_basic
130 * object has been destroyed.
132 std::vector<db_base_sptr> db(int which_side);
135 * \brief is the subdev_spec valid?
137 bool is_valid(const usrp_subdev_spec &ss);
140 * \brief given a subdev_spec, return the corresponding daughterboard object.
141 * \throws std::invalid_ argument if ss is invalid.
143 * \param ss specifies the side and subdevice
145 db_base_sptr selected_subdev(const usrp_subdev_spec &ss);
148 * \brief return frequency of master oscillator on USRP
150 long fpga_master_clock_freq () const { return d_fpga_master_clock_freq; }
153 * Tell API that the master oscillator on the USRP is operating at a non-standard
154 * fixed frequency. This is only needed for custom USRP hardware modified to
155 * operate at a different frequency from the default factory configuration. This
156 * function must be called prior to any other API function.
157 * \param master_clock USRP2 FPGA master clock frequency in Hz (10..64 MHz)
159 void set_fpga_master_clock_freq (long master_clock) { d_fpga_master_clock_freq = master_clock; }
162 * \returns usb data rate in bytes/sec
164 int usb_data_rate () const { return d_usb_data_rate; }
166 void set_verbose (bool on) { d_verbose = on; }
168 //! magic value used on alternate register read interfaces
169 static const int READ_FAILED = -99999;
172 * \brief Write EEPROM on motherboard or any daughterboard.
173 * \param i2c_addr I2C bus address of EEPROM
174 * \param eeprom_offset byte offset in EEPROM to begin writing
175 * \param buf the data to write
176 * \returns true iff sucessful
178 bool write_eeprom (int i2c_addr, int eeprom_offset, const std::string buf);
181 * \brief Read EEPROM on motherboard or any daughterboard.
182 * \param i2c_addr I2C bus address of EEPROM
183 * \param eeprom_offset byte offset in EEPROM to begin reading
184 * \param len number of bytes to read
185 * \returns the data read if successful, else a zero length string.
187 std::string read_eeprom (int i2c_addr, int eeprom_offset, int len);
190 * \brief Write to I2C peripheral
191 * \param i2c_addr I2C bus address (7-bits)
192 * \param buf the data to write
193 * \returns true iff successful
194 * Writes are limited to a maximum of of 64 bytes.
196 bool write_i2c (int i2c_addr, const std::string buf);
199 * \brief Read from I2C peripheral
200 * \param i2c_addr I2C bus address (7-bits)
201 * \param len number of bytes to read
202 * \returns the data read if successful, else a zero length string.
203 * Reads are limited to a maximum of 64 bytes.
205 std::string read_i2c (int i2c_addr, int len);
208 * \brief Set ADC offset correction
209 * \param which_adc which ADC[0,3]: 0 = RX_A I, 1 = RX_A Q...
210 * \param offset 16-bit value to subtract from raw ADC input.
212 bool set_adc_offset (int which_adc, int offset);
215 * \brief Set DAC offset correction
216 * \param which_dac which DAC[0,3]: 0 = TX_A I, 1 = TX_A Q...
217 * \param offset 10-bit offset value (ambiguous format: See AD9862 datasheet).
218 * \param offset_pin 1-bit value. If 0 offset applied to -ve differential pin;
219 * If 1 offset applied to +ve differential pin.
221 bool set_dac_offset (int which_dac, int offset, int offset_pin);
224 * \brief Control ADC input buffer
225 * \param which_adc which ADC[0,3]
226 * \param bypass if non-zero, bypass input buffer and connect input
227 * directly to switched cap SHA input of RxPGA.
229 bool set_adc_buffer_bypass (int which_adc, bool bypass);
232 * \brief Enable/disable automatic DC offset removal control loop in FPGA
234 * \param bits which control loops to enable
235 * \param mask which \p bits to pay attention to
237 * If the corresponding bit is set, enable the automatic DC
238 * offset correction control loop.
241 * The 4 low bits are significant:
249 * By default the control loop is enabled on all ADC's.
251 bool set_dc_offset_cl_enable(int bits, int mask);
254 * \brief return the usrp's serial number.
256 * \returns non-zero length string iff successful.
258 std::string serial_number();
261 * \brief Return daughterboard ID for given side [0,1].
263 * \param which_side [0,1] which daughterboard
265 * \return daughterboard id >= 0 if successful
266 * \return -1 if no daugherboard
267 * \return -2 if invalid EEPROM on daughterboard
269 virtual int daughterboard_id (int which_side) const = 0;
272 * \brief Clock ticks to delay rising of T/R signal
273 * \sa write_atr_mask, write_atr_txval, write_atr_rxval
275 bool write_atr_tx_delay(int value);
278 * \brief Clock ticks to delay falling edge of T/R signal
279 * \sa write_atr_mask, write_atr_txval, write_atr_rxval
281 bool write_atr_rx_delay(int value);
284 \f // ================================================================
285 // Routines to access and control daughterboard specific i/o
287 // Those with a common_ prefix access either the Tx or Rx side depending
288 // on the txrx parameter. Those without the common_ prefix are virtual
289 // and are overriden in usrp_basic_rx and usrp_basic_tx to access the
290 // the Rx or Tx sides automatically. We provide the common_ versions
291 // for those daughterboards such as the WBX and XCVR2450 that share
292 // h/w resources (such as the LO) between the Tx and Rx sides.
294 // ----------------------------------------------------------------
295 // BEGIN common_ daughterboard control functions
298 * \brief Set Programmable Gain Amplifier(PGA)
300 * \param txrx Tx or Rx?
301 * \param which_amp which amp [0,3]
302 * \param gain_in_db gain value(linear in dB)
304 * gain is rounded to closest setting supported by hardware.
306 * \returns true iff sucessful.
308 * \sa pga_min(), pga_max(), pga_db_per_step()
310 bool common_set_pga(txrx_t txrx, int which_amp, double gain_in_db);
313 * \brief Return programmable gain amplifier gain setting in dB.
315 * \param txrx Tx or Rx?
316 * \param which_amp which amp [0,3]
318 double common_pga(txrx_t txrx, int which_amp) const;
321 * \brief Return minimum legal PGA gain in dB.
322 * \param txrx Tx or Rx?
324 double common_pga_min(txrx_t txrx) const;
327 * \brief Return maximum legal PGA gain in dB.
328 * \param txrx Tx or Rx?
330 double common_pga_max(txrx_t txrx) const;
333 * \brief Return hardware step size of PGA(linear in dB).
334 * \param txrx Tx or Rx?
336 double common_pga_db_per_step(txrx_t txrx) const;
339 * \brief Write direction register(output enables) for pins that go to daughterboard.
341 * \param txrx Tx or Rx?
342 * \param which_side [0,1] which size
343 * \param value value to write into register
344 * \param mask which bits of value to write into reg
346 * Each d'board has 16-bits of general purpose i/o.
347 * Setting the bit makes it an output from the FPGA to the d'board.
349 * This register is initialized based on a value stored in the
350 * d'board EEPROM. In general, you shouldn't be using this routine
351 * without a very good reason. Using this method incorrectly will
352 * kill your USRP motherboard and/or daughterboard.
354 bool _common_write_oe(txrx_t txrx, int which_side, int value, int mask);
357 * \brief Write daughterboard i/o pin value
359 * \param txrx Tx or Rx?
360 * \param which_side [0,1] which d'board
361 * \param value value to write into register
362 * \param mask which bits of value to write into reg
364 bool common_write_io(txrx_t txrx, int which_side, int value, int mask);
367 * \brief Read daughterboard i/o pin value
369 * \param txrx Tx or Rx?
370 * \param which_side [0,1] which d'board
371 * \param value output
373 bool common_read_io(txrx_t txrx, int which_side, int *value);
376 * \brief Read daughterboard i/o pin value
378 * \param txrx Tx or Rx?
379 * \param which_side [0,1] which d'board
380 * \returns register value if successful, else READ_FAILED
382 int common_read_io(txrx_t txrx, int which_side);
385 * \brief Write daughterboard refclk config register
387 * \param txrx Tx or Rx?
388 * \param which_side [0,1] which d'board
389 * \param value value to write into register, see below
392 * Control whether a reference clock is sent to the daughterboards,
393 * and what frequency. The refclk is sent on d'board i/o pin 0.
396 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
397 * +-----------------------------------------------+-+------------+
398 * | Reserved (Must be zero) |E| DIVISOR |
399 * +-----------------------------------------------+-+------------+
401 * Bit 7 -- 1 turns on refclk, 0 allows IO use
402 * Bits 6:0 Divider value
405 bool common_write_refclk(txrx_t txrx, int which_side, int value);
408 * \brief Automatic Transmit/Receive switching
411 * If automatic transmit/receive (ATR) switching is enabled in the
412 * FR_ATR_CTL register, the presence or absence of data in the FPGA
413 * transmit fifo selects between two sets of values for each of the 4
414 * banks of daughterboard i/o pins.
416 * Each daughterboard slot has 3 16-bit registers associated with it:
417 * FR_ATR_MASK_*, FR_ATR_TXVAL_* and FR_ATR_RXVAL_*
419 * FR_ATR_MASK_{0,1,2,3}:
421 * These registers determine which of the daugherboard i/o pins are
422 * affected by ATR switching. If a bit in the mask is set, the
423 * corresponding i/o bit is controlled by ATR, else it's output
424 * value comes from the normal i/o pin output register:
427 * FR_ATR_TXVAL_{0,1,2,3}:
428 * FR_ATR_RXVAL_{0,1,2,3}:
430 * If the Tx fifo contains data, then the bits from TXVAL that are
431 * selected by MASK are output. Otherwise, the bits from RXVAL that
432 * are selected by MASK are output.
435 bool common_write_atr_mask(txrx_t txrx, int which_side, int value);
436 bool common_write_atr_txval(txrx_t txrx, int which_side, int value);
437 bool common_write_atr_rxval(txrx_t txrx, int which_side, int value);
440 * \brief Write auxiliary digital to analog converter.
442 * \param txrx Tx or Rx?
443 * \param which_side [0,1] which d'board
444 * N.B., SLOT_TX_A and SLOT_RX_A share the same AUX DAC's.
445 * SLOT_TX_B and SLOT_RX_B share the same AUX DAC's.
446 * \param which_dac [2,3] TX slots must use only 2 and 3.
447 * \param value [0,4095]
448 * \returns true iff successful
450 bool common_write_aux_dac(txrx_t txrx, int which_side, int which_dac, int value);
453 * \brief Read auxiliary analog to digital converter.
455 * \param txrx Tx or Rx?
456 * \param which_side [0,1] which d'board
457 * \param which_adc [0,1]
458 * \param value return 12-bit value [0,4095]
459 * \returns true iff successful
461 bool common_read_aux_adc(txrx_t txrx, int which_side, int which_adc, int *value);
464 * \brief Read auxiliary analog to digital converter.
466 * \param txrx Tx or Rx?
467 * \param which_side [0,1] which d'board
468 * \param which_adc [0,1]
469 * \returns value in the range [0,4095] if successful, else READ_FAILED.
471 int common_read_aux_adc(txrx_t txrx, int which_side, int which_adc);
473 // END common_ daughterboard control functions
\f
474 // ----------------------------------------------------------------
475 // BEGIN virtual daughterboard control functions
478 * \brief Set Programmable Gain Amplifier (PGA)
480 * \param which_amp which amp [0,3]
481 * \param gain_in_db gain value (linear in dB)
483 * gain is rounded to closest setting supported by hardware.
485 * \returns true iff sucessful.
487 * \sa pga_min(), pga_max(), pga_db_per_step()
489 virtual bool set_pga (int which_amp, double gain_in_db) = 0;
492 * \brief Return programmable gain amplifier gain setting in dB.
494 * \param which_amp which amp [0,3]
496 virtual double pga (int which_amp) const = 0;
499 * \brief Return minimum legal PGA gain in dB.
501 virtual double pga_min () const = 0;
504 * \brief Return maximum legal PGA gain in dB.
506 virtual double pga_max () const = 0;
509 * \brief Return hardware step size of PGA (linear in dB).
511 virtual double pga_db_per_step () const = 0;
514 * \brief Write direction register (output enables) for pins that go to daughterboard.
516 * \param which_side [0,1] which size
517 * \param value value to write into register
518 * \param mask which bits of value to write into reg
520 * Each d'board has 16-bits of general purpose i/o.
521 * Setting the bit makes it an output from the FPGA to the d'board.
523 * This register is initialized based on a value stored in the
524 * d'board EEPROM. In general, you shouldn't be using this routine
525 * without a very good reason. Using this method incorrectly will
526 * kill your USRP motherboard and/or daughterboard.
528 virtual bool _write_oe (int which_side, int value, int mask) = 0;
531 * \brief Write daughterboard i/o pin value
533 * \param which_side [0,1] which d'board
534 * \param value value to write into register
535 * \param mask which bits of value to write into reg
537 virtual bool write_io (int which_side, int value, int mask) = 0;
540 * \brief Read daughterboard i/o pin value
542 * \param which_side [0,1] which d'board
543 * \param value output
545 virtual bool read_io (int which_side, int *value) = 0;
548 * \brief Read daughterboard i/o pin value
550 * \param which_side [0,1] which d'board
551 * \returns register value if successful, else READ_FAILED
553 virtual int read_io (int which_side) = 0;
556 * \brief Write daughterboard refclk config register
558 * \param which_side [0,1] which d'board
559 * \param value value to write into register, see below
562 * Control whether a reference clock is sent to the daughterboards,
563 * and what frequency. The refclk is sent on d'board i/o pin 0.
566 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
567 * +-----------------------------------------------+-+------------+
568 * | Reserved (Must be zero) |E| DIVISOR |
569 * +-----------------------------------------------+-+------------+
571 * Bit 7 -- 1 turns on refclk, 0 allows IO use
572 * Bits 6:0 Divider value
575 virtual bool write_refclk(int which_side, int value) = 0;
577 virtual bool write_atr_mask(int which_side, int value) = 0;
578 virtual bool write_atr_txval(int which_side, int value) = 0;
579 virtual bool write_atr_rxval(int which_side, int value) = 0;
582 * \brief Write auxiliary digital to analog converter.
584 * \param which_side [0,1] which d'board
585 * N.B., SLOT_TX_A and SLOT_RX_A share the same AUX DAC's.
586 * SLOT_TX_B and SLOT_RX_B share the same AUX DAC's.
587 * \param which_dac [2,3] TX slots must use only 2 and 3.
588 * \param value [0,4095]
589 * \returns true iff successful
591 virtual bool write_aux_dac (int which_side, int which_dac, int value) = 0;
594 * \brief Read auxiliary analog to digital converter.
596 * \param which_side [0,1] which d'board
597 * \param which_adc [0,1]
598 * \param value return 12-bit value [0,4095]
599 * \returns true iff successful
601 virtual bool read_aux_adc (int which_side, int which_adc, int *value) = 0;
604 * \brief Read auxiliary analog to digital converter.
606 * \param which_side [0,1] which d'board
607 * \param which_adc [0,1]
608 * \returns value in the range [0,4095] if successful, else READ_FAILED.
610 virtual int read_aux_adc (int which_side, int which_adc) = 0;
613 * \brief returns current fusb block size
615 virtual int block_size() const = 0;
618 * \brief returns A/D or D/A converter rate in Hz
620 virtual long converter_rate() const = 0;
622 // END virtual daughterboard control functions
\f
624 // ----------------------------------------------------------------
625 // Low level implementation routines.
626 // You probably shouldn't be using these...
629 bool _set_led (int which_led, bool on);
632 * \brief Write FPGA register.
633 * \param regno 7-bit register number
634 * \param value 32-bit value
635 * \returns true iff successful
637 bool _write_fpga_reg (int regno, int value); //< 7-bit regno, 32-bit value
640 * \brief Read FPGA register.
641 * \param regno 7-bit register number
642 * \param value 32-bit value
643 * \returns true iff successful
645 bool _read_fpga_reg (int regno, int *value); //< 7-bit regno, 32-bit value
648 * \brief Read FPGA register.
649 * \param regno 7-bit register number
650 * \returns register value if successful, else READ_FAILED
652 int _read_fpga_reg (int regno);
655 * \brief Write FPGA register with mask.
656 * \param regno 7-bit register number
657 * \param value 16-bit value
658 * \param mask 16-bit value
659 * \returns true if successful
660 * Only use this for registers who actually implement a mask in the verilog firmware, like FR_RX_MASTER_SLAVE
662 bool _write_fpga_reg_masked (int regno, int value, int mask);
665 * \brief Write AD9862 register.
666 * \param which_codec 0 or 1
667 * \param regno 6-bit register number
668 * \param value 8-bit value
669 * \returns true iff successful
671 bool _write_9862 (int which_codec, int regno, unsigned char value);
674 * \brief Read AD9862 register.
675 * \param which_codec 0 or 1
676 * \param regno 6-bit register number
677 * \param value 8-bit value
678 * \returns true iff successful
680 bool _read_9862 (int which_codec, int regno, unsigned char *value) const;
683 * \brief Read AD9862 register.
684 * \param which_codec 0 or 1
685 * \param regno 6-bit register number
686 * \returns register value if successful, else READ_FAILED
688 int _read_9862 (int which_codec, int regno) const;
691 * \brief Write data to SPI bus peripheral.
693 * \param optional_header 0,1 or 2 bytes to write before buf.
694 * \param enables bitmask of peripherals to write. See usrp_spi_defs.h
695 * \param format transaction format. See usrp_spi_defs.h SPI_FMT_*
696 * \param buf the data to write
697 * \returns true iff successful
698 * Writes are limited to a maximum of 64 bytes.
700 * If \p format specifies that optional_header bytes are present, they are
701 * written to the peripheral immediately prior to writing \p buf.
703 bool _write_spi (int optional_header, int enables, int format, std::string buf);
706 * \brief Read data from SPI bus peripheral.
708 * \param optional_header 0,1 or 2 bytes to write before buf.
709 * \param enables bitmask of peripheral to read. See usrp_spi_defs.h
710 * \param format transaction format. See usrp_spi_defs.h SPI_FMT_*
711 * \param len number of bytes to read. Must be in [0,64].
712 * \returns the data read if sucessful, else a zero length string.
714 * Reads are limited to a maximum of 64 bytes.
716 * If \p format specifies that optional_header bytes are present, they
717 * are written to the peripheral first. Then \p len bytes are read from
718 * the peripheral and returned.
720 std::string _read_spi (int optional_header, int enables, int format, int len);
723 * \brief Start data transfers.
724 * Called in base class to derived class order.
729 * \brief Stop data transfers.
730 * Called in base class to derived class order.
736 * \brief class for accessing the receive side of the USRP
739 class usrp_basic_rx : public usrp_basic
742 fusb_devhandle *d_devhandle;
743 fusb_ephandle *d_ephandle;
744 int d_bytes_seen; // how many bytes we've seen
750 * \param which_board Which USRP board on usb (not particularly useful; use 0)
751 * \param fusb_block_size fast usb xfer block size. Must be a multiple of 512.
752 * Use zero for a reasonable default.
753 * \param fusb_nblocks number of fast usb URBs to allocate. Use zero for a reasonable default.
754 * \param fpga_filename name of the rbf file to load
755 * \param firmware_filename name of ihx file to load
757 usrp_basic_rx (int which_board,
758 int fusb_block_size=0,
760 const std::string fpga_filename = "",
761 const std::string firmware_filename = ""
762 ); // throws if trouble
764 bool set_rx_enable (bool on);
765 bool rx_enable () const { return d_rx_enable; }
767 bool disable_rx (); // conditional disable, return prev state
768 void restore_rx (bool on); // conditional set
770 void probe_rx_slots (bool verbose);
776 * \brief invokes constructor, returns instance or 0 if trouble
778 * \param which_board Which USRP board on usb (not particularly useful; use 0)
779 * \param fusb_block_size fast usb xfer block size. Must be a multiple of 512.
780 * Use zero for a reasonable default.
781 * \param fusb_nblocks number of fast usb URBs to allocate. Use zero for a reasonable default.
782 * \param fpga_filename name of file that contains image to load into FPGA
783 * \param firmware_filename name of file that contains image to load into FX2
785 static usrp_basic_rx *make (int which_board,
786 int fusb_block_size=0,
788 const std::string fpga_filename = "",
789 const std::string firmware_filename = ""
793 * \brief tell the fpga the rate rx samples are coming from the A/D's
795 * div = fpga_master_clock_freq () / sample_rate
797 * sample_rate is determined by a myriad of registers
798 * in the 9862. That's why you have to tell us, so
799 * we can tell the fpga.
801 bool set_fpga_rx_sample_rate_divisor (unsigned int div);
804 * \brief read data from the D/A's via the FPGA.
805 * \p len must be a multiple of 512 bytes.
807 * \returns the number of bytes read, or -1 on error.
809 * If overrun is non-NULL it will be set true iff an RX overrun is detected.
811 int read (void *buf, int len, bool *overrun);
814 //! sampling rate of A/D converter
815 virtual long converter_rate() const { return fpga_master_clock_freq(); } // 64M
816 long adc_rate() const { return converter_rate(); }
817 int daughterboard_id (int which_side) const { return d_dbid[which_side & 0x1]; }
819 bool set_pga (int which_amp, double gain_in_db);
820 double pga (int which_amp) const;
821 double pga_min () const;
822 double pga_max () const;
823 double pga_db_per_step () const;
825 bool _write_oe (int which_side, int value, int mask);
826 bool write_io (int which_side, int value, int mask);
827 bool read_io (int which_side, int *value);
828 int read_io (int which_side);
829 bool write_refclk(int which_side, int value);
830 bool write_atr_mask(int which_side, int value);
831 bool write_atr_txval(int which_side, int value);
832 bool write_atr_rxval(int which_side, int value);
834 bool write_aux_dac (int which_side, int which_dac, int value);
835 bool read_aux_adc (int which_side, int which_adc, int *value);
836 int read_aux_adc (int which_side, int which_adc);
838 int block_size() const;
840 // called in base class to derived class order
846 * \brief class for accessing the transmit side of the USRP
849 class usrp_basic_tx : public usrp_basic
852 fusb_devhandle *d_devhandle;
853 fusb_ephandle *d_ephandle;
854 int d_bytes_seen; // how many bytes we've seen
860 * \param which_board Which USRP board on usb (not particularly useful; use 0)
861 * \param fusb_block_size fast usb xfer block size. Must be a multiple of 512.
862 * Use zero for a reasonable default.
863 * \param fusb_nblocks number of fast usb URBs to allocate. Use zero for a reasonable default.
864 * \param fpga_filename name of file that contains image to load into FPGA
865 * \param firmware_filename name of file that contains image to load into FX2
867 usrp_basic_tx (int which_board,
868 int fusb_block_size=0,
870 const std::string fpga_filename = "",
871 const std::string firmware_filename = ""
872 ); // throws if trouble
874 bool set_tx_enable (bool on);
875 bool tx_enable () const { return d_tx_enable; }
877 bool disable_tx (); // conditional disable, return prev state
878 void restore_tx (bool on); // conditional set
880 void probe_tx_slots (bool verbose);
887 * \brief invokes constructor, returns instance or 0 if trouble
889 * \param which_board Which USRP board on usb (not particularly useful; use 0)
890 * \param fusb_block_size fast usb xfer block size. Must be a multiple of 512.
891 * Use zero for a reasonable default.
892 * \param fusb_nblocks number of fast usb URBs to allocate. Use zero for a reasonable default.
893 * \param fpga_filename name of file that contains image to load into FPGA
894 * \param firmware_filename name of file that contains image to load into FX2
896 static usrp_basic_tx *make (int which_board, int fusb_block_size=0, int fusb_nblocks=0,
897 const std::string fpga_filename = "",
898 const std::string firmware_filename = ""
902 * \brief tell the fpga the rate tx samples are going to the D/A's
904 * div = fpga_master_clock_freq () * 2
906 * sample_rate is determined by a myriad of registers
907 * in the 9862. That's why you have to tell us, so
908 * we can tell the fpga.
910 bool set_fpga_tx_sample_rate_divisor (unsigned int div);
913 * \brief Write data to the A/D's via the FPGA.
915 * \p len must be a multiple of 512 bytes.
916 * \returns number of bytes written or -1 on error.
918 * if \p underrun is non-NULL, it will be set to true iff
919 * a transmit underrun condition is detected.
921 int write (const void *buf, int len, bool *underrun);
924 * Block until all outstanding writes have completed.
925 * This is typically used to assist with benchmarking
927 void wait_for_completion ();
929 //! sampling rate of D/A converter
930 virtual long converter_rate() const { return fpga_master_clock_freq () * 2; } // 128M
931 long dac_rate() const { return converter_rate(); }
932 int daughterboard_id (int which_side) const { return d_dbid[which_side & 0x1]; }
934 bool set_pga (int which_amp, double gain_in_db);
935 double pga (int which_amp) const;
936 double pga_min () const;
937 double pga_max () const;
938 double pga_db_per_step () const;
940 bool _write_oe (int which_side, int value, int mask);
941 bool write_io (int which_side, int value, int mask);
942 bool read_io (int which_side, int *value);
943 int read_io (int which_side);
944 bool write_refclk(int which_side, int value);
945 bool write_atr_mask(int which_side, int value);
946 bool write_atr_txval(int which_side, int value);
947 bool write_atr_rxval(int which_side, int value);
949 bool write_aux_dac (int which_side, int which_dac, int value);
950 bool read_aux_adc (int which_side, int which_adc, int *value);
951 int read_aux_adc (int which_side, int which_adc);
953 int block_size() const;
955 // called in base class to derived class order