3 * Copyright 2003,2004,2008,2009 Free Software Foundation, Inc.
5 * This file is part of GNU Radio
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8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 3, or (at your option)
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13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with GNU Radio; see the file COPYING. If not, write to
19 * the Free Software Foundation, Inc., 51 Franklin Street,
20 * Boston, MA 02110-1301, USA.
24 * ----------------------------------------------------------------------
25 * Mid level interface to the Universal Software Radio Peripheral (Rev 1)
27 * These classes implement the basic functionality for talking to the
28 * USRP. They try to be as independent of the signal processing code
29 * in FPGA as possible. They implement access to the low level
30 * peripherals on the board, provide a common way for reading and
31 * writing registers in the FPGA, and provide the high speed interface
32 * to streaming data across the USB.
34 * It is expected that subclasses will be derived that provide
35 * access to the functionality to a particular FPGA configuration.
36 * ----------------------------------------------------------------------
39 #ifndef INCLUDED_USRP_BASIC_H
40 #define INCLUDED_USRP_BASIC_H
42 #include <usrp/db_base.h>
43 #include <usrp/usrp_slots.h>
46 #include <boost/utility.hpp>
47 #include <usrp/usrp_subdev_spec.h>
49 struct libusb_device_handle;
59 * \brief abstract base class for usrp operations
62 class usrp_basic : boost::noncopyable
65 void shutdown_daughterboards();
68 struct libusb_device_handle *d_udh;
69 struct libusb_context *d_ctx;
70 int d_usb_data_rate; // bytes/sec
71 int d_bytes_per_poll; // how often to poll for overruns
73 long d_fpga_master_clock_freq;
75 static const int MAX_REGS = 128;
76 unsigned int d_fpga_shadows[MAX_REGS];
78 int d_dbid[2]; // daughterboard ID's (side A, side B)
81 * Shared pointers to subclasses of db_base.
83 * The outer vector is of length 2 (0 = side A, 1 = side B). The
84 * inner vectors are of length 1, 2 or 3 depending on the number of
85 * subdevices implemented by the daugherboard. At this time, only
86 * the Basic Rx and LF Rx implement more than 1 subdevice.
88 std::vector< std::vector<db_base_sptr> > d_db;
90 //! One time call, made only only from usrp_standard_*::make after shared_ptr is created.
91 void init_db(usrp_basic_sptr u);
94 usrp_basic (int which_board,
95 struct libusb_device_handle *open_interface (struct libusb_device *dev),
96 const std::string fpga_filename = "",
97 const std::string firmware_filename = "");
100 * \brief advise usrp_basic of usb data rate (bytes/sec)
102 * N.B., this doesn't tweak any hardware. Derived classes
103 * should call this to inform us of the data rate whenever it's
104 * first set or if it changes.
106 * \param usb_data_rate bytes/sec
108 void set_usb_data_rate (int usb_data_rate);
111 * \brief Write auxiliary digital to analog converter.
113 * \param slot Which Tx or Rx slot to write.
114 * N.B., SLOT_TX_A and SLOT_RX_A share the same AUX DAC's.
115 * SLOT_TX_B and SLOT_RX_B share the same AUX DAC's.
116 * \param which_dac [0,3] RX slots must use only 0 and 1. TX slots must use only 2 and 3.
117 * \param value [0,4095]
118 * \returns true iff successful
120 bool _write_aux_dac (int slot, int which_dac, int value);
123 * \brief Read auxiliary analog to digital converter.
125 * \param slot 2-bit slot number. E.g., SLOT_TX_A
126 * \param which_adc [0,1]
127 * \param value return 12-bit value [0,4095]
128 * \returns true iff successful
130 bool _read_aux_adc (int slot, int which_adc, int *value);
133 * \brief Read auxiliary analog to digital converter.
135 * \param slot 2-bit slot number. E.g., SLOT_TX_A
136 * \param which_adc [0,1]
137 * \returns value in the range [0,4095] if successful, else READ_FAILED.
139 int _read_aux_adc (int slot, int which_adc);
143 virtual ~usrp_basic ();
147 * Return a vector of vectors that contain shared pointers
148 * to the daughterboard instance(s) associated with the specified side.
150 * It is an error to use the returned objects after the usrp_basic
151 * object has been destroyed.
153 std::vector<std::vector<db_base_sptr> > db() const { return d_db; }
156 * Return a vector of size >= 1 that contains shared pointers
157 * to the daughterboard instance(s) associated with the specified side.
159 * \param which_side [0,1] which daughterboard
161 * It is an error to use the returned objects after the usrp_basic
162 * object has been destroyed.
164 std::vector<db_base_sptr> db(int which_side);
167 * \brief is the subdev_spec valid?
169 bool is_valid(const usrp_subdev_spec &ss);
172 * \brief given a subdev_spec, return the corresponding daughterboard object.
173 * \throws std::invalid_ argument if ss is invalid.
175 * \param ss specifies the side and subdevice
177 db_base_sptr selected_subdev(const usrp_subdev_spec &ss);
180 * \brief return frequency of master oscillator on USRP
182 long fpga_master_clock_freq () const { return d_fpga_master_clock_freq; }
185 * Tell API that the master oscillator on the USRP is operating at a non-standard
186 * fixed frequency. This is only needed for custom USRP hardware modified to
187 * operate at a different frequency from the default factory configuration. This
188 * function must be called prior to any other API function.
189 * \param master_clock USRP2 FPGA master clock frequency in Hz (10..64 MHz)
191 void set_fpga_master_clock_freq (long master_clock) { d_fpga_master_clock_freq = master_clock; }
194 * \returns usb data rate in bytes/sec
196 int usb_data_rate () const { return d_usb_data_rate; }
198 void set_verbose (bool on) { d_verbose = on; }
200 //! magic value used on alternate register read interfaces
201 static const int READ_FAILED = -99999;
204 * \brief Write EEPROM on motherboard or any daughterboard.
205 * \param i2c_addr I2C bus address of EEPROM
206 * \param eeprom_offset byte offset in EEPROM to begin writing
207 * \param buf the data to write
208 * \returns true iff sucessful
210 bool write_eeprom (int i2c_addr, int eeprom_offset, const std::string buf);
213 * \brief Read EEPROM on motherboard or any daughterboard.
214 * \param i2c_addr I2C bus address of EEPROM
215 * \param eeprom_offset byte offset in EEPROM to begin reading
216 * \param len number of bytes to read
217 * \returns the data read if successful, else a zero length string.
219 std::string read_eeprom (int i2c_addr, int eeprom_offset, int len);
222 * \brief Write to I2C peripheral
223 * \param i2c_addr I2C bus address (7-bits)
224 * \param buf the data to write
225 * \returns true iff successful
226 * Writes are limited to a maximum of of 64 bytes.
228 bool write_i2c (int i2c_addr, const std::string buf);
231 * \brief Read from I2C peripheral
232 * \param i2c_addr I2C bus address (7-bits)
233 * \param len number of bytes to read
234 * \returns the data read if successful, else a zero length string.
235 * Reads are limited to a maximum of 64 bytes.
237 std::string read_i2c (int i2c_addr, int len);
240 * \brief Set ADC offset correction
241 * \param which_adc which ADC[0,3]: 0 = RX_A I, 1 = RX_A Q...
242 * \param offset 16-bit value to subtract from raw ADC input.
244 bool set_adc_offset (int which_adc, int offset);
247 * \brief Set DAC offset correction
248 * \param which_dac which DAC[0,3]: 0 = TX_A I, 1 = TX_A Q...
249 * \param offset 10-bit offset value (ambiguous format: See AD9862 datasheet).
250 * \param offset_pin 1-bit value. If 0 offset applied to -ve differential pin;
251 * If 1 offset applied to +ve differential pin.
253 bool set_dac_offset (int which_dac, int offset, int offset_pin);
256 * \brief Control ADC input buffer
257 * \param which_adc which ADC[0,3]
258 * \param bypass if non-zero, bypass input buffer and connect input
259 * directly to switched cap SHA input of RxPGA.
261 bool set_adc_buffer_bypass (int which_adc, bool bypass);
264 * \brief Enable/disable automatic DC offset removal control loop in FPGA
266 * \param bits which control loops to enable
267 * \param mask which \p bits to pay attention to
269 * If the corresponding bit is set, enable the automatic DC
270 * offset correction control loop.
273 * The 4 low bits are significant:
281 * By default the control loop is enabled on all ADC's.
283 bool set_dc_offset_cl_enable(int bits, int mask);
286 * \brief return the usrp's serial number.
288 * \returns non-zero length string iff successful.
290 std::string serial_number();
293 * \brief Return daughterboard ID for given side [0,1].
295 * \param which_side [0,1] which daughterboard
297 * \return daughterboard id >= 0 if successful
298 * \return -1 if no daugherboard
299 * \return -2 if invalid EEPROM on daughterboard
301 virtual int daughterboard_id (int which_side) const = 0;
304 * \brief Clock ticks to delay rising of T/R signal
305 * \sa write_atr_mask, write_atr_txval, write_atr_rxval
307 bool write_atr_tx_delay(int value);
310 * \brief Clock ticks to delay falling edge of T/R signal
311 * \sa write_atr_mask, write_atr_txval, write_atr_rxval
313 bool write_atr_rx_delay(int value);
316 \f // ================================================================
317 // Routines to access and control daughterboard specific i/o
319 // Those with a common_ prefix access either the Tx or Rx side depending
320 // on the txrx parameter. Those without the common_ prefix are virtual
321 // and are overriden in usrp_basic_rx and usrp_basic_tx to access the
322 // the Rx or Tx sides automatically. We provide the common_ versions
323 // for those daughterboards such as the WBX and XCVR2450 that share
324 // h/w resources (such as the LO) between the Tx and Rx sides.
326 // ----------------------------------------------------------------
327 // BEGIN common_ daughterboard control functions
330 * \brief Set Programmable Gain Amplifier(PGA)
332 * \param txrx Tx or Rx?
333 * \param which_amp which amp [0,3]
334 * \param gain_in_db gain value(linear in dB)
336 * gain is rounded to closest setting supported by hardware.
338 * \returns true iff sucessful.
340 * \sa pga_min(), pga_max(), pga_db_per_step()
342 bool common_set_pga(txrx_t txrx, int which_amp, double gain_in_db);
345 * \brief Return programmable gain amplifier gain setting in dB.
347 * \param txrx Tx or Rx?
348 * \param which_amp which amp [0,3]
350 double common_pga(txrx_t txrx, int which_amp) const;
353 * \brief Return minimum legal PGA gain in dB.
354 * \param txrx Tx or Rx?
356 double common_pga_min(txrx_t txrx) const;
359 * \brief Return maximum legal PGA gain in dB.
360 * \param txrx Tx or Rx?
362 double common_pga_max(txrx_t txrx) const;
365 * \brief Return hardware step size of PGA(linear in dB).
366 * \param txrx Tx or Rx?
368 double common_pga_db_per_step(txrx_t txrx) const;
371 * \brief Write direction register(output enables) for pins that go to daughterboard.
373 * \param txrx Tx or Rx?
374 * \param which_side [0,1] which size
375 * \param value value to write into register
376 * \param mask which bits of value to write into reg
378 * Each d'board has 16-bits of general purpose i/o.
379 * Setting the bit makes it an output from the FPGA to the d'board.
381 * This register is initialized based on a value stored in the
382 * d'board EEPROM. In general, you shouldn't be using this routine
383 * without a very good reason. Using this method incorrectly will
384 * kill your USRP motherboard and/or daughterboard.
386 bool _common_write_oe(txrx_t txrx, int which_side, int value, int mask);
389 * \brief Write daughterboard i/o pin value
391 * \param txrx Tx or Rx?
392 * \param which_side [0,1] which d'board
393 * \param value value to write into register
394 * \param mask which bits of value to write into reg
396 bool common_write_io(txrx_t txrx, int which_side, int value, int mask);
399 * \brief Read daughterboard i/o pin value
401 * \param txrx Tx or Rx?
402 * \param which_side [0,1] which d'board
403 * \param value output
405 bool common_read_io(txrx_t txrx, int which_side, int *value);
408 * \brief Read daughterboard i/o pin value
410 * \param txrx Tx or Rx?
411 * \param which_side [0,1] which d'board
412 * \returns register value if successful, else READ_FAILED
414 int common_read_io(txrx_t txrx, int which_side);
417 * \brief Write daughterboard refclk config register
419 * \param txrx Tx or Rx?
420 * \param which_side [0,1] which d'board
421 * \param value value to write into register, see below
424 * Control whether a reference clock is sent to the daughterboards,
425 * and what frequency. The refclk is sent on d'board i/o pin 0.
428 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
429 * +-----------------------------------------------+-+------------+
430 * | Reserved (Must be zero) |E| DIVISOR |
431 * +-----------------------------------------------+-+------------+
433 * Bit 7 -- 1 turns on refclk, 0 allows IO use
434 * Bits 6:0 Divider value
437 bool common_write_refclk(txrx_t txrx, int which_side, int value);
440 * \brief Automatic Transmit/Receive switching
443 * If automatic transmit/receive (ATR) switching is enabled in the
444 * FR_ATR_CTL register, the presence or absence of data in the FPGA
445 * transmit fifo selects between two sets of values for each of the 4
446 * banks of daughterboard i/o pins.
448 * Each daughterboard slot has 3 16-bit registers associated with it:
449 * FR_ATR_MASK_*, FR_ATR_TXVAL_* and FR_ATR_RXVAL_*
451 * FR_ATR_MASK_{0,1,2,3}:
453 * These registers determine which of the daugherboard i/o pins are
454 * affected by ATR switching. If a bit in the mask is set, the
455 * corresponding i/o bit is controlled by ATR, else it's output
456 * value comes from the normal i/o pin output register:
459 * FR_ATR_TXVAL_{0,1,2,3}:
460 * FR_ATR_RXVAL_{0,1,2,3}:
462 * If the Tx fifo contains data, then the bits from TXVAL that are
463 * selected by MASK are output. Otherwise, the bits from RXVAL that
464 * are selected by MASK are output.
467 bool common_write_atr_mask(txrx_t txrx, int which_side, int value);
468 bool common_write_atr_txval(txrx_t txrx, int which_side, int value);
469 bool common_write_atr_rxval(txrx_t txrx, int which_side, int value);
472 * \brief Write auxiliary digital to analog converter.
474 * \param txrx Tx or Rx?
475 * \param which_side [0,1] which d'board
476 * N.B., SLOT_TX_A and SLOT_RX_A share the same AUX DAC's.
477 * SLOT_TX_B and SLOT_RX_B share the same AUX DAC's.
478 * \param which_dac [2,3] TX slots must use only 2 and 3.
479 * \param value [0,4095]
480 * \returns true iff successful
482 bool common_write_aux_dac(txrx_t txrx, int which_side, int which_dac, int value);
485 * \brief Read auxiliary analog to digital converter.
487 * \param txrx Tx or Rx?
488 * \param which_side [0,1] which d'board
489 * \param which_adc [0,1]
490 * \param value return 12-bit value [0,4095]
491 * \returns true iff successful
493 bool common_read_aux_adc(txrx_t txrx, int which_side, int which_adc, int *value);
496 * \brief Read auxiliary analog to digital converter.
498 * \param txrx Tx or Rx?
499 * \param which_side [0,1] which d'board
500 * \param which_adc [0,1]
501 * \returns value in the range [0,4095] if successful, else READ_FAILED.
503 int common_read_aux_adc(txrx_t txrx, int which_side, int which_adc);
505 // END common_ daughterboard control functions
\f
506 // ----------------------------------------------------------------
507 // BEGIN virtual daughterboard control functions
510 * \brief Set Programmable Gain Amplifier (PGA)
512 * \param which_amp which amp [0,3]
513 * \param gain_in_db gain value (linear in dB)
515 * gain is rounded to closest setting supported by hardware.
517 * \returns true iff sucessful.
519 * \sa pga_min(), pga_max(), pga_db_per_step()
521 virtual bool set_pga (int which_amp, double gain_in_db) = 0;
524 * \brief Return programmable gain amplifier gain setting in dB.
526 * \param which_amp which amp [0,3]
528 virtual double pga (int which_amp) const = 0;
531 * \brief Return minimum legal PGA gain in dB.
533 virtual double pga_min () const = 0;
536 * \brief Return maximum legal PGA gain in dB.
538 virtual double pga_max () const = 0;
541 * \brief Return hardware step size of PGA (linear in dB).
543 virtual double pga_db_per_step () const = 0;
546 * \brief Write direction register (output enables) for pins that go to daughterboard.
548 * \param which_side [0,1] which size
549 * \param value value to write into register
550 * \param mask which bits of value to write into reg
552 * Each d'board has 16-bits of general purpose i/o.
553 * Setting the bit makes it an output from the FPGA to the d'board.
555 * This register is initialized based on a value stored in the
556 * d'board EEPROM. In general, you shouldn't be using this routine
557 * without a very good reason. Using this method incorrectly will
558 * kill your USRP motherboard and/or daughterboard.
560 virtual bool _write_oe (int which_side, int value, int mask) = 0;
563 * \brief Write daughterboard i/o pin value
565 * \param which_side [0,1] which d'board
566 * \param value value to write into register
567 * \param mask which bits of value to write into reg
569 virtual bool write_io (int which_side, int value, int mask) = 0;
572 * \brief Read daughterboard i/o pin value
574 * \param which_side [0,1] which d'board
575 * \param value output
577 virtual bool read_io (int which_side, int *value) = 0;
580 * \brief Read daughterboard i/o pin value
582 * \param which_side [0,1] which d'board
583 * \returns register value if successful, else READ_FAILED
585 virtual int read_io (int which_side) = 0;
588 * \brief Write daughterboard refclk config register
590 * \param which_side [0,1] which d'board
591 * \param value value to write into register, see below
594 * Control whether a reference clock is sent to the daughterboards,
595 * and what frequency. The refclk is sent on d'board i/o pin 0.
598 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
599 * +-----------------------------------------------+-+------------+
600 * | Reserved (Must be zero) |E| DIVISOR |
601 * +-----------------------------------------------+-+------------+
603 * Bit 7 -- 1 turns on refclk, 0 allows IO use
604 * Bits 6:0 Divider value
607 virtual bool write_refclk(int which_side, int value) = 0;
609 virtual bool write_atr_mask(int which_side, int value) = 0;
610 virtual bool write_atr_txval(int which_side, int value) = 0;
611 virtual bool write_atr_rxval(int which_side, int value) = 0;
614 * \brief Write auxiliary digital to analog converter.
616 * \param which_side [0,1] which d'board
617 * N.B., SLOT_TX_A and SLOT_RX_A share the same AUX DAC's.
618 * SLOT_TX_B and SLOT_RX_B share the same AUX DAC's.
619 * \param which_dac [2,3] TX slots must use only 2 and 3.
620 * \param value [0,4095]
621 * \returns true iff successful
623 virtual bool write_aux_dac (int which_side, int which_dac, int value) = 0;
626 * \brief Read auxiliary analog to digital converter.
628 * \param which_side [0,1] which d'board
629 * \param which_adc [0,1]
630 * \param value return 12-bit value [0,4095]
631 * \returns true iff successful
633 virtual bool read_aux_adc (int which_side, int which_adc, int *value) = 0;
636 * \brief Read auxiliary analog to digital converter.
638 * \param which_side [0,1] which d'board
639 * \param which_adc [0,1]
640 * \returns value in the range [0,4095] if successful, else READ_FAILED.
642 virtual int read_aux_adc (int which_side, int which_adc) = 0;
645 * \brief returns current fusb block size
647 virtual int block_size() const = 0;
650 * \brief returns A/D or D/A converter rate in Hz
652 virtual long converter_rate() const = 0;
654 // END virtual daughterboard control functions
\f
656 // ----------------------------------------------------------------
657 // Low level implementation routines.
658 // You probably shouldn't be using these...
661 bool _set_led (int which_led, bool on);
664 * \brief Write FPGA register.
665 * \param regno 7-bit register number
666 * \param value 32-bit value
667 * \returns true iff successful
669 bool _write_fpga_reg (int regno, int value); //< 7-bit regno, 32-bit value
672 * \brief Read FPGA register.
673 * \param regno 7-bit register number
674 * \param value 32-bit value
675 * \returns true iff successful
677 bool _read_fpga_reg (int regno, int *value); //< 7-bit regno, 32-bit value
680 * \brief Read FPGA register.
681 * \param regno 7-bit register number
682 * \returns register value if successful, else READ_FAILED
684 int _read_fpga_reg (int regno);
687 * \brief Write FPGA register with mask.
688 * \param regno 7-bit register number
689 * \param value 16-bit value
690 * \param mask 16-bit value
691 * \returns true if successful
692 * Only use this for registers who actually implement a mask in the verilog firmware, like FR_RX_MASTER_SLAVE
694 bool _write_fpga_reg_masked (int regno, int value, int mask);
697 * \brief Write AD9862 register.
698 * \param which_codec 0 or 1
699 * \param regno 6-bit register number
700 * \param value 8-bit value
701 * \returns true iff successful
703 bool _write_9862 (int which_codec, int regno, unsigned char value);
706 * \brief Read AD9862 register.
707 * \param which_codec 0 or 1
708 * \param regno 6-bit register number
709 * \param value 8-bit value
710 * \returns true iff successful
712 bool _read_9862 (int which_codec, int regno, unsigned char *value) const;
715 * \brief Read AD9862 register.
716 * \param which_codec 0 or 1
717 * \param regno 6-bit register number
718 * \returns register value if successful, else READ_FAILED
720 int _read_9862 (int which_codec, int regno) const;
723 * \brief Write data to SPI bus peripheral.
725 * \param optional_header 0,1 or 2 bytes to write before buf.
726 * \param enables bitmask of peripherals to write. See usrp_spi_defs.h
727 * \param format transaction format. See usrp_spi_defs.h SPI_FMT_*
728 * \param buf the data to write
729 * \returns true iff successful
730 * Writes are limited to a maximum of 64 bytes.
732 * If \p format specifies that optional_header bytes are present, they are
733 * written to the peripheral immediately prior to writing \p buf.
735 bool _write_spi (int optional_header, int enables, int format, std::string buf);
738 * \brief Read data from SPI bus peripheral.
740 * \param optional_header 0,1 or 2 bytes to write before buf.
741 * \param enables bitmask of peripheral to read. See usrp_spi_defs.h
742 * \param format transaction format. See usrp_spi_defs.h SPI_FMT_*
743 * \param len number of bytes to read. Must be in [0,64].
744 * \returns the data read if sucessful, else a zero length string.
746 * Reads are limited to a maximum of 64 bytes.
748 * If \p format specifies that optional_header bytes are present, they
749 * are written to the peripheral first. Then \p len bytes are read from
750 * the peripheral and returned.
752 std::string _read_spi (int optional_header, int enables, int format, int len);
755 * \brief Start data transfers.
756 * Called in base class to derived class order.
761 * \brief Stop data transfers.
762 * Called in base class to derived class order.
768 * \brief class for accessing the receive side of the USRP
771 class usrp_basic_rx : public usrp_basic
774 fusb_devhandle *d_devhandle;
775 fusb_ephandle *d_ephandle;
776 int d_bytes_seen; // how many bytes we've seen
782 * \param which_board Which USRP board on usb (not particularly useful; use 0)
783 * \param fusb_block_size fast usb xfer block size. Must be a multiple of 512.
784 * Use zero for a reasonable default.
785 * \param fusb_nblocks number of fast usb URBs to allocate. Use zero for a reasonable default.
786 * \param fpga_filename name of the rbf file to load
787 * \param firmware_filename name of ihx file to load
789 usrp_basic_rx (int which_board,
790 int fusb_block_size=0,
792 const std::string fpga_filename = "",
793 const std::string firmware_filename = ""
794 ); // throws if trouble
796 bool set_rx_enable (bool on);
797 bool rx_enable () const { return d_rx_enable; }
799 bool disable_rx (); // conditional disable, return prev state
800 void restore_rx (bool on); // conditional set
802 void probe_rx_slots (bool verbose);
808 * \brief invokes constructor, returns instance or 0 if trouble
810 * \param which_board Which USRP board on usb (not particularly useful; use 0)
811 * \param fusb_block_size fast usb xfer block size. Must be a multiple of 512.
812 * Use zero for a reasonable default.
813 * \param fusb_nblocks number of fast usb URBs to allocate. Use zero for a reasonable default.
814 * \param fpga_filename name of file that contains image to load into FPGA
815 * \param firmware_filename name of file that contains image to load into FX2
817 static usrp_basic_rx *make (int which_board,
818 int fusb_block_size=0,
820 const std::string fpga_filename = "",
821 const std::string firmware_filename = ""
825 * \brief tell the fpga the rate rx samples are coming from the A/D's
827 * div = fpga_master_clock_freq () / sample_rate
829 * sample_rate is determined by a myriad of registers
830 * in the 9862. That's why you have to tell us, so
831 * we can tell the fpga.
833 bool set_fpga_rx_sample_rate_divisor (unsigned int div);
836 * \brief read data from the D/A's via the FPGA.
837 * \p len must be a multiple of 512 bytes.
839 * \returns the number of bytes read, or -1 on error.
841 * If overrun is non-NULL it will be set true iff an RX overrun is detected.
843 int read (void *buf, int len, bool *overrun);
846 //! sampling rate of A/D converter
847 virtual long converter_rate() const { return fpga_master_clock_freq(); } // 64M
848 long adc_rate() const { return converter_rate(); }
849 int daughterboard_id (int which_side) const { return d_dbid[which_side & 0x1]; }
851 bool set_pga (int which_amp, double gain_in_db);
852 double pga (int which_amp) const;
853 double pga_min () const;
854 double pga_max () const;
855 double pga_db_per_step () const;
857 bool _write_oe (int which_side, int value, int mask);
858 bool write_io (int which_side, int value, int mask);
859 bool read_io (int which_side, int *value);
860 int read_io (int which_side);
861 bool write_refclk(int which_side, int value);
862 bool write_atr_mask(int which_side, int value);
863 bool write_atr_txval(int which_side, int value);
864 bool write_atr_rxval(int which_side, int value);
866 bool write_aux_dac (int which_side, int which_dac, int value);
867 bool read_aux_adc (int which_side, int which_adc, int *value);
868 int read_aux_adc (int which_side, int which_adc);
870 int block_size() const;
872 // called in base class to derived class order
878 * \brief class for accessing the transmit side of the USRP
881 class usrp_basic_tx : public usrp_basic
884 fusb_devhandle *d_devhandle;
885 fusb_ephandle *d_ephandle;
886 int d_bytes_seen; // how many bytes we've seen
892 * \param which_board Which USRP board on usb (not particularly useful; use 0)
893 * \param fusb_block_size fast usb xfer block size. Must be a multiple of 512.
894 * Use zero for a reasonable default.
895 * \param fusb_nblocks number of fast usb URBs to allocate. Use zero for a reasonable default.
896 * \param fpga_filename name of file that contains image to load into FPGA
897 * \param firmware_filename name of file that contains image to load into FX2
899 usrp_basic_tx (int which_board,
900 int fusb_block_size=0,
902 const std::string fpga_filename = "",
903 const std::string firmware_filename = ""
904 ); // throws if trouble
906 bool set_tx_enable (bool on);
907 bool tx_enable () const { return d_tx_enable; }
909 bool disable_tx (); // conditional disable, return prev state
910 void restore_tx (bool on); // conditional set
912 void probe_tx_slots (bool verbose);
919 * \brief invokes constructor, returns instance or 0 if trouble
921 * \param which_board Which USRP board on usb (not particularly useful; use 0)
922 * \param fusb_block_size fast usb xfer block size. Must be a multiple of 512.
923 * Use zero for a reasonable default.
924 * \param fusb_nblocks number of fast usb URBs to allocate. Use zero for a reasonable default.
925 * \param fpga_filename name of file that contains image to load into FPGA
926 * \param firmware_filename name of file that contains image to load into FX2
928 static usrp_basic_tx *make (int which_board, int fusb_block_size=0, int fusb_nblocks=0,
929 const std::string fpga_filename = "",
930 const std::string firmware_filename = ""
934 * \brief tell the fpga the rate tx samples are going to the D/A's
936 * div = fpga_master_clock_freq () * 2
938 * sample_rate is determined by a myriad of registers
939 * in the 9862. That's why you have to tell us, so
940 * we can tell the fpga.
942 bool set_fpga_tx_sample_rate_divisor (unsigned int div);
945 * \brief Write data to the A/D's via the FPGA.
947 * \p len must be a multiple of 512 bytes.
948 * \returns number of bytes written or -1 on error.
950 * if \p underrun is non-NULL, it will be set to true iff
951 * a transmit underrun condition is detected.
953 int write (const void *buf, int len, bool *underrun);
956 * Block until all outstanding writes have completed.
957 * This is typically used to assist with benchmarking
959 void wait_for_completion ();
961 //! sampling rate of D/A converter
962 virtual long converter_rate() const { return fpga_master_clock_freq () * 2; } // 128M
963 long dac_rate() const { return converter_rate(); }
964 int daughterboard_id (int which_side) const { return d_dbid[which_side & 0x1]; }
966 bool set_pga (int which_amp, double gain_in_db);
967 double pga (int which_amp) const;
968 double pga_min () const;
969 double pga_max () const;
970 double pga_db_per_step () const;
972 bool _write_oe (int which_side, int value, int mask);
973 bool write_io (int which_side, int value, int mask);
974 bool read_io (int which_side, int *value);
975 int read_io (int which_side);
976 bool write_refclk(int which_side, int value);
977 bool write_atr_mask(int which_side, int value);
978 bool write_atr_txval(int which_side, int value);
979 bool write_atr_rxval(int which_side, int value);
981 bool write_aux_dac (int which_side, int which_dac, int value);
982 bool read_aux_adc (int which_side, int which_adc, int *value);
983 int read_aux_adc (int which_side, int which_adc);
985 int block_size() const;
987 // called in base class to derived class order