3 // USRP - Universal Software Radio Peripheral
5 // Copyright (C) 2003,2004 Matt Ettus
7 // This program is free software; you can redistribute it and/or modify
8 // it under the terms of the GNU General Public License as published by
9 // the Free Software Foundation; either version 2 of the License, or
10 // (at your option) any later version.
12 // This program is distributed in the hope that it will be useful,
13 // but WITHOUT ANY WARRANTY; without even the implied warranty of
14 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 // GNU General Public License for more details.
17 // You should have received a copy of the GNU General Public License
18 // along with this program; if not, write to the Free Software
19 // Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
22 // Top level module for a full setup with DUCs and DDCs
24 // Define DEBUG_OWNS_IO_PINS if we're using the daughterboard i/o pins
25 // for debugging info. NB, This can kill the m'board and/or d'board if you
26 // have anything except basic d'boards installed.
28 // Uncomment the following to include optional circuitry
30 `include "usrp_std.vh"
31 `include "../../../firmware/include/fpga_regs_common.v"
32 `include "../../../firmware/include/fpga_regs_standard.v"
35 (output MYSTERY_SIGNAL,
46 input wire [11:0] rx_a_a,
47 input wire [11:0] rx_b_a,
48 input wire [11:0] rx_a_b,
49 input wire [11:0] rx_b_b,
51 output wire [13:0] tx_a,
52 output wire [13:0] tx_b,
59 input wire [2:0] usbctl,
60 output wire [1:0] usbrdy,
61 inout [15:0] usbdata, // NB Careful, inout
63 // These are the general purpose i/o's that go to the daughterboard slots
64 inout wire [15:0] io_tx_a,
65 inout wire [15:0] io_tx_b,
66 inout wire [15:0] io_rx_a,
67 inout wire [15:0] io_rx_b
69 wire [15:0] debugdata,debugctrl;
70 assign MYSTERY_SIGNAL = 1'b0;
78 wire have_space, have_pkt_rdy;
79 assign usbrdy[0] = have_space;
80 assign usbrdy[1] = have_pkt_rdy;
82 wire tx_underrun, rx_overrun;
83 wire clear_status = FX2_1;
84 assign FX2_2 = rx_overrun;
85 assign FX2_3 = tx_underrun;
87 wire [15:0] usbdata_out;
89 wire [3:0] dac0mux,dac1mux,dac2mux,dac3mux;
92 wire [3:0] rx_numchan;
93 wire [2:0] tx_numchan;
95 wire [7:0] interp_rate, decim_rate;
96 wire [15:0] tx_debugbus, rx_debugbus;
98 wire enable_tx, enable_rx;
99 wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset;
102 // Tri-state bus macro
103 bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) );
105 assign clk64 = master_clk;
107 wire [15:0] ch0tx,ch1tx,ch2tx,ch3tx; //,ch4tx,ch5tx,ch6tx,ch7tx;
108 wire [15:0] ch0rx,ch1rx,ch2rx,ch3rx,ch4rx,ch5rx,ch6rx,ch7rx;
111 wire [15:0] i_out_0,i_out_1,q_out_0,q_out_1;
112 wire [15:0] bb_tx_i0,bb_tx_q0,bb_tx_i1,bb_tx_q1; // bb_tx_i2,bb_tx_q2,bb_tx_i3,bb_tx_q3;
114 wire strobe_interp, tx_sample_strobe;
118 wire [6:0] serial_addr;
119 wire [31:0] serial_data;
121 reg [15:0] debug_counter;
122 reg [15:0] loopback_i_0,loopback_q_0;
124 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
127 assign bb_tx_i0 = ch0tx;
128 assign bb_tx_q0 = ch1tx;
129 assign bb_tx_i1 = ch2tx;
130 assign bb_tx_q1 = ch3tx;
133 ( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),
134 .usbdata(usbdata),.WR(WR),.have_space(have_space),.tx_underrun(tx_underrun),
135 .channels({tx_numchan,1'b0}),
136 .tx_i_0(ch0tx),.tx_q_0(ch1tx),
137 .tx_i_1(ch2tx),.tx_q_1(ch3tx),
140 .txclk(clk64),.txstrobe(strobe_interp),
141 .clear_status(clear_status),
143 .debugbus(tx_debugbus) );
146 ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
147 .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
148 .interpolator_strobe(strobe_interp),.freq(),
149 .i_in(bb_tx_i0),.q_in(bb_tx_q0),.i_out(i_out_0),.q_out(q_out_0) );
152 ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
153 .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
154 .interpolator_strobe(strobe_interp),.freq(),
155 .i_in(bb_tx_i1),.q_in(bb_tx_q1),.i_out(i_out_1),.q_out(q_out_1) );
157 setting_reg #(`FR_TX_MUX)
158 sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
159 .out({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan}));
161 wire [15:0] tx_a_a = dac0mux[3] ? (dac0mux[1] ? (dac0mux[0] ? q_out_1 : i_out_1) : (dac0mux[0] ? q_out_0 : i_out_0)) : 16'b0;
162 wire [15:0] tx_b_a = dac1mux[3] ? (dac1mux[1] ? (dac1mux[0] ? q_out_1 : i_out_1) : (dac1mux[0] ? q_out_0 : i_out_0)) : 16'b0;
163 wire [15:0] tx_a_b = dac2mux[3] ? (dac2mux[1] ? (dac2mux[0] ? q_out_1 : i_out_1) : (dac2mux[0] ? q_out_0 : i_out_0)) : 16'b0;
164 wire [15:0] tx_b_b = dac3mux[3] ? (dac3mux[1] ? (dac3mux[0] ? q_out_1 : i_out_1) : (dac3mux[0] ? q_out_0 : i_out_0)) : 16'b0;
166 wire txsync = tx_sample_strobe;
167 assign TXSYNC_A = txsync;
168 assign TXSYNC_B = txsync;
170 assign tx_a = txsync ? tx_b_a[15:2] : tx_a_a[15:2];
171 assign tx_b = txsync ? tx_b_b[15:2] : tx_a_b[15:2];
172 `endif // `ifdef TX_ON
174 /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
177 wire rx_sample_strobe,strobe_decim,hb_strobe;
178 wire [15:0] bb_rx_i0,bb_rx_q0,bb_rx_i1,bb_rx_q1,
179 bb_rx_i2,bb_rx_q2,bb_rx_i3,bb_rx_q3;
181 wire loopback = settings[0];
182 wire counter = settings[1];
184 always @(posedge clk64)
186 debug_counter <= #1 16'd0;
188 debug_counter <= #1 16'd0;
190 debug_counter <=#1 debug_counter + 16'd2;
192 always @(posedge clk64)
195 loopback_i_0 <= #1 ch0tx;
196 loopback_q_0 <= #1 ch1tx;
199 assign ch0rx = counter ? debug_counter : loopback ? loopback_i_0 : bb_rx_i0;
200 assign ch1rx = counter ? debug_counter + 16'd1 : loopback ? loopback_q_0 : bb_rx_q0;
201 assign ch2rx = bb_rx_i1;
202 assign ch3rx = bb_rx_q1;
203 assign ch4rx = bb_rx_i2;
204 assign ch5rx = bb_rx_q2;
205 assign ch6rx = bb_rx_i3;
206 assign ch7rx = bb_rx_q3;
208 wire [15:0] ddc0_in_i,ddc0_in_q,ddc1_in_i,ddc1_in_q,ddc2_in_i,ddc2_in_q,ddc3_in_i,ddc3_in_q;
209 wire [31:0] rssi_0,rssi_1,rssi_2,rssi_3;
211 adc_interface adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(1'b1),
212 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
213 .rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(rx_a_b),.rx_b_b(rx_b_b),
214 .rssi_0(rssi_0),.rssi_1(rssi_1),.rssi_2(rssi_2),.rssi_3(rssi_3),
215 .ddc0_in_i(ddc0_in_i),.ddc0_in_q(ddc0_in_q),
216 .ddc1_in_i(ddc1_in_i),.ddc1_in_q(ddc1_in_q),
217 .ddc2_in_i(ddc2_in_i),.ddc2_in_q(ddc2_in_q),
218 .ddc3_in_i(ddc3_in_i),.ddc3_in_q(ddc3_in_q),.rx_numchan(rx_numchan) );
221 ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
222 .reset_regs(rx_dsp_reset),
223 .usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun),
224 .channels(rx_numchan),
225 .ch_0(ch0rx),.ch_1(ch1rx),
226 .ch_2(ch2rx),.ch_3(ch3rx),
227 .ch_4(ch4rx),.ch_5(ch5rx),
228 .ch_6(ch6rx),.ch_7(ch7rx),
229 .rxclk(clk64),.rxstrobe(hb_strobe),
230 .clear_status(clear_status),
231 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
232 .debugbus(rx_debugbus) );
235 rx_chain #(`FR_RX_FREQ_0,`FR_RX_PHASE_0) rx_chain_0
236 ( .clock(clk64),.reset(1'b0),.enable(enable_rx),
237 .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(hb_strobe),
238 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
239 .i_in(ddc0_in_i),.q_in(ddc0_in_q),.i_out(bb_rx_i0),.q_out(bb_rx_q0),.debugdata(debugdata),.debugctrl(debugctrl));
241 assign bb_rx_i0=16'd0;
242 assign bb_rx_q0=16'd0;
246 rx_chain #(`FR_RX_FREQ_1,`FR_RX_PHASE_1) rx_chain_1
247 ( .clock(clk64),.reset(1'b0),.enable(enable_rx),
248 .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
249 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
250 .i_in(ddc1_in_i),.q_in(ddc1_in_q),.i_out(bb_rx_i1),.q_out(bb_rx_q1));
252 assign bb_rx_i1=16'd0;
253 assign bb_rx_q1=16'd0;
257 rx_chain #(`FR_RX_FREQ_2,`FR_RX_PHASE_2) rx_chain_2
258 ( .clock(clk64),.reset(1'b0),.enable(enable_rx),
259 .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
260 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
261 .i_in(ddc2_in_i),.q_in(ddc2_in_q),.i_out(bb_rx_i2),.q_out(bb_rx_q2));
263 assign bb_rx_i2=16'd0;
264 assign bb_rx_q2=16'd0;
268 rx_chain #(`FR_RX_FREQ_3,`FR_RX_PHASE_3) rx_chain_3
269 ( .clock(clk64),.reset(1'b0),.enable(enable_rx),
270 .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
271 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
272 .i_in(ddc3_in_i),.q_in(ddc3_in_q),.i_out(bb_rx_i3),.q_out(bb_rx_q3));
274 assign bb_rx_i3=16'd0;
275 assign bb_rx_q3=16'd0;
278 `endif // `ifdef RX_ON
280 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
283 wire [31:0] capabilities;
284 assign capabilities[7] = `TX_CAP_HB;
285 assign capabilities[6:4] = `TX_CAP_NCHAN;
286 assign capabilities[3] = `RX_CAP_HB;
287 assign capabilities[2:0] = `RX_CAP_NCHAN;
291 ( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI),
292 .enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO),
293 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
294 .readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a),
295 .readback_4(rssi_0),.readback_5(rssi_1),.readback_6(rssi_2),.readback_7(rssi_3)
298 wire [15:0] reg_0,reg_1,reg_2,reg_3;
299 master_control master_control
300 ( .master_clk(clk64),.usbclk(usbclk),
301 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
302 .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset),
303 .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
304 .enable_tx(enable_tx),.enable_rx(enable_rx),
305 .interp_rate(interp_rate),.decim_rate(decim_rate),
306 .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp),
307 .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
309 //.debug_0(rx_a_a),.debug_1(ddc0_in_i),
310 .debug_0(rx_debugbus),.debug_1(ddc0_in_i),
311 .debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,tx_underrun,rx_overrun,decim_rate}),
312 .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) );
315 (.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b),
316 .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3),
317 .clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset),
318 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
320 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
322 setting_reg #(`FR_MODE) sr_misc(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(settings));
324 endmodule // usrp_std