3 // USRP - Universal Software Radio Peripheral
5 // Copyright (C) 2003,2004 Matt Ettus
6 // Copyright 2007 Free Software Foundation, Inc.
8 // This program is free software; you can redistribute it and/or modify
9 // it under the terms of the GNU General Public License as published by
10 // the Free Software Foundation; either version 2 of the License, or
11 // (at your option) any later version.
13 // This program is distributed in the hope that it will be useful,
14 // but WITHOUT ANY WARRANTY; without even the implied warranty of
15 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 // GNU General Public License for more details.
18 // You should have received a copy of the GNU General Public License
19 // along with this program; if not, write to the Free Software
20 // Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
26 `include "../../../firmware/include/fpga_regs_common.v"
27 `include "../../../firmware/include/fpga_regs_standard.v"
29 module usrp_inband_usb
30 (output MYSTERY_SIGNAL,
41 input wire [11:0] rx_a_a,
42 input wire [11:0] rx_b_a,
43 input wire [11:0] rx_a_b,
44 input wire [11:0] rx_b_b,
46 output wire [13:0] tx_a,
47 output wire [13:0] tx_b,
54 input wire [2:0] usbctl,
55 output wire [1:0] usbrdy,
56 inout [15:0] usbdata, // NB Careful, inout
58 // These are the general purpose i/o's that go to the daughterboard slots
59 inout wire [15:0] io_tx_a,
60 inout wire [15:0] io_tx_b,
61 inout wire [15:0] io_rx_a,
62 inout wire [15:0] io_rx_b
64 wire [15:0] debugdata,debugctrl;
65 assign MYSTERY_SIGNAL = 1'b0;
73 wire have_space, have_pkt_rdy;
74 assign usbrdy[0] = have_space;
75 assign usbrdy[1] = have_pkt_rdy;
78 wire clear_status = FX2_1;
79 assign FX2_2 = rx_overrun;
80 assign FX2_3 = (tx_underrun == 0);
82 wire [15:0] usbdata_out;
84 wire [3:0] dac0mux,dac1mux,dac2mux,dac3mux;
87 wire [3:0] rx_numchan;
88 wire [2:0] tx_numchan;
90 wire [7:0] interp_rate, decim_rate;
91 wire [15:0] tx_debugbus, rx_debugbus;
93 wire enable_tx, enable_rx;
94 wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset;
97 // Tri-state bus macro
98 bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) );
100 wire [15:0] ch0tx,ch1tx,ch2tx,ch3tx; //,ch4tx,ch5tx,ch6tx,ch7tx;
101 wire [15:0] ch0rx,ch1rx,ch2rx,ch3rx,ch4rx,ch5rx,ch6rx,ch7rx;
104 wire [15:0] i_out_0,i_out_1,q_out_0,q_out_1;
105 wire [15:0] bb_tx_i0,bb_tx_q0,bb_tx_i1,bb_tx_q1; // bb_tx_i2,bb_tx_q2,bb_tx_i3,bb_tx_q3;
107 wire strobe_interp, tx_sample_strobe;
111 wire [6:0] serial_addr;
112 wire [31:0] serial_data;
114 reg [15:0] debug_counter;
115 reg [15:0] loopback_i_0,loopback_q_0;
118 //Connection RX inband <-> TX inband
120 wire [15:0] rx_databus;
123 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
126 assign bb_tx_i0 = ch0tx;
127 assign bb_tx_q0 = ch1tx;
128 assign bb_tx_i1 = ch2tx;
129 assign bb_tx_q1 = ch3tx;
131 wire [1:0] tx_underrun;
134 tx_buffer_inband tx_buffer
135 ( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),
136 .usbdata(usbdata),.WR(WR),.have_space(have_space),
137 .tx_underrun(tx_underrun),.channels({tx_numchan,1'b0}),
138 .tx_i_0(ch0tx),.tx_q_0(ch1tx),
139 .tx_i_1(ch2tx),.tx_q_1(ch3tx),
142 .txclk(clk64),.txstrobe(strobe_interp),
143 .clear_status(clear_status),
146 .rx_databus(rx_databus),
147 .rx_WR_done(rx_WR_done),
148 .rx_WR_enabled(rx_WR_enabled),
150 .reg_data_out(reg_data_out),
151 .reg_data_in(reg_data_in),
152 .reg_io_enable(reg_io_enable),
153 .debugbus(rx_debugbus),
154 .rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2),
155 .rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait),
156 .stop(stop), .stop_time(stop_time));
159 defparam tx_buffer.NUM_CHAN=2;
164 ( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),
165 .usbdata(usbdata),.WR(WR),.have_space(have_space),.tx_underrun(tx_underrun),
166 .channels({tx_numchan,1'b0}),
167 .tx_i_0(ch0tx),.tx_q_0(ch1tx),
168 .tx_i_1(ch2tx),.tx_q_1(ch3tx),
171 .txclk(clk64),.txstrobe(strobe_interp),
172 .clear_status(clear_status),
173 .tx_empty(tx_empty));
178 ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
179 .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
180 .interpolator_strobe(strobe_interp),.freq(),
181 .i_in(bb_tx_i0),.q_in(bb_tx_q0),.i_out(i_out_0),.q_out(q_out_0) );
183 assign i_out_0=16'd0;
184 assign q_out_0=16'd0;
189 ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
190 .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
191 .interpolator_strobe(strobe_interp),.freq(),
192 .i_in(bb_tx_i1),.q_in(bb_tx_q1),.i_out(i_out_1),.q_out(q_out_1) );
194 assign i_out_1=16'd0;
195 assign q_out_1=16'd0;
198 setting_reg #(`FR_TX_MUX)
199 sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
200 .out({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan}));
202 wire [15:0] tx_a_a = dac0mux[3] ? (dac0mux[1] ? (dac0mux[0] ? q_out_1 : i_out_1) : (dac0mux[0] ? q_out_0 : i_out_0)) : 16'b0;
203 wire [15:0] tx_b_a = dac1mux[3] ? (dac1mux[1] ? (dac1mux[0] ? q_out_1 : i_out_1) : (dac1mux[0] ? q_out_0 : i_out_0)) : 16'b0;
204 wire [15:0] tx_a_b = dac2mux[3] ? (dac2mux[1] ? (dac2mux[0] ? q_out_1 : i_out_1) : (dac2mux[0] ? q_out_0 : i_out_0)) : 16'b0;
205 wire [15:0] tx_b_b = dac3mux[3] ? (dac3mux[1] ? (dac3mux[0] ? q_out_1 : i_out_1) : (dac3mux[0] ? q_out_0 : i_out_0)) : 16'b0;
207 wire txsync = tx_sample_strobe;
208 assign TXSYNC_A = txsync;
209 assign TXSYNC_B = txsync;
211 assign tx_a = txsync ? tx_b_a[15:2] : tx_a_a[15:2];
212 assign tx_b = txsync ? tx_b_b[15:2] : tx_a_b[15:2];
213 `endif // `ifdef TX_ON
215 /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
218 wire rx_sample_strobe,strobe_decim,hb_strobe;
219 wire [15:0] bb_rx_i0,bb_rx_q0,bb_rx_i1,bb_rx_q1,
220 bb_rx_i2,bb_rx_q2,bb_rx_i3,bb_rx_q3;
222 wire loopback = settings[0];
223 wire counter = settings[1];
225 always @(posedge clk64)
227 debug_counter <= #1 16'd0;
229 debug_counter <= #1 16'd0;
231 debug_counter <=#1 debug_counter + 16'd2;
233 always @(posedge clk64)
236 loopback_i_0 <= #1 ch0tx;
237 loopback_q_0 <= #1 ch1tx;
240 assign ch0rx = counter ? debug_counter : loopback ? loopback_i_0 : bb_rx_i0;
241 assign ch1rx = counter ? debug_counter + 16'd1 : loopback ? loopback_q_0 : bb_rx_q0;
242 assign ch2rx = bb_rx_i1;
243 assign ch3rx = bb_rx_q1;
244 assign ch4rx = bb_rx_i2;
245 assign ch5rx = bb_rx_q2;
246 assign ch6rx = bb_rx_i3;
247 assign ch7rx = bb_rx_q3;
249 wire [15:0] ddc0_in_i,ddc0_in_q,ddc1_in_i,ddc1_in_q,ddc2_in_i,ddc2_in_q,ddc3_in_i,ddc3_in_q;
250 wire [31:0] rssi_0,rssi_1,rssi_2,rssi_3;
251 adc_interface adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(1'b1),
252 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
253 .rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(rx_a_b),.rx_b_b(rx_b_b),
254 .rssi_0(rssi_0),.rssi_1(rssi_1),.rssi_2(rssi_2),.rssi_3(rssi_3),
255 .ddc0_in_i(ddc0_in_i),.ddc0_in_q(ddc0_in_q),
256 .ddc1_in_i(ddc1_in_i),.ddc1_in_q(ddc1_in_q),
257 .ddc2_in_i(ddc2_in_i),.ddc2_in_q(ddc2_in_q),
258 .ddc3_in_i(ddc3_in_i),.ddc3_in_q(ddc3_in_q),.rx_numchan(rx_numchan));
260 rx_buffer_inband rx_buffer
261 ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
262 .reset_regs(rx_dsp_reset),
263 .usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun),
264 .channels(rx_numchan),
265 .ch_0(ch0rx),.ch_1(ch1rx),
266 .ch_2(ch2rx),.ch_3(ch3rx),
267 .ch_4(ch4rx),.ch_5(ch5rx),
268 .ch_6(ch6rx),.ch_7(ch7rx),
269 .rxclk(clk64),.rxstrobe(hb_strobe),
270 .clear_status(clear_status),
272 .rx_databus(rx_databus),
273 .rx_WR_done(rx_WR_done),
274 .rx_WR_enabled(rx_WR_enabled),
275 .debugbus(tx_debugbus),
276 .rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), .rssi_3(rssi_3),
277 .tx_underrun(tx_underrun));
280 defparam rx_buffer.NUM_CHAN=2;
285 ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
286 .reset_regs(rx_dsp_reset),
287 .usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun),
288 .channels(rx_numchan),
289 .ch_0(ch0rx),.ch_1(ch1rx),
290 .ch_2(ch2rx),.ch_3(ch3rx),
291 .ch_4(ch4rx),.ch_5(ch5rx),
292 .ch_6(ch6rx),.ch_7(ch7rx),
293 .rxclk(clk64),.rxstrobe(hb_strobe),
294 .clear_status(clear_status),
295 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
299 rx_chain #(`FR_RX_FREQ_0,`FR_RX_PHASE_0) rx_chain_0
300 ( .clock(clk64),.reset(1'b0),.enable(enable_rx),
301 .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(hb_strobe),
302 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
303 .i_in(ddc0_in_i),.q_in(ddc0_in_q),.i_out(bb_rx_i0),.q_out(bb_rx_q0),.debugdata(debugdata),.debugctrl(debugctrl));
305 assign bb_rx_i0=16'd0;
306 assign bb_rx_q0=16'd0;
310 rx_chain #(`FR_RX_FREQ_1,`FR_RX_PHASE_1) rx_chain_1
311 ( .clock(clk64),.reset(1'b0),.enable(enable_rx),
312 .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
313 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
314 .i_in(ddc1_in_i),.q_in(ddc1_in_q),.i_out(bb_rx_i1),.q_out(bb_rx_q1));
316 assign bb_rx_i1=16'd0;
317 assign bb_rx_q1=16'd0;
321 rx_chain #(`FR_RX_FREQ_2,`FR_RX_PHASE_2) rx_chain_2
322 ( .clock(clk64),.reset(1'b0),.enable(enable_rx),
323 .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
324 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
325 .i_in(ddc2_in_i),.q_in(ddc2_in_q),.i_out(bb_rx_i2),.q_out(bb_rx_q2));
327 assign bb_rx_i2=16'd0;
328 assign bb_rx_q2=16'd0;
332 rx_chain #(`FR_RX_FREQ_3,`FR_RX_PHASE_3) rx_chain_3
333 ( .clock(clk64),.reset(1'b0),.enable(enable_rx),
334 .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
335 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
336 .i_in(ddc3_in_i),.q_in(ddc3_in_q),.i_out(bb_rx_i3),.q_out(bb_rx_q3));
338 assign bb_rx_i3=16'd0;
339 assign bb_rx_q3=16'd0;
342 `endif // `ifdef RX_ON
344 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
347 wire [31:0] capabilities;
348 assign capabilities[7] = `TX_CAP_HB;
349 assign capabilities[6:4] = `TX_CAP_NCHAN;
350 assign capabilities[3] = `RX_CAP_HB;
351 assign capabilities[2:0] = `RX_CAP_NCHAN;
354 ( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI),
355 .enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO),
356 .serial_addr(addr_db),.serial_data(data_db),.serial_strobe(strobe_db),
357 .readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a),
358 .readback_4(rssi_0),.readback_5(rssi_1),.readback_6(rssi_2),.readback_7(rssi_3)
362 wire [31:0] reg_data_out;
363 wire [31:0] reg_data_in;
364 wire [1:0] reg_io_enable;
365 wire [31:0] rssi_threshhold;
366 wire [31:0] rssi_wait;
373 assign serial_strobe = strobe_db | strobe_wr;
374 assign serial_addr = (strobe_db)? (addr_db) : (addr_wr);
375 assign serial_data = (strobe_db)? (data_db) : (data_wr);
376 //assign serial_strobe = strobe_wr;
377 //assign serial_data = data_wr;
378 //assign serial_addr = addr_wr;
380 register_io register_control
381 (.clk(clk64),.reset(1'b0),.enable(reg_io_enable),.addr(reg_addr),.datain(reg_data_in),
382 .dataout(reg_data_out), .addr_wr(addr_wr), .data_wr(data_wr), .strobe_wr(strobe_wr),
383 .rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2),
384 .rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait),
385 .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3),
386 .debug_en(debug_en), .misc(settings),
387 .txmux({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan}));
390 //implementing freeze mode
393 wire [15:0] stop_time;
394 assign clk64 = (timestop == 0) ? master_clk : 0;
395 always @(posedge master_clk)
396 if (timestop[15:0] != 0)
397 timestop <= timestop - 16'd1;
399 timestop <= stop_time;
402 wire [15:0] reg_0,reg_1,reg_2,reg_3;
403 master_control master_control
404 ( .master_clk(clk64),.usbclk(usbclk),
405 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
406 .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset),
407 .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
408 .enable_tx(enable_tx),.enable_rx(enable_rx),
409 .interp_rate(interp_rate),.decim_rate(decim_rate),
410 .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp),
411 .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
413 //.debug_0(rx_a_a),.debug_1(ddc0_in_i),
414 .debug_0(rx_debugbus),.debug_1(ddc0_in_i),
415 .debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,tx_underrun,rx_overrun,decim_rate}),
416 .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) );
419 (.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b),
420 .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3),
421 .clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset),
422 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
424 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
426 setting_reg #(`FR_MODE) sr_misc(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(settings));
428 endmodule // usrp_inband_usb