3 `include "../../../firmware/include/fpga_regs_common.v"
4 `include "../../../firmware/include/fpga_regs_standard.v"
6 module mrfm_proc (input clock, input reset, input enable,
7 input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe,
8 input [15:0] signal_in, output wire [15:0] signal_out, output wire sync_out,
9 output wire [15:0] i, output wire [15:0] q,
10 output wire [15:0] ip, output wire [15:0] qp,
11 output wire strobe_out, output wire [63:0] debugbus);
14 wire sample_strobe, strobe_0, strobe_1, strobe_2;
15 assign sample_strobe = 1'b1;
16 wire [7:0] rate_0, rate_1, rate_2;
18 setting_reg #(`FR_MRFM_DECIM) sr_decim(.clock(clock),.reset(reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out({rate_2,rate_1,rate_0}));
20 strobe_gen strobe_gen_0
21 ( .clock(clock),.reset(reset),.enable(enable),
22 .rate(rate_0),.strobe_in(sample_strobe),.strobe(strobe_0) );
23 strobe_gen strobe_gen_1
24 ( .clock(clock),.reset(reset),.enable(enable),
25 .rate(rate_1),.strobe_in(strobe_0),.strobe(strobe_1) );
29 assign sync_out = phase[31];
30 wire [15:0] i_decim_0, i_decim_1, i_decim_2;
31 wire [15:0] q_decim_0, q_decim_1, q_decim_2;
33 wire [15:0] i_interp_0, i_interp_1, i_interp_2;
34 wire [15:0] q_interp_0, q_interp_1, q_interp_2;
36 wire [15:0] i_filt, q_filt, i_comp, q_comp;
41 phase_acc #(`FR_MRFM_FREQ,`FR_MRFM_PHASE,32) rx_phase_acc
42 (.clk(clock),.reset(reset),.enable(enable),
43 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
44 .strobe(sample_strobe),.phase(phase) );
46 cordic rx_cordic (.clock(clock),.reset(reset),.enable(enable),
47 .xi(signal_in),.yi(16'd0),.zi(phase[31:16]),
48 .xo(i_decim_0),.yo(q_decim_0),.zo() );
50 cic_decim cic_decim_i_0 (.clock(clock),.reset(reset),.enable(enable),
51 .rate(rate_0),.strobe_in(sample_strobe),.strobe_out(strobe_0),
52 .signal_in(i_decim_0),.signal_out(i_decim_1));
53 cic_decim cic_decim_i_1 (.clock(clock),.reset(reset),.enable(enable),
54 .rate(rate_1),.strobe_in(strobe_0),.strobe_out(strobe_1),
55 .signal_in(i_decim_1),.signal_out(i));
57 cic_decim cic_decim_q_0 (.clock(clock),.reset(reset),.enable(enable),
58 .rate(rate_0),.strobe_in(sample_strobe),.strobe_out(strobe_0),
59 .signal_in(q_decim_0),.signal_out(q_decim_1));
60 cic_decim cic_decim_q_1 (.clock(clock),.reset(reset),.enable(enable),
61 .rate(rate_1),.strobe_in(strobe_0),.strobe_out(strobe_1),
62 .signal_in(q_decim_1),.signal_out(q));
64 assign strobe_out = strobe_1;
66 biquad_2stage iir_i (.clock(clock),.reset(reset),.strobe_in(strobe_1),
67 .serial_strobe(serial_strobe),.serial_addr(serial_addr),.serial_data(serial_data),
68 .sample_in(i),.sample_out(i_filt),.debugbus(debugbus));
70 biquad_2stage iir_q (.clock(clock),.reset(reset),.strobe_in(strobe_1),
71 .serial_strobe(serial_strobe),.serial_addr(serial_addr),.serial_data(serial_data),
72 .sample_in(q),.sample_out(q_filt),.debugbus());
74 mrfm_compensator compensator (.clock(clock),.reset(reset),.strobe_in(strobe_1),
75 .serial_strobe(serial_strobe),.serial_addr(serial_addr),.serial_data(serial_data),
76 .i_in(i_filt),.q_in(q_filt),.i_out(i_comp),.q_out(q_comp));
78 cic_interp cic_interp_i_0 (.clock(clock),.reset(reset),.enable(enable),
79 .rate(rate_1),.strobe_in(strobe_1),.strobe_out(strobe_0),
80 .signal_in(i_comp),.signal_out(i_interp_0));
81 cic_interp cic_interp_i_1 (.clock(clock),.reset(reset),.enable(enable),
82 .rate(rate_0),.strobe_in(strobe_0),.strobe_out(sample_strobe),
83 .signal_in(i_interp_0),.signal_out(i_interp_1));
85 cic_interp cic_interp_q_0 (.clock(clock),.reset(reset),.enable(enable),
86 .rate(rate_1),.strobe_in(strobe_1),.strobe_out(strobe_0),
87 .signal_in(q_comp),.signal_out(q_interp_0));
88 cic_interp cic_interp_q_1 (.clock(clock),.reset(reset),.enable(enable),
89 .rate(rate_0),.strobe_in(strobe_0),.strobe_out(sample_strobe),
90 .signal_in(q_interp_0),.signal_out(q_interp_1));
92 cordic tx_cordic (.clock(clock),.reset(reset),.enable(enable),
93 .xi(i_interp_1),.yi(q_interp_1),.zi(-phase[31:16]),
94 .xo(signal_out),.yo(),.zo() );
96 endmodule // mrfm_proc