3 // USRP - Universal Software Radio Peripheral
5 // Copyright (C) 2006 Matt Ettus
7 // This program is free software; you can redistribute it and/or modify
8 // it under the terms of the GNU General Public License as published by
9 // the Free Software Foundation; either version 2 of the License, or
10 // (at your option) any later version.
12 // This program is distributed in the hope that it will be useful,
13 // but WITHOUT ANY WARRANTY; without even the implied warranty of
14 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 // GNU General Public License for more details.
17 // You should have received a copy of the GNU General Public License
18 // along with this program; if not, write to the Free Software
19 // Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
22 // Top level module for a full setup with DUCs and DDCs
24 // Uncomment the following to include optional circuitry
27 `include "../../../firmware/include/fpga_regs_common.v"
28 `include "../../../firmware/include/fpga_regs_standard.v"
31 (output MYSTERY_SIGNAL,
42 input wire [11:0] rx_a_a,
43 input wire [11:0] rx_b_a,
44 input wire [11:0] rx_a_b,
45 input wire [11:0] rx_b_b,
47 output wire [13:0] tx_a,
48 output wire [13:0] tx_b,
55 input wire [2:0] usbctl,
56 output wire [1:0] usbrdy,
57 inout [15:0] usbdata, // NB Careful, inout
59 // These are the general purpose i/o's that go to the daughterboard slots
60 inout wire [15:0] io_tx_a,
61 inout wire [15:0] io_tx_b,
62 inout wire [15:0] io_rx_a,
63 inout wire [15:0] io_rx_b
65 wire [15:0] debugdata,debugctrl;
66 assign MYSTERY_SIGNAL = 1'b0;
74 wire have_space, have_pkt_rdy;
75 assign usbrdy[0] = have_space;
76 assign usbrdy[1] = have_pkt_rdy;
78 wire tx_underrun, rx_overrun;
79 wire clear_status = FX2_1;
80 assign FX2_2 = rx_overrun;
81 assign FX2_3 = tx_underrun;
83 wire [15:0] usbdata_out;
85 wire [3:0] dac0mux,dac1mux,dac2mux,dac3mux;
88 wire [3:0] rx_numchan;
90 wire [15:0] tx_debugbus, rx_debugbus;
92 wire enable_tx, enable_rx;
93 wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset;
96 // Tri-state bus macro
97 bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) );
99 assign clk64 = master_clk;
101 wire [15:0] ch0tx,ch1tx,ch2tx,ch3tx;
102 wire [15:0] ch0rx,ch1rx,ch2rx,ch3rx,ch4rx,ch5rx,ch6rx,ch7rx;
105 wire [6:0] serial_addr;
106 wire [31:0] serial_data;
108 /////////////////////////////////////////////////////////////////////////////////////////////////////
110 setting_reg #(`FR_TX_MUX)
111 sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
112 .out({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan}));
114 //////////////////////////////////////////////////////////////////////////////////////////////////////
115 // Signal Processing Chain
119 wire [15:0] i,q,ip,qp;
123 always @(posedge clk64)
124 adc0 <= #1 {rx_a_a[11],rx_a_a[11:0],3'b0};
126 wire [15:0] adc0_corr;
127 rx_dcoffset #(0)rx_dcoffset0(.clock(clk64),.enable(1'b1),.reset(reset),.adc_in(adc0),.adc_out(adc0_corr),
128 .serial_addr(7'd0),.serial_data(32'd0),.serial_strobe(1'b0));
130 //wire [63:0] filt_debug = 64'd0;
132 mrfm_proc mrfm_proc(.clock(clk64),.reset(rx_dsp_reset),.enable(enable_rx),
133 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
134 .signal_in(adc0_corr),.signal_out(dac0),.sync_out(sync_out),
135 .i(i),.q(q),.ip(ip),.qp(qp),.strobe_out(strobe_out),
136 .debugbus( /* filt_debug */ ));
139 assign TXSYNC_A = txsync;
140 assign TXSYNC_B = txsync;
142 assign tx_a = dac0[15:2];
144 //////////////////////////////////////////////////////////////////////////////////////////////////
145 // Data Collection on RX Buffer
147 assign rx_numchan[0] = 1'b0;
148 setting_reg #(`FR_RX_MUX) sr_rxmux(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),
149 .in(serial_data),.out(rx_numchan[3:1]));
152 ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
153 .usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun),
154 .channels(rx_numchan),
157 .ch_4(16'd0),.ch_5(16'd0),
158 .ch_6(16'd0),.ch_7(16'd0),
159 .rxclk(clk64),.rxstrobe(strobe_out),
160 .clear_status(clear_status),
161 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
162 .debugbus(rx_debugbus) );
164 //////////////////////////////////////////////////////////////////////////////
167 wire [31:0] capabilities = 32'd2;
170 ( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI),
171 .enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO),
172 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
173 .readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a) );
175 wire [15:0] reg_0,reg_1,reg_2,reg_3;
176 master_control master_control
177 ( .master_clk(clk64),.usbclk(usbclk),
178 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
179 .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset),
180 .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
181 .enable_tx(enable_tx),.enable_rx(enable_rx),
182 .interp_rate(interp_rate),.decim_rate(decim_rate),
183 .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp),
184 .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
186 .debug_0({15'd0,sync_out}), //filt_debug[63:48]),
187 .debug_1({15'd0,sync_out}), //filt_debug[47:32]),
188 .debug_2({15'd0,sync_out}), //filt_debug[31:16]),
189 .debug_3({15'd0,sync_out}), //filt_debug[15:0]),
190 .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) );
193 (.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b),
194 .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3),
195 .clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset),
196 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));