3 # This is mrfm_fft_sos.py
4 # Modification of Matt's mrfm_fft.py that reads filter coefs from file
6 # Copyright 2004,2005 Free Software Foundation, Inc.
8 # This file is part of GNU Radio
10 # GNU Radio is free software; you can redistribute it and/or modify
11 # it under the terms of the GNU General Public License as published by
12 # the Free Software Foundation; either version 2, or (at your option)
15 # GNU Radio is distributed in the hope that it will be useful,
16 # but WITHOUT ANY WARRANTY; without even the implied warranty of
17 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 # GNU General Public License for more details.
20 # You should have received a copy of the GNU General Public License
21 # along with GNU Radio; see the file COPYING. If not, write to
22 # the Free Software Foundation, Inc., 51 Franklin Street,
23 # Boston, MA 02110-1301, USA.
26 from gnuradio import gr, gru
27 from gnuradio import usrp
29 class source_c(usrp.source_c):
30 def __init__(self,fpga_filename):
31 usrp.source_c.__init__(self,which=0, decim_rate=64, nchan=2, mux=0x32103210, mode=0,
32 fpga_filename=fpga_filename)
34 self._write_9862(0,2,0x80) # Bypass ADC buffer, minimum gain
35 self._write_9862(0,3,0x80) # Bypass ADC buffer, minimum gain
37 self._write_9862(0,8,0) # TX PWR Down
38 self._write_9862(0,10,0) # DAC offset
39 self._write_9862(0,11,0) # DAC offset
40 self._write_9862(0,14,0x80) # gain
41 self._write_9862(0,16,0xff) # pga
42 self._write_9862(0,18,0x0c) # TX IF
43 self._write_9862(0,19,0x01) # TX Digital
44 self._write_9862(0,20,0x00) # TX Mod
46 # max/min values are +/-2, so scale is set to make 2 = 32767
48 self._write_fpga_reg(69,0x0e) # debug mux
49 self._write_fpga_reg(5,-1)
50 self._write_fpga_reg(7,-1)
51 self._write_oe(0,0xffff, 0xffff)
52 self._write_oe(1,0xffff, 0xffff)
53 self._write_fpga_reg(14,0xf)
57 def set_coeffs(self,frac_bits,b20,b10,b00,a20,a10,b21,b11,b01,a21,a11):
58 def make_val(address,value):
59 return (address << 16) | (value & 0xffff)
61 # gain, scale already included in a's and b's from file
63 self._write_fpga_reg(67,make_val(1,b20))
64 self._write_fpga_reg(67,make_val(2,b10))
65 self._write_fpga_reg(67,make_val(3,b00))
66 self._write_fpga_reg(67,make_val(4,a20))
67 self._write_fpga_reg(67,make_val(5,a10))
69 self._write_fpga_reg(67,make_val(7,b21))
70 self._write_fpga_reg(67,make_val(8,b11))
71 self._write_fpga_reg(67,make_val(9,b01))
72 self._write_fpga_reg(67,make_val(10,a21))
73 self._write_fpga_reg(67,make_val(11,a11))
75 self._write_fpga_reg(68,frac_bits) # Shift
77 print "Biquad 0 : b2=%d b1=%d b0=%d a2=%d a1=%d" % (b20,b10,b00,a20,a10)
78 print "Biquad 1 : b2=%d b1=%d b0=%d a2=%d a1=%d" % (b21,b11,b01,a21,a11)
80 def set_decim_rate(self,rate=None):
85 while (rate>1) and (i<257):
86 if (rate/i) * i == rate:
95 print "Failed to set DECIMATOR"
104 print "Failed to set DECIMATOR"
110 print "Failed to set DECIMATOR"
114 print "a = %d b = %d" % (a,b)
115 self._write_fpga_reg(64,(a-1)*256+(b-1)) # Set actual decimation
117 def decim_rate(self):
120 def set_center_freq(self,freq):
121 self._write_fpga_reg(65,int(-freq/64e6*65536*65536)) # set center freq
123 def set_compensator(self,a11,a12,a21,a22,shift):
124 self._write_fpga_reg(70,a11)
125 self._write_fpga_reg(71,a12)
126 self._write_fpga_reg(72,a21)
127 self._write_fpga_reg(73,a22)
128 self._write_fpga_reg(74,shift) # comp shift