3 // USRP - Universal Software Radio Peripheral
5 // Copyright (C) 2003 Matt Ettus
7 // This program is free software; you can redistribute it and/or modify
8 // it under the terms of the GNU General Public License as published by
9 // the Free Software Foundation; either version 2 of the License, or
10 // (at your option) any later version.
12 // This program is distributed in the hope that it will be useful,
13 // but WITHOUT ANY WARRANTY; without even the implied warranty of
14 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 // GNU General Public License for more details.
17 // You should have received a copy of the GNU General Public License
18 // along with this program; if not, write to the Free Software
19 // Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
22 // Interface to Cypress FX2 bus
23 // A packet is 512 Bytes. Each fifo line is 2 bytes
24 // Fifo has 1024 or 2048 lines
28 input bus_reset, // Used here for the 257-Hack to fix the FX2 bug
29 input reset, // standard DSP-side reset
32 output wire have_space,
33 output reg tx_underrun,
34 input wire [3:0] channels,
35 output reg [15:0] tx_i_0,
36 output reg [15:0] tx_q_0,
37 output reg [15:0] tx_i_1,
38 output reg [15:0] tx_q_1,
39 output reg [15:0] tx_i_2,
40 output reg [15:0] tx_q_2,
41 output reg [15:0] tx_i_3,
42 output reg [15:0] tx_q_3,
47 output [11:0] debugbus
50 wire [11:0] txfifolevel;
51 reg [8:0] write_count;
59 assign rdreq = ((load_next != channels) & !tx_empty);
61 always @(posedge txclk)
64 {tx_i_0,tx_q_0,tx_i_1,tx_q_1,tx_i_2,tx_q_2,tx_i_3,tx_q_3}
69 if(load_next != channels)
71 load_next <= #1 load_next + 4'd1;
73 4'd0 : tx_i_0 <= #1 tx_empty ? 16'd0 : fifodata;
74 4'd1 : tx_q_0 <= #1 tx_empty ? 16'd0 : fifodata;
75 4'd2 : tx_i_1 <= #1 tx_empty ? 16'd0 : fifodata;
76 4'd3 : tx_q_1 <= #1 tx_empty ? 16'd0 : fifodata;
77 4'd4 : tx_i_2 <= #1 tx_empty ? 16'd0 : fifodata;
78 4'd5 : tx_q_2 <= #1 tx_empty ? 16'd0 : fifodata;
79 4'd6 : tx_i_3 <= #1 tx_empty ? 16'd0 : fifodata;
80 4'd7 : tx_q_3 <= #1 tx_empty ? 16'd0 : fifodata;
81 endcase // case(load_next)
82 end // if (load_next != channels)
83 else if(txstrobe & (load_next == channels))
89 assign have_space = (txfifolevel <= (4095-256));
91 always @(posedge usbclk)
92 if(bus_reset) // Use bus reset because this is on usbclk
94 else if(WR & ~write_count[8])
95 write_count <= #1 write_count + 9'd1;
97 write_count <= #1 WR ? write_count : 9'b0;
100 always @(posedge txclk)
103 else if(txstrobe & (load_next != channels))
105 else if(clear_status)
111 .wrreq ( WR & ~write_count[8] ),
118 .aclr ( reset ), // asynch, so we can use either
120 .rdempty ( tx_empty ),
123 .wrusedw ( txfifolevel )
127 assign debugbus[0] = WR;
128 assign debugbus[1] = have_space;
129 assign debugbus[2] = tx_empty;
130 assign debugbus[3] = tx_full;
131 assign debugbus[4] = tx_underrun;
132 assign debugbus[5] = write_count[8];
133 assign debugbus[6] = txstrobe;
134 assign debugbus[7] = rdreq;
135 assign debugbus[11:8] = load_next;
137 endmodule // tx_buffer