3 // USRP - Universal Software Radio Peripheral
5 // Copyright (C) 2003,2004 Matt Ettus
7 // This program is free software; you can redistribute it and/or modify
8 // it under the terms of the GNU General Public License as published by
9 // the Free Software Foundation; either version 2 of the License, or
10 // (at your option) any later version.
12 // This program is distributed in the hope that it will be useful,
13 // but WITHOUT ANY WARRANTY; without even the implied warranty of
14 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 // GNU General Public License for more details.
17 // You should have received a copy of the GNU General Public License
18 // along with this program; if not, write to the Free Software
19 // Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
24 // Serial Control Bus from Cypress chip
32 inout wire serial_data_out,
33 output reg [6:0] serial_addr,
34 output reg [31:0] serial_data,
35 output wire serial_strobe,
36 input wire [31:0] readback_0,
37 input wire [31:0] readback_1,
38 input wire [31:0] readback_2,
39 input wire [31:0] readback_3,
40 input wire [31:0] readback_4,
41 input wire [31:0] readback_5,
42 input wire [31:0] readback_6,
43 input wire [31:0] readback_7
50 assign serial_data_out = is_read ? serial_data[31] : 1'bz;
52 always @(posedge serial_clock, posedge reset, negedge enable)
57 else if(ser_ctr == 39)
60 ser_ctr <= #1 ser_ctr + 8'd1;
62 always @(posedge serial_clock, posedge reset, negedge enable)
67 else if((ser_ctr == 7)&&(serial_addr[6]==1))
70 always @(posedge serial_clock, posedge reset)
73 serial_addr <= #1 7'b0;
74 serial_data <= #1 32'b0;
75 write_done <= #1 1'b0;
79 //serial_addr <= #1 7'b0;
80 //serial_data <= #1 32'b0;
81 write_done <= #1 1'b0;
85 if(~is_read && (ser_ctr == 39))
86 write_done <= #1 1'b1;
88 write_done <= #1 1'b0;
89 if(is_read & (ser_ctr==8))
91 7'd1: serial_data <= #1 readback_0;
92 7'd2: serial_data <= #1 readback_1;
93 7'd3: serial_data <= #1 readback_2;
94 7'd4: serial_data <= #1 readback_3;
95 7'd5: serial_data <= #1 readback_4;
96 7'd6: serial_data <= #1 readback_5;
97 7'd7: serial_data <= #1 readback_6;
98 7'd8: serial_data <= #1 readback_7;
99 default: serial_data <= #1 32'd0;
100 endcase // case(serial_addr)
101 else if(ser_ctr >= 8)
102 serial_data <= #1 {serial_data[30:0],serial_data_in};
104 serial_addr <= #1 {serial_addr[5:0],serial_data_in};
105 end // else: !if(~enable)
107 reg enable_d1, enable_d2;
108 always @(posedge master_clk)
110 enable_d1 <= #1 enable;
111 enable_d2 <= #1 enable_d1;
114 assign serial_strobe = enable_d2 & ~enable_d1;
116 endmodule // serial_io