3 module rssi (input clock, input reset, input enable,
4 input [11:0] adc, output [15:0] rssi, output [15:0] over_count);
6 wire over_hi = (adc == 12'h7FF);
7 wire over_lo = (adc == 12'h800);
8 wire over = over_hi | over_lo;
10 reg [25:0] over_count_int;
11 always @(posedge clock)
13 over_count_int <= #1 26'd0;
15 over_count_int <= #1 over_count_int + (over ? 26'd65535 : 26'd0) - over_count_int[25:10];
17 assign over_count = over_count_int[25:10];
19 wire [11:0] abs_adc = adc[11] ? ~adc : adc;
22 always @(posedge clock)
26 rssi_int <= #1 rssi_int + abs_adc - rssi_int[25:10];
28 assign rssi = rssi_int[25:10];