3 // USRP - Universal Software Radio Peripheral
5 // Copyright (C) 2006 Martin Dudok van Heel
7 // This program is free software; you can redistribute it and/or modify
8 // it under the terms of the GNU General Public License as published by
9 // the Free Software Foundation; either version 2 of the License, or
10 // (at your option) any later version.
12 // This program is distributed in the hope that it will be useful,
13 // but WITHOUT ANY WARRANTY; without even the implied warranty of
14 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 // GNU General Public License for more details.
17 // You should have received a copy of the GNU General Public License
18 // along with this program; if not, write to the Free Software
19 // Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
22 `include "../../../firmware/include/fpga_regs_common.v"
23 `include "../../../firmware/include/fpga_regs_standard.v"
24 // Clock, enable, and reset controls for whole system
25 // Modified version to enable multi_usrp synchronisation
27 module master_control_multi
28 ( input master_clk, input usbclk,
29 input wire [6:0] serial_addr, input wire [31:0] serial_data, input wire serial_strobe,
30 input wire rx_slave_sync,
31 output tx_bus_reset, output rx_bus_reset,
32 output wire tx_dsp_reset, output wire rx_dsp_reset,
33 output wire enable_tx, output wire enable_rx,
35 output wire [7:0] interp_rate, output wire [7:0] decim_rate,
36 output tx_sample_strobe, output strobe_interp,
37 output rx_sample_strobe, output strobe_decim,
39 input wire [15:0] debug_0,input wire [15:0] debug_1,input wire [15:0] debug_2,input wire [15:0] debug_3,
40 output wire [15:0] reg_0, output wire [15:0] reg_1, output wire [15:0] reg_2, output wire [15:0] reg_3
43 wire [15:0] reg_1_std;
45 master_control master_control_standard
46 ( .master_clk(master_clk),.usbclk(usbclk),
47 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
48 .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset),
49 .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
50 .enable_tx(enable_tx),.enable_rx(enable_rx),
51 .interp_rate(interp_rate),.decim_rate(decim_rate),
52 .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp),
53 .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
55 .debug_0(debug_0),.debug_1(debug_1),
56 .debug_2(debug_2),.debug_3(debug_3),
57 .reg_0(reg_0),.reg_1(reg_1_std),.reg_2(reg_2),.reg_3(reg_3) );
59 // FIXME need a separate reset for all control settings
60 // Master/slave Controls assignments
61 wire [7:0] rx_master_slave_controls;
62 setting_reg_masked #(`FR_RX_MASTER_SLAVE) sr_rx_mstr_slv_ctrl(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(rx_master_slave_controls));
64 assign sync_rx = rx_master_slave_controls[`bitnoFR_RX_SYNC] | (rx_master_slave_controls[`bitnoFR_RX_SYNC_SLAVE] & rx_slave_sync);
65 //sync if we are told by master_control or if we get a hardware slave sync
66 //TODO There can be a one sample difference between master and slave sync.
67 // Maybe use a register for sync_rx which uses the (neg or pos) edge of master_clock and/or rx_slave_sync to trigger
68 // Or even use a seperate sync_rx_out and sync_rx_internal (which lags behind)
69 //TODO make output pin not hardwired
70 assign reg_1 ={(rx_master_slave_controls[`bitnoFR_RX_SYNC_MASTER])? sync_rx:reg_1_std[15],reg_1_std[14:0]};
73 endmodule // master_control