3 module ram32_2sum (input clock, input write,
4 input [4:0] wr_addr, input [15:0] wr_data,
5 input [4:0] rd_addr1, input [4:0] rd_addr2,
6 output reg [15:0] sum);
8 reg [15:0] ram_array [0:31];
11 always @(posedge clock)
13 ram_array[wr_addr] <= #1 wr_data;
15 assign sum_int = ram_array[rd_addr1] + ram_array[rd_addr2];
17 always @(posedge clock)
18 sum <= #1 sum_int[16:1] + (sum_int[16]&sum_int[0]);
21 endmodule // ram32_2sum