3 module ram16_2port (input clock, input write,
4 input [3:0] wr_addr, input [15:0] wr_data,
5 input [3:0] rd_addr1, output reg [15:0] rd_data1,
6 input [3:0] rd_addr2, output reg [15:0] rd_data2);
8 reg [15:0] ram_array [0:31];
10 always @(posedge clock)
11 rd_data1 <= #1 ram_array[rd_addr1];
13 always @(posedge clock)
14 rd_data2 <= #1 ram_array[rd_addr2];
16 always @(posedge clock)
18 ram_array[wr_addr] <= #1 wr_data;
20 endmodule // ram16_2port