3 module mac (input clock, input reset, input enable, input clear,
4 input signed [15:0] x, input signed [15:0] y,
5 input [7:0] shift, output [15:0] z );
7 reg signed [30:0] product;
8 reg signed [39:0] z_int;
9 reg signed [15:0] z_shift;
12 always @(posedge clock)
13 enable_d1 <= #1 enable;
15 always @(posedge clock)
19 z_int <= #1 z_int + {{9{product[30]}},product};
21 always @(posedge clock)
24 always @* // FIXME full case? parallel case?
26 //8'd0 : z_shift <= z_int[39:24];
27 //8'd1 : z_shift <= z_int[38:23];
28 //8'd2 : z_shift <= z_int[37:22];
29 //8'd3 : z_shift <= z_int[36:21];
30 //8'd4 : z_shift <= z_int[35:20];
31 //8'd5 : z_shift <= z_int[34:19];
32 8'd6 : z_shift <= z_int[33:18];
33 8'd7 : z_shift <= z_int[32:17];
34 8'd8 : z_shift <= z_int[31:16];
35 8'd9 : z_shift <= z_int[30:15];
36 8'd10 : z_shift <= z_int[29:14];
37 8'd11 : z_shift <= z_int[28:13];
38 //8'd12 : z_shift <= z_int[27:12];
39 //8'd13 : z_shift <= z_int[26:11];
40 //8'd14 : z_shift <= z_int[25:10];
41 //8'd15 : z_shift <= z_int[24:9];
42 //8'd16 : z_shift <= z_int[23:8];
43 //8'd17 : z_shift <= z_int[22:7];
44 //8'd18 : z_shift <= z_int[21:6];
45 //8'd19 : z_shift <= z_int[20:5];
46 //8'd20 : z_shift <= z_int[19:4];
47 //8'd21 : z_shift <= z_int[18:3];
48 //8'd22 : z_shift <= z_int[17:2];
49 //8'd23 : z_shift <= z_int[16:1];
50 //8'd24 : z_shift <= z_int[15:0];
51 default : z_shift <= z_int[15:0];
52 endcase // case(shift)
54 // FIXME do we need to saturate?
56 assign z = z_int[15:0];