4 (input clock, input reset, input enable,
5 input strobe_in, input strobe_out,
6 input [15:0] signal_in_i, input [15:0] signal_in_q,
7 output reg [15:0] signal_out_i, output reg [15:0] signal_out_q,
8 output wire [12:0] debug);
10 wire [15:0] coeff_ram_out;
11 wire [15:0] data_ram_out_i;
12 wire [15:0] data_ram_out_q;
14 wire [3:0] data_rd_addr;
15 reg [3:0] data_wr_addr;
16 reg [2:0] coeff_rd_addr;
20 wire [15:0] mac_out_i;
21 wire [15:0] mac_out_q;
22 reg [15:0] delayed_middle_i, delayed_middle_q;
23 wire [7:0] shift = 8'd9;
27 wire [15:0] data_ram_out_i_b;
29 always @(posedge clock)
31 stb_out_happened <= #1 1'b0;
33 stb_out_happened <= #1 1'b1;
35 assign debug = {filt_done,data_rd_addr,data_wr_addr,coeff_rd_addr};
37 wire [15:0] signal_out_i = stb_out_happened ? mac_out_i : delayed_middle_i;
38 wire [15:0] signal_out_q = stb_out_happened ? mac_out_q : delayed_middle_q;
40 /* always @(posedge clock)
43 signal_out_i <= #1 16'd0;
44 signal_out_q <= #1 16'd0;
48 signal_out_i <= #1 delayed_middle_i; // Multiply by 1 for middle coeff
49 signal_out_q <= #1 delayed_middle_q;
51 //else if(filt_done&stb_out_happened)
52 else if(stb_out_happened)
54 signal_out_i <= #1 mac_out_i;
55 signal_out_q <= #1 mac_out_q;
59 always @(posedge clock)
61 coeff_rd_addr <= #1 3'd0;
62 else if(coeff_rd_addr != 3'd0)
63 coeff_rd_addr <= #1 coeff_rd_addr + 3'd1;
65 coeff_rd_addr <= #1 3'd1;
68 always@(posedge clock)
69 filt_done_d1 <= #1 filt_done;
71 always @(posedge clock)
73 data_wr_addr <= #1 4'd0;
75 else if(filt_done & ~filt_done_d1)
76 data_wr_addr <= #1 data_wr_addr + 4'd1;
78 always @(posedge clock)
79 if(coeff_rd_addr == 3'd7)
81 delayed_middle_i <= #1 data_ram_out_i_b;
82 // delayed_middle_q <= #1 data_ram_out_q_b;
85 // always @(posedge clock)
87 // data_rd_addr <= #1 4'd0;
89 // data_rd_addr <= #1 data_wr_addr + 4'd1;
90 // else if(!filt_done)
91 // data_rd_addr <= #1 data_rd_addr + 4'd1;
93 // data_rd_addr <= #1 data_wr_addr;
95 wire [3:0] data_rd_addr1 = data_wr_addr + {1'b0,coeff_rd_addr};
96 wire [3:0] data_rd_addr2 = data_wr_addr + 15 - {1'b0,coeff_rd_addr};
97 // always @(posedge clock)
99 // filt_done <= #1 1'b1;
100 // else if(strobe_in)
101 // filt_done <= #1 1'b0;
102 // else if(coeff_rd_addr == 4'd0)
103 // filt_done <= #1 1'b1;
105 assign filt_done = (coeff_rd_addr == 3'd0);
107 coeff_ram coeff_ram ( .clock(clock),.rd_addr({1'b0,coeff_rd_addr}),.rd_data(coeff_ram_out) );
109 ram16_2sum data_ram_i ( .clock(clock),.write(strobe_in),.wr_addr(data_wr_addr),.wr_data(signal_in_i),
110 .rd_addr1(data_rd_addr1),.rd_addr2(data_rd_addr2),.rd_data(data_ram_out_i_b),.sum(data_ram_out_i));
112 ram16_2sum data_ram_q ( .clock(clock),.write(strobe_in),.wr_addr(data_wr_addr),.wr_data(signal_in_q),
113 .rd_addr1(data_rd_addr1),.rd_addr2(data_rd_addr2),.rd_data(data_ram_out_q));
115 mac mac_i (.clock(clock),.reset(reset),.enable(~filt_done),.clear(strobe_in),
116 .x(data_ram_out_i),.y(coeff_ram_out),.shift(shift),.z(mac_out_i) );
118 mac mac_q (.clock(clock),.reset(reset),.enable(~filt_done),.clear(strobe_in),
119 .x(data_ram_out_q),.y(coeff_ram_out),.shift(shift),.z(mac_out_q) );
121 endmodule // halfband_interp