3 module coeff_rom (input clock, input [2:0] addr, output reg [15:0] data);
5 always @(posedge clock)
7 3'd0 : data <= #1 -16'd49;
8 3'd1 : data <= #1 16'd165;
9 3'd2 : data <= #1 -16'd412;
10 3'd3 : data <= #1 16'd873;
11 3'd4 : data <= #1 -16'd1681;
12 3'd5 : data <= #1 16'd3135;
13 3'd6 : data <= #1 -16'd6282;
14 3'd7 : data <= #1 16'd20628;
17 endmodule // coeff_rom