3 // USRP - Universal Software Radio Peripheral
5 // Copyright (C) 2003 Matt Ettus
7 // This program is free software; you can redistribute it and/or modify
8 // it under the terms of the GNU General Public License as published by
9 // the Free Software Foundation; either version 2 of the License, or
10 // (at your option) any later version.
12 // This program is distributed in the hope that it will be useful,
13 // but WITHOUT ANY WARRANTY; without even the implied warranty of
14 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 // GNU General Public License for more details.
17 // You should have received a copy of the GNU General Public License
18 // along with this program; if not, write to the Free Software
19 // Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
23 // Vendor Independent FIFO module
24 // Width and Depth should be parameterizable
25 // Asynchronous clocks for each side
26 // Read side is read-acknowledge, not read-request
27 // FIFO does not enforce "don't write when full, don't read when empty"
28 // That is up to the connecting modules
29 // The FIFO only holds 2^N-1 entries, not 2^N
31 module fifo (reset,data,write,wrclk,wr_used,q,read_ack,rdclk,rd_used);
35 input reset; // Asynchronous
36 input [width-1:0] data;
39 output [depth-1:0] wr_used;
43 output [depth-1:0] rd_used;
45 reg [depth-1:0] read_addr, write_addr,
46 read_addr_gray, read_addr_gray_sync,
47 write_addr_gray, write_addr_gray_sync;
49 // Pseudo-dual-port RAM
50 dpram #(.depth(10),.width(width),.size(1024))
51 fifo_ram (.wclk(wrclk),.wdata(data),.waddr(write_addr),.wen(write),
52 .rclk(rdclk), .rdata(q),.raddr(read_addr) );
54 wire [depth-1:0] wag,rag;
56 // Keep track of own side's pointer
57 always @(posedge wrclk or posedge reset)
58 if(reset) write_addr <= #1 0;
59 else if(write) write_addr <= #1 write_addr + 1;
61 always @(posedge rdclk or posedge reset)
62 if(reset) read_addr <= #1 0;
63 else if(read_ack) read_addr <= #1 read_addr + 1;
65 // Convert own side pointer to gray
66 bin2gray #(depth) write_b2g (write_addr,wag);
67 bin2gray #(depth) read_b2g (read_addr,rag);
70 always @(posedge wrclk or posedge reset)
71 if(reset) write_addr_gray <= #1 0;
72 else write_addr_gray <= #1 wag;
74 always @(posedge rdclk or posedge reset)
75 if(reset) read_addr_gray <= #1 0;
76 else read_addr_gray <= #1 rag;
78 // Send it to other side and latch
79 always @(posedge wrclk or posedge reset)
80 if(reset) read_addr_gray_sync <= #1 0;
81 else read_addr_gray_sync <= #1 read_addr_gray;
83 always @(posedge rdclk or posedge reset)
84 if(reset) write_addr_gray_sync <= #1 0;
85 else write_addr_gray_sync <= #1 write_addr_gray;
87 wire [depth-1:0] write_addr_sync, read_addr_sync;
89 // Convert back to binary
90 gray2bin #(depth) write_g2b (write_addr_gray_sync, write_addr_sync);
91 gray2bin #(depth) read_g2b (read_addr_gray_sync, read_addr_sync);
93 assign rd_used = write_addr_sync - read_addr;
94 assign wr_used = write_addr - read_addr_sync;
98 module bin2gray(bin_val,gray_val);
100 input [width-1:0] bin_val;
101 output reg [width-1:0] gray_val;
107 gray_val[width-1] = bin_val[width-1];
108 for(i=0;i<width-1;i=i+1)
109 gray_val[i] = bin_val[i] ^ bin_val[i+1];
111 endmodule // bin2gray
113 module gray2bin(gray_val,bin_val);
115 input [width-1:0] gray_val;
116 output reg [width-1:0] bin_val;
122 bin_val[width-1] = gray_val[width-1];
123 for(i=width-2;i>=0;i=i-1)
124 bin_val[i] = bin_val[i+1] ^ gray_val[i];
126 endmodule // gray2bin