3 // USRP - Universal Software Radio Peripheral
5 // Copyright (C) 2003 Matt Ettus
7 // This program is free software; you can redistribute it and/or modify
8 // it under the terms of the GNU General Public License as published by
9 // the Free Software Foundation; either version 2 of the License, or
10 // (at your option) any later version.
12 // This program is distributed in the hope that it will be useful,
13 // but WITHOUT ANY WARRANTY; without even the implied warranty of
14 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 // GNU General Public License for more details.
17 // You should have received a copy of the GNU General Public License
18 // along with this program; if not, write to the Free Software
19 // Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
23 module cic_interp(clock,reset,enable,rate,strobe_in,strobe_out,signal_in,signal_out);
26 parameter log2_of_max_rate = 7;
27 parameter maxbitgain = (N-1)*log2_of_max_rate;
33 input strobe_in,strobe_out;
34 input [bw-1:0] signal_in;
35 wire [bw-1:0] signal_in;
36 output [bw-1:0] signal_out;
37 wire [bw-1:0] signal_out;
39 wire [bw+maxbitgain-1:0] signal_in_ext;
40 reg [bw+maxbitgain-1:0] integrator [0:N-1];
41 reg [bw+maxbitgain-1:0] differentiator [0:N-1];
42 reg [bw+maxbitgain-1:0] pipeline [0:N-1];
46 sign_extend #(bw,bw+maxbitgain)
47 ext_input (.in(signal_in),.out(signal_in_ext));
49 wire clear_me = reset | ~enable;
50 //FIXME Note that this section has pipe and diff reversed
51 // It still works, but is confusing
52 always @(posedge clock)
55 integrator[i] <= #1 0;
56 else if (enable & strobe_out)
59 integrator[0] <= #1 integrator[0] + pipeline[N-1];
61 integrator[i] <= #1 integrator[i] + integrator[i-1];
64 always @(posedge clock)
69 differentiator[i] <= #1 0;
73 else if (enable && strobe_in)
75 differentiator[0] <= #1 signal_in_ext;
76 pipeline[0] <= #1 signal_in_ext - differentiator[0];
79 differentiator[i] <= #1 pipeline[i-1];
80 pipeline[i] <= #1 pipeline[i-1] - differentiator[i];
84 wire [bw+maxbitgain-1:0] signal_out_unnorm = integrator[N-1];
87 cic_int_shifter(rate,signal_out_unnorm,signal_out);
89 endmodule // cic_interp