3 // USRP - Universal Software Radio Peripheral
5 // Copyright (C) 2003 Matt Ettus
7 // This program is free software; you can redistribute it and/or modify
8 // it under the terms of the GNU General Public License as published by
9 // the Free Software Foundation; either version 2 of the License, or
10 // (at your option) any later version.
12 // This program is distributed in the hope that it will be useful,
13 // but WITHOUT ANY WARRANTY; without even the implied warranty of
14 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 // GNU General Public License for more details.
17 // You should have received a copy of the GNU General Public License
18 // along with this program; if not, write to the Free Software
19 // Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
24 ( clock,reset,enable,rate,strobe_in,strobe_out,signal_in,signal_out);
27 parameter log2_of_max_rate = 8;
28 parameter maxbitgain = N * log2_of_max_rate;
34 input strobe_in,strobe_out;
35 input [bw-1:0] signal_in;
36 output [bw-1:0] signal_out;
37 reg [bw-1:0] signal_out;
39 wire [bw+maxbitgain-1:0] signal_in_ext;
40 reg [bw+maxbitgain-1:0] integrator [0:N-1];
41 reg [bw+maxbitgain-1:0] differentiator [0:N-1];
42 reg [bw+maxbitgain-1:0] pipeline [0:N-1];
43 reg [bw+maxbitgain-1:0] sampler;
47 sign_extend #(bw,bw+maxbitgain)
48 ext_input (.in(signal_in),.out(signal_in_ext));
50 always @(posedge clock)
53 integrator[i] <= #1 0;
54 else if (enable && strobe_in)
56 integrator[0] <= #1 integrator[0] + signal_in_ext;
58 integrator[i] <= #1 integrator[i] + integrator[i-1];
61 always @(posedge clock)
68 differentiator[i] <= #1 0;
71 else if (enable && strobe_out)
73 sampler <= #1 integrator[N-1];
74 differentiator[0] <= #1 sampler;
75 pipeline[0] <= #1 sampler - differentiator[0];
78 differentiator[i] <= #1 pipeline[i-1];
79 pipeline[i] <= #1 pipeline[i-1] - differentiator[i];
81 end // if (enable && strobe_out)
83 wire [bw+maxbitgain-1:0] signal_out_unnorm = pipeline[N-1];
85 // Output Scaling to same width as input
86 function [2:0] log_ceil;
88 log_ceil = val[6] ? 3'd7 : val[5] ? 3'd6 : val[4] ? 3'd5 :
89 val[3] ? 3'd4 : val[2] ? 3'd3 : val[1] ? 3'd2 : 3'd1;
90 endfunction // log_ceil
92 wire [2:0] shift = log_ceil(rate);
96 3'd2 : signal_out = signal_out_unnorm[2*N+bw-1:2*N]; // Decim by 4
97 3'd3 : signal_out = signal_out_unnorm[3*N+bw-1:3*N];
98 3'd4 : signal_out = signal_out_unnorm[4*N+bw-1:4*N];
99 3'd5 : signal_out = signal_out_unnorm[5*N+bw-1:5*N];
100 3'd6 : signal_out = signal_out_unnorm[6*N+bw-1:6*N];
101 3'd7 : signal_out = signal_out_unnorm[7*N+bw-1:7*N];
102 default : signal_out = signal_out_unnorm[7*N+bw-1:7*N];
103 endcase // case(shift)
105 endmodule // cic_decim