3 // USRP - Universal Software Radio Peripheral
5 // Copyright (C) 2003 Matt Ettus
7 // This program is free software; you can redistribute it and/or modify
8 // it under the terms of the GNU General Public License as published by
9 // the Free Software Foundation; either version 2 of the License, or
10 // (at your option) any later version.
12 // This program is distributed in the hope that it will be useful,
13 // but WITHOUT ANY WARRANTY; without even the implied warranty of
14 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 // GNU General Public License for more details.
17 // You should have received a copy of the GNU General Public License
18 // along with this program; if not, write to the Free Software
19 // Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
22 // Interface to Cypress FX2 bus
23 // A packet is 512 Bytes. Each fifo line is 4 bytes
24 // Fifo has 1024 or 2048 lines
29 inout [15:0] usbdata, // TRISTATE
30 input wire [5:0] usbctl,
31 output wire [5:0] usbrdy,
38 output [11:0] debugbus,
42 parameter IN_CHANNELS = 1;
43 parameter OUT_CHANNELS = 1;
44 parameter bitmask = (IN_CHANNELS*2)-1;
46 wire have_space, have_pkt_rdy;
48 reg tx_underrun, rx_overrun;
50 assign WR = usbctl[0];
51 assign RD = usbctl[1];
52 assign OE = usbctl[2];
54 assign usbrdy[0] = have_space;
55 assign usbrdy[1] = have_pkt_rdy;
56 assign usbrdy[2] = tx_underrun;
57 assign usbrdy[3] = rx_overrun;
59 reg [IN_CHANNELS*2*16-1:0] fifo_in;
60 wire [OUT_CHANNELS*2*16-1:0] fifo_out;
62 wire [15:0] usbdata_in = usbdata;
69 reg [15:0] usbdata_out;
70 wire [10:0] txfifolevel,rxfifolevel;
71 reg [8:0] write_count;
79 // Tri-state bus macro
80 bustri bustri(.data(usbdata_out),
84 //////////////////////////////////////////////
85 // TX Side (USB --> DAC)
86 always @(posedge usbclk, posedge reset)
94 if(WR & ~write_count[8])
97 1'b0 : fifo_in[31:16] <= #1 usbdata_in; // I
98 1'b1 : fifo_in[15:0] <= #1 usbdata_in; // Q
100 write_count <= #1 write_count + 9'd1;
103 write_count <= #1 WR ? write_count : 9'b0;
106 always @(posedge usbclk)
110 if(write_count[0] && ~write_count[8] && WR)
115 assign rdreq = txstrobe & !tx_empty;
116 assign txdata = tx_empty ? 32'b0 : txd;
118 always @(posedge txclk)
121 else if(txstrobe & tx_empty)
123 else if(clear_status)
126 fifo_1c_2k txfifo (.data ( fifo_in ),
136 .rdempty ( tx_empty ),
139 .wrusedw ( txfifolevel )
142 assign have_space = (txfifolevel <= (2048-128));
144 //////////////////////////////
145 // Receive FIFO (ADC --> USB)
147 always @(posedge rxclk)
150 else if(rxstrobe & rx_full)
152 else if(clear_status)
155 always @(select_out, fifo_out)
157 0 : usbdata_out = fifo_out[31:16]; // I
158 1 : usbdata_out = fifo_out[15:0]; // Q
162 always @(posedge usbclk, posedge reset)
164 usbdata_out <= #1 16'b0;
167 usbdata_out = fifo_out[31:16];
169 usbdata_out = fifo_out[15:0];
172 always @(negedge usbclk, posedge reset)
174 select_out <= #1 1'b0;
176 select_out <= #1 1'b0;
178 select_out <= #1 ~select_out;
180 fifo_1c_2k rxfifo (.data ( rxdata ), // counter ),
181 .wrreq (rxstrobe & ~rx_full ),
185 .rdreq ( select_out ),// & RD ), // FIXME
190 .rdempty ( rx_empty ),
191 .rdusedw ( rxfifolevel ),
196 assign have_pkt_rdy = (rxfifolevel >= 128);
199 assign debugbus[0] = tx_underrun;
200 assign debugbus[1] = rx_overrun;
201 assign debugbus[2] = tx_empty;
202 assign debugbus[3] = tx_full;
203 assign debugbus[4] = rx_empty;
204 assign debugbus[5] = rx_full;
205 assign debugbus[6] = txstrobe;
206 assign debugbus[7] = rxstrobe;
207 assign debugbus[8] = select_out;
208 assign debugbus[9] = rxstrobe & ~rx_full;
209 assign debugbus[10] = have_space;
210 assign debugbus[11] = have_pkt_rdy;
212 endmodule // bus_interface