2 // Model of Pipelined [ZBT] Synchronous SRAM
4 module ssram(clock,addr,data,wen,ce);
5 parameter addrbits = 19;
6 parameter depth = 524288;
9 input [addrbits-1:0] addr;
14 reg [35:0] ram [0:depth-1];
17 reg write_d1,write_d2;
18 reg [addrbits-1:0] addr_d1,addr_d2;
20 always @(posedge clock)
22 read_d1 <= #1 ce & ~wen;
23 write_d1 <= #1 ce & wen;
25 read_d2 <= #1 read_d1;
26 write_d2 <= #1 write_d1;
27 addr_d2 <= #1 addr_d1;
30 end // always @ (posedge clock)
32 data = (ce & read_d2) ? ram[addr_d2] : 36'bz;
34 always @(posedge clock)
35 if(~ce & (write_d2 | write_d1 | wen))
36 $display("$time ERROR: RAM CE not asserted during write cycle");