1 // Model of FIFO in Altera
3 module fifo_1c_1k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
4 rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
7 parameter depth = 1024;
8 //`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
24 reg [width-1:0] mem [0:depth-1];
43 for(i=0;i<depth;i=i+1)
47 always @(posedge wrclk)
51 mem[wrptr] <= #1 data;
54 always @(posedge rdclk)
65 assign q = mem[rdptr];
69 always @(posedge wrclk)
70 wrusedw <= #1 wrptr - rdptr;
72 always @(posedge rdclk)
73 rdusedw <= #1 wrptr - rdptr;
75 assign wrempty = (wrusedw == 0);
76 assign wrfull = (wrusedw == depth-1);
78 assign rdempty = (rdusedw == 0);
79 assign rdfull = (rdusedw == depth-1);
81 endmodule // fifo_1c_1k