1 // megafunction wizard: %FIFO%
\r
2 // GENERATION: STANDARD
\r
6 // ============================================================
\r
7 // File Name: fifo_4k_18.v
\r
8 // Megafunction Name(s):
\r
11 // Simulation Library Files(s):
\r
13 // ============================================================
\r
14 // ************************************************************
\r
15 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
\r
17 // 7.1 Build 178 06/25/2007 SP 1 SJ Web Edition
\r
18 // ************************************************************
\r
21 //Copyright (C) 1991-2007 Altera Corporation
\r
22 //Your use of Altera Corporation's design tools, logic functions
\r
23 //and other software and tools, and its AMPP partner logic
\r
24 //functions, and any output files from any of the foregoing
\r
25 //(including device programming or simulation files), and any
\r
26 //associated documentation or information are expressly subject
\r
27 //to the terms and conditions of the Altera Program License
\r
28 //Subscription Agreement, Altera MegaCore Function License
\r
29 //Agreement, or other applicable license agreement, including,
\r
30 //without limitation, that your use is for the sole purpose of
\r
31 //programming logic devices manufactured by Altera and sold by
\r
32 //Altera or its authorized distributors. Please refer to the
\r
33 //applicable agreement for further details.
\r
36 // synopsys translate_off
\r
37 `timescale 1 ps / 1 ps
\r
38 // synopsys translate_on
\r
60 output [11:0] rdusedw;
\r
62 output [11:0] wrusedw;
\r
65 wire [11:0] sub_wire1;
\r
67 wire [17:0] sub_wire3;
\r
68 wire [11:0] sub_wire4;
\r
69 wire rdempty = sub_wire0;
\r
70 wire [11:0] wrusedw = sub_wire1[11:0];
\r
71 wire wrfull = sub_wire2;
\r
72 wire [17:0] q = sub_wire3[17:0];
\r
73 wire [11:0] rdusedw = sub_wire4[11:0];
\r
75 dcfifo dcfifo_component (
\r
82 .rdempty (sub_wire0),
\r
83 .wrusedw (sub_wire1),
\r
84 .wrfull (sub_wire2),
\r
86 .rdusedw (sub_wire4)
\r
87 // synopsys translate_off
\r
91 // synopsys translate_on
\r
94 dcfifo_component.add_ram_output_register = "OFF",
\r
95 dcfifo_component.clocks_are_synchronized = "FALSE",
\r
96 dcfifo_component.intended_device_family = "Cyclone",
\r
97 dcfifo_component.lpm_numwords = 4096,
\r
98 dcfifo_component.lpm_showahead = "ON",
\r
99 dcfifo_component.lpm_type = "dcfifo",
\r
100 dcfifo_component.lpm_width = 18,
\r
101 dcfifo_component.lpm_widthu = 12,
\r
102 dcfifo_component.overflow_checking = "OFF",
\r
103 dcfifo_component.underflow_checking = "OFF",
\r
104 dcfifo_component.use_eab = "ON";
\r
109 // ============================================================
\r
110 // CNX file retrieval info
\r
111 // ============================================================
\r
112 // Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
\r
113 // Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
\r
114 // Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
\r
115 // Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
\r
116 // Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
\r
117 // Retrieval info: PRIVATE: Clock NUMERIC "4"
\r
118 // Retrieval info: PRIVATE: Depth NUMERIC "4096"
\r
119 // Retrieval info: PRIVATE: Empty NUMERIC "1"
\r
120 // Retrieval info: PRIVATE: Full NUMERIC "1"
\r
121 // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
\r
122 // Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
\r
123 // Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
\r
124 // Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
\r
125 // Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
\r
126 // Retrieval info: PRIVATE: Optimize NUMERIC "2"
\r
127 // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
\r
128 // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
\r
129 // Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
\r
130 // Retrieval info: PRIVATE: UsedW NUMERIC "1"
\r
131 // Retrieval info: PRIVATE: Width NUMERIC "18"
\r
132 // Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
\r
133 // Retrieval info: PRIVATE: diff_widths NUMERIC "0"
\r
134 // Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
\r
135 // Retrieval info: PRIVATE: output_width NUMERIC "18"
\r
136 // Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
\r
137 // Retrieval info: PRIVATE: rsFull NUMERIC "0"
\r
138 // Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
\r
139 // Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
\r
140 // Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
\r
141 // Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
\r
142 // Retrieval info: PRIVATE: wsFull NUMERIC "1"
\r
143 // Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
\r
144 // Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
\r
145 // Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
\r
146 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
\r
147 // Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
\r
148 // Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
\r
149 // Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
\r
150 // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "18"
\r
151 // Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
\r
152 // Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
\r
153 // Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
\r
154 // Retrieval info: CONSTANT: USE_EAB STRING "ON"
\r
155 // Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
\r
156 // Retrieval info: USED_PORT: data 0 0 18 0 INPUT NODEFVAL data[17..0]
\r
157 // Retrieval info: USED_PORT: q 0 0 18 0 OUTPUT NODEFVAL q[17..0]
\r
158 // Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
\r
159 // Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
\r
160 // Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
\r
161 // Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]
\r
162 // Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
\r
163 // Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
\r
164 // Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
\r
165 // Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]
\r
166 // Retrieval info: CONNECT: @data 0 0 18 0 data 0 0 18 0
\r
167 // Retrieval info: CONNECT: q 0 0 18 0 @q 0 0 18 0
\r
168 // Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
\r
169 // Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
\r
170 // Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
\r
171 // Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
\r
172 // Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
\r
173 // Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
\r
174 // Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
\r
175 // Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
\r
176 // Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
\r
177 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
\r
178 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.v TRUE
\r
179 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.inc FALSE
\r
180 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.cmp FALSE
\r
181 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.bsf FALSE
\r
182 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_inst.v FALSE
\r
183 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_bb.v FALSE
\r
184 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_waveforms.html FALSE
\r
185 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_wave*.jpg FALSE
\r
186 // Retrieval info: LIB_FILE: altera_mf
\r